digsim-logic-simulator 0.22.0__py3-none-any.whl

digsim/circuit/_circuit.py

@@ -0,0 +1,329 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+Module that handles the circuit simulation of components
+"""
+
+from __future__ import annotations
+
+import heapq
+import pathlib
+from typing import Tuple
+
+from digsim.storage_model import CircuitDataClass, CircuitFileDataClass
+
+from ._waves_writer import WavesWriter
+from .components.atoms import VALUE_TYPE, Component, DigsimException, PortOutDelta
+
+
+class CircuitError(DigsimException):
+    """A circuit error class"""
+
+
+class CircuitEvent:
+    """
+    The circuit event class for storing the
+    delta events in the simulation.
+    """
+
+    def __init__(self, time_ns: int, port: PortOutDelta, value: VALUE_TYPE):
+        self._time_ns: int = time_ns
+        self._port: PortOutDelta = port
+        self._value: VALUE_TYPE = value
+
+    @property
+    def time_ns(self) -> int:
+        """Get the simulation time (ns) of this event"""
+        return self._time_ns
+
+    @property
+    def port(self) -> PortOutDelta:
+        """Get the port of this event"""
+        return self._port
+
+    @property
+    def value(self) -> VALUE_TYPE:
+        """Get the delta cycle value of this event"""
+        return self._value
+
+    def is_same_event(self, port: PortOutDelta):
+        """Return True if the in the event is the same as"""
+        return port == self._port
+
+    def update(self, time_ns: int, value: VALUE_TYPE):
+        """Update the event with a new time (ns) and a new value"""
+        self._time_ns = time_ns
+        self._value = value
+
+    def __lt__(self, other) -> bool:
+        return other.time_ns > self.time_ns
+
+    def __eq__(self, other) -> bool:
+        return (
+            isinstance(other, CircuitEvent)
+            and self._port == other._port
+            and self._time_ns == other._time_ns
+            and self._value == other._value
+        )
+
+
+class Circuit:
+    """Class thay handles the circuit simulation"""
+
+    def __init__(self, name: str | None = None, vcd: str | None = None):
+        self._components: dict[str, Component] = {}
+        self._circuit_events: list[CircuitEvent] = []
+        self._events_by_port: dict[PortOutDelta, CircuitEvent] = {}
+        self._name: str | None = name
+        self._time_ns: int = 0
+        self._folder: str | None = None
+        self._vcd: WavesWriter | None = None
+
+        if vcd is not None:
+            self._vcd = WavesWriter(filename=vcd)
+
+    @property
+    def name(self) -> str | None:
+        """Get the circuit name"""
+        return self._name
+
+    @property
+    def time_ns(self) -> int:
+        """Get the current simulation time (ns)"""
+        return self._time_ns
+
+    @property
+    def components(self) -> list[Component]:
+        """Get the components in this circuit"""
+        return list(self._components.values())
+
+    def load_path(self, path) -> str:
+        """Get the load path relative to the circuit path"""
+        if self._folder is not None:
+            return self._folder + "/" + path
+        return path
+
+    def store_path(self, path) -> str:
+        """Get the store path relative to the circuit path"""
+        if self._folder is not None:
+            return str(
+                pathlib.Path(path).resolve().absolute().relative_to(pathlib.Path(self._folder))
+            )
+        return path
+
+    def delete_component(self, component: Component):
+        """Delete a component from the circuit"""
+        del self._components[component.name()]
+        component.remove_connections()
+
+    def get_toplevel_components(self) -> list[Component]:
+        """Get toplevel components in the circuit"""
+        return [comp for comp in self._components.values() if comp.is_toplevel()]
+
+    def init(self):
+        """Initialize circuit and components (and ports)"""
+        self._time_ns = 0
+        self._circuit_events = []
+        self._events_by_port = {}
+        if self._vcd is not None:
+            self._vcd_init()
+        for _, comp in self._components.items():
+            comp.init()
+        for _, comp in self._components.items():
+            comp.default_state()
+        self.run_until(ns=0)  # Handle all time zero events
+
+    def clear(self):
+        """Remove all components"""
+        for _, comp in self._components.items():
+            comp.clear()
+        self._components = {}
+
+    def vcd(self, filename):
+        """Start wave collecting in a gtkwave .vcd file"""
+        if self._vcd is not None:
+            raise CircuitError("VCD already started")
+        self._vcd = WavesWriter(filename=filename)
+        self._vcd_init()
+
+    def vcd_close(self):
+        """Close gtkwave .vcd file"""
+        if self._vcd is not None:
+            self._vcd.close()
+            self._vcd = None
+
+    def _vcd_init(self):
+        port_info = []
+        for _, comp in self._components.items():
+            for port in comp.ports:
+                port_info.append((port.path(), port.name(), port.width))
+        self._vcd.init(port_info)
+
+        # Dump initial state in vcd
+        for _, comp in self._components.items():
+            for port in comp.ports:
+                self._vcd.write(port, self._time_ns)
+
+    def _time_to_ns(self, s=None, ms=None, us=None, ns=None) -> int:
+        time_ns = 0
+        time_ns += s * 1e9 if s is not None else 0
+        time_ns += ms * 1e6 if ms is not None else 0
+        time_ns += us * 1e3 if us is not None else 0
+        time_ns += ns if ns is not None else 0
+        return int(time_ns)
+
+    def __exit__(self, exc_type, exc_value, exc_traceback):
+        self._vcd.close()
+
+    def process_single_event(self, stop_time_ns=None) -> Tuple[bool, bool]:
+        """
+        Process one simulation event
+        Return False if ther are now events of if the stop_time has passed
+        """
+        while self._circuit_events:
+            event = heapq.heappop(self._circuit_events)
+
+            # Check if this is the latest event for this port
+            if event != self._events_by_port.get(event.port):
+                # This is a stale event, ignore it
+                continue
+
+            if stop_time_ns is not None and event.time_ns > stop_time_ns:
+                # Put the event back if it's after the stop time
+                heapq.heappush(self._circuit_events, event)
+                return False, False
+
+            del self._events_by_port[event.port]
+            # print(
+            #     f"Execute event {event.port.path()}.{event.port.name()}"
+            #     f" {event.time_ns} {event.value}"
+            # )
+            self._time_ns = event.time_ns
+            event.port.delta_cycle(event.value)
+            toplevel = event.port.parent().is_toplevel()
+            if self._vcd is not None:
+                self._vcd.write(event.port, self._time_ns)
+            return True, toplevel
+
+        return False, False
+
+    def _is_toplevel_event(self) -> bool:
+        if len(self._circuit_events) == 0:
+            return False
+        event = self._circuit_events[0]
+        return event.port.parent().is_toplevel()
+
+    def run(
+        self,
+        s: int | None = None,
+        ms: int | None = None,
+        us: int | None = None,
+        ns: int | None = None,
+        single_step: bool = False,
+    ) -> bool:
+        """Run simulation for a period of time"""
+        stop_time_ns = self._time_ns + self._time_to_ns(s=s, ms=ms, us=us, ns=ns)
+        single_step_stop = False
+        while len(self._circuit_events) > 0 and self._time_ns <= stop_time_ns:
+            more_events, top_level_event = self.process_single_event(stop_time_ns)
+            if not more_events:
+                break
+            if single_step and top_level_event:
+                stop_time_ns = self._time_ns
+                single_step_stop = True
+        self._time_ns = max(self._time_ns, stop_time_ns)
+        return single_step_stop
+
+    def run_until(
+        self,
+        s: int | None = None,
+        ms: int | None = None,
+        us: int | None = None,
+        ns: int | None = None,
+    ):
+        """Run simulation until a specified time"""
+        stop_time_ns = self._time_to_ns(s=s, ms=ms, us=us, ns=ns)
+        if stop_time_ns >= self._time_ns:
+            self.run(ns=stop_time_ns - self._time_ns)
+
+    def add_event(self, port: PortOutDelta, value: VALUE_TYPE, propagation_delay_ns: int):
+        """Add delta cycle event, this will also write values to .vcd file"""
+        event_time_ns = self._time_ns + propagation_delay_ns
+        # print(f"Add event {port.parent().name()}:{port.name()} => {value}")
+        event = CircuitEvent(event_time_ns, port, value)
+        self._events_by_port[port] = event
+        heapq.heappush(self._circuit_events, event)
+
+    def add_component(self, component: Component):
+        """Add component to circuit"""
+        name_id = 1
+        namebase = component.name()
+        while component.name() in self._components:
+            component.set_name(f"{namebase}_{name_id}", update_circuit=False)
+            name_id += 1
+        self._components[component.name()] = component
+
+    def change_component_name(self, component: Component, name: str):
+        """Change component name"""
+        comp = self._components[component.name()]
+        del self._components[component.name()]
+        comp.set_name(name, update_circuit=False)
+        self.add_component(comp)
+
+    def get_component(self, component_name: str) -> Component:
+        """Get component witgh 'component_name'"""
+        comp = self._components.get(component_name)
+        if comp is not None:
+            return comp
+        raise CircuitError(f"Component '{component_name}' not found")
+
+    def to_dataclass(self, folder: str | None = None) -> CircuitDataClass:
+        """Generate dict from circuit, used when storing circuit"""
+        if self._name is None:
+            raise CircuitError("Circuit must have a name")
+        self._folder = folder
+        return CircuitDataClass.from_circuit(self)
+
+    def from_dataclass(
+        self,
+        circuit_dc: CircuitDataClass,
+        folder: str | None = None,
+        component_exceptions: bool = True,
+        connect_exceptions: bool = True,
+    ) -> list[str]:
+        """Clear circuit and add components from dict"""
+        self._folder = folder
+        self.clear()
+
+        exception_str_list = []
+        for component in circuit_dc.components:
+            try:
+                component.create(self)
+            except DigsimException as exc:
+                if component_exceptions:
+                    raise exc
+                exception_str_list.append(f"{str(exc.__class__.__name__)}:{str(exc)}")
+            except FileNotFoundError as exc:
+                if component_exceptions:
+                    raise exc
+                exception_str_list.append(f"{str(exc.__class__.__name__)}:{str(exc)}")
+        for wire in circuit_dc.wires:
+            try:
+                wire.connect(self)
+            except DigsimException as exc:
+                if connect_exceptions:
+                    raise exc
+                exception_str_list.append(f"{exc.__class__.__name__}:{str(exc)}")
+
+        return exception_str_list
+
+    def to_json_file(self, filename: str):
+        """Store circuit in json file"""
+        circuitfile_dc = CircuitFileDataClass(circuit=self.to_dataclass())
+        circuitfile_dc.save(filename)
+
+    def from_json_file(self, filename: str, folder: str | None = None):
+        """Load circuit from json file"""
+        file_dc = CircuitFileDataClass.load(filename)
+        self.from_dataclass(file_dc.circuit, folder)

digsim/circuit/_waves_writer.py

@@ -0,0 +1,61 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+Module that handles the creation of vcd files
+"""
+
+import io
+from typing import Any, Tuple
+
+from vcd import VCDWriter
+
+from .components.atoms import Port
+
+
+class WavesWriter:
+    """Class that handles the creation of vcd files"""
+
+    def __init__(self, filename: str):
+        self._vcd_name: str = filename
+        self._vcd_file: io.TextIOWrapper | None = None
+        self._vcd_writer: VCDWriter | None = None
+        self._vcd_dict: dict[str, Any] = {}
+
+    def init(self, port_info: list[Tuple[str, str, int]]):
+        """Initialize vcd writer"""
+        if self._vcd_file is not None or self._vcd_writer is not None:
+            self.close()
+        self._vcd_file = open(self._vcd_name, mode="w", encoding="utf-8")
+        if self._vcd_file is None:
+            raise RuntimeError("VCD file is None")
+        self._vcd_writer = VCDWriter(self._vcd_file, timescale="1 ns", date="today")
+        for port_path, port_name, port_width in port_info:
+            var = self._vcd_writer.register_var(port_path, port_name, "wire", size=port_width)
+            self._vcd_dict[f"{port_path}.{port_name}"] = var
+        self._vcd_file.flush()
+
+    def write(self, port: Port, time_ns: int):
+        """Write port value to vcd file"""
+        if self._vcd_file is None:
+            raise RuntimeError("VCD file is None")
+        if self._vcd_writer is None:
+            raise RuntimeError("VCD Writer is None")
+        for wired_port in port.get_wired_ports_recursive():
+            var = self._vcd_dict.get(f"{wired_port.path()}.{wired_port.name()}")
+            if var is None:
+                continue
+            self._vcd_writer.change(var, timestamp=time_ns, value=wired_port.value)
+        self._vcd_file.flush()
+
+    def close(self):
+        """Close vcd file"""
+        if self._vcd_writer is not None:
+            self._vcd_writer.close()
+            self._vcd_writer = None
+
+        if self._vcd_file is not None:
+            self._vcd_file.close()
+            self._vcd_file = None
+
+        self._vcd_dict = {}

digsim/circuit/components/__init__.py

@@ -0,0 +1,26 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""All classes within digsim.circuit.components namespace"""
+
+from ._bus_bits import Bus2Wires, Wires2Bus  # noqa: F401
+from ._button import PushButton  # noqa: F401
+from ._buzzer import Buzzer  # noqa: F401
+from ._clock import Clock  # noqa: F401
+from ._dip_switch import DipSwitch  # noqa: F401
+from ._flip_flops import SRFF, ClockedJKFF, ClockedSRFF, ClockedTFF, FlipFlop  # noqa: F401
+from ._gates import AND, DFF, MUX, NAND, NOR, NOT, OR, SR, XOR  # noqa: F401
+from ._hexdigit import HexDigit  # noqa: F401
+from ._ic import IntegratedCircuit  # noqa: F401
+from ._label_wire import LabelWireIn, LabelWireOut  # noqa: F401
+from ._led import Led  # noqa: F401
+from ._logic_analyzer import LogicAnalyzer  # noqa: F401
+from ._mem64kbyte import Mem64kByte  # noqa: F401
+from ._memstdout import MemStdOut  # noqa: F401
+from ._note import Note  # noqa: F401
+from ._on_off_switch import OnOffSwitch  # noqa: F401
+from ._seven_segment import SevenSegment  # noqa: F401
+from ._static_level import GND, VDD  # noqa: F401
+from ._static_value import StaticValue  # noqa: F401
+from ._yosys_component import YosysComponent, YosysComponentException  # noqa: F401
+from .atoms import PortConnectionError  # noqa: F401

digsim/circuit/components/_bus_bits.py

@@ -0,0 +1,68 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with the bus/bit <=> bus/bit components"""
+
+from .atoms import Component, PortMultiBitWire
+
+
+class Bus2Wires(Component):
+    """Bus to Bits splitter"""
+
+    def __init__(self, circuit, name=None, width=1, enable=None):
+        super().__init__(circuit, name)
+        self._bus = PortMultiBitWire(self, "bus", width=width)
+        self.add_port(self._bus)
+        self._enable = enable
+        if self._enable is None:
+            self._enable = list(range(width))
+
+        for bit_id in range(width):
+            if bit_id in self._enable:
+                bit_port = self._bus.get_bit(bit_id)
+                self.add_port(bit_port)
+
+        self.parameter_set("width", width)
+        self.parameter_set("enable", enable)
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "width": {
+                "type": "int",
+                "min": 2,
+                "max": 32,
+                "default": 2,
+                "description": "Bus width",
+            },
+            "enable": {
+                "type": "width_bool",
+                "default": None,
+                "description": "Enable bit",
+            },
+        }
+
+
+class Wires2Bus(Component):
+    """Bits to Bus merger"""
+
+    def __init__(self, circuit, name=None, width=1):
+        super().__init__(circuit, name)
+        self._bus = PortMultiBitWire(self, "bus", width=width, output=True)
+        self.add_port(self._bus)
+        for bit_id in range(width):
+            bit_port = self._bus.get_bit(bit_id)
+            self.add_port(bit_port)
+        self.parameter_set("width", width)
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "width": {
+                "type": "int",
+                "min": 2,
+                "max": 32,
+                "default": 2,
+                "description": "Bus width",
+            },
+        }

digsim/circuit/components/_button.py

@@ -0,0 +1,44 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""A PushButton component"""
+
+from .atoms import CallbackComponent, PortOutImmediate
+
+
+class PushButton(CallbackComponent):
+    """PushButton component class"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name)
+        portout = PortOutImmediate(self, "O")
+        self.add_port(portout)
+        portout.update_parent(True)
+
+    def default_state(self):
+        self.release()
+
+    def push(self):
+        """Push pushbutton"""
+        self.O.value = 1
+
+    def release(self):
+        """Release pushbutton"""
+        self.O.value = 0
+
+    def reconfigure(self):
+        self.release()
+
+    @property
+    def has_action(self):
+        return True
+
+    @property
+    def active(self):
+        return self.O.value == 1
+
+    def onpress(self):
+        self.push()
+
+    def onrelease(self):
+        self.release()

digsim/circuit/components/_buzzer.py

@@ -0,0 +1,45 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with the Buzzer component"""
+
+from .atoms import CallbackComponent, PortIn
+
+
+class Buzzer(CallbackComponent):
+    """Buzzer component class"""
+
+    TONE_TO_FREQUENCY = {
+        "A": 880,
+        "B": 987.77,
+        "C": 1046.5,
+        "D": 1174.66,
+        "E": 1318.51,
+        "F": 1396.91,
+        "G": 1567.98,
+    }
+
+    def __init__(self, circuit, name=None, tone="A"):
+        super().__init__(circuit, name)
+        self.add_port(PortIn(self, "I"))
+        self.parameter_set("tone", tone)
+
+    @property
+    def active(self):
+        return self.I.has_driver() and self.I.value == 1
+
+    def tone_frequency(self):
+        """Get frequency for tone"""
+        return self.TONE_TO_FREQUENCY[self.parameter_get("tone")]
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "tone": {
+                "type": "list",
+                "items": ["A", "B", "C", "D", "E", "F", "G"],
+                "default": "A",
+                "description": "Buzzer tone",
+                "reconfigurable": True,
+            },
+        }

digsim/circuit/components/_clock.py

@@ -0,0 +1,54 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Clock component module"""
+
+from .atoms import CallbackComponent, PortOutDelta, PortOutImmediate
+
+
+class Clock(CallbackComponent):
+    """Clock component class"""
+
+    def __init__(self, circuit, name=None, frequency=1):
+        super().__init__(circuit, name)
+        self._feedback = PortOutDelta(self, "feedback")
+        portout = PortOutImmediate(self, "O")
+        self.add_port(portout)
+        self._feedback.update_parent(True)
+        self.parameter_set("frequency", frequency)
+        self.reconfigure()
+
+    def default_state(self):
+        self.O.value = 0
+        self._feedback.value = 1
+
+    def update(self):
+        if self._feedback.value == 1:
+            self.O.value = 1
+            self._feedback.value = 0
+        else:
+            self.O.value = 0
+            self._feedback.value = 1
+        super().update()
+
+    def reconfigure(self):
+        frequency = self.parameter_get("frequency")
+        half_period_ns = int(1000000000 / (frequency * 2))
+        self._feedback.set_delay_ns(half_period_ns)
+
+    @property
+    def active(self):
+        return self.O.value == 1
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "frequency": {
+                "type": "int",
+                "min": 1,
+                "max": 50,
+                "default": 1,
+                "description": "Clock frequency in Hz",
+                "reconfigurable": True,
+            },
+        }