digsim-logic-simulator 0.22.0__py3-none-any.whl

digsim/circuit/components/_led.py

@@ -0,0 +1,18 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with the LED component"""
+
+from .atoms import CallbackComponent, PortIn
+
+
+class Led(CallbackComponent):
+    """LED component class"""
+
+    def __init__(self, circuit, name=None, callback=None):
+        super().__init__(circuit, name, callback)
+        self.add_port(PortIn(self, "I"))
+
+    @property
+    def active(self):
+        return self.I.has_driver() and self.I.value == 1

digsim/circuit/components/_logic_analyzer.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with Logic Analyzer component"""
+
+from .atoms import CallbackComponent, PortOutDelta, PortWire
+
+
+class LogicAnalyzer(CallbackComponent):
+    """Logic Analyzer component class"""
+
+    PORTLIST = ["A", "B", "C", "D", "E", "F", "G", "H"]
+
+    def __init__(self, circuit, name=None, sample_rate=100):
+        super().__init__(circuit, name)
+        self.data_dict = {}
+        for portname in self.PORTLIST:
+            self.add_port(PortWire(self, portname))
+            self.data_dict[portname] = [0] * 100
+        self._feedback = PortOutDelta(self, "feedback")
+        self._feedback.update_parent(True)
+        self.parameter_set("sample_rate", sample_rate)
+        self.reconfigure()
+
+    def default_state(self):
+        self._feedback.value = 1
+
+    def update(self):
+        if self._feedback.value == 1:
+            self._feedback.value = 0
+        else:
+            self._feedback.value = 1
+
+        for portname in self.PORTLIST:
+            self.data_dict[portname].pop(0)
+            value = 1 if self.port(portname).value == 1 else 0
+            self.data_dict[portname].append(value)
+        super().update()
+
+    def reconfigure(self):
+        sample_rate = self.parameter_get("sample_rate")
+        period_ns = int(1000000000 / sample_rate)
+        self._feedback.set_delay_ns(period_ns)
+
+    def signal_data(self):
+        """Get the logic analyzer signal data"""
+        return self.data_dict
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "sample_rate": {
+                "type": "int",
+                "min": 10,
+                "max": 100,
+                "default": 20,
+                "description": "Sample rate in Hz",
+                "reconfigurable": True,
+            },
+        }

digsim/circuit/components/_mem64kbyte.py

@@ -0,0 +1,42 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+This module implements a 64kByte synchronous memory
+with 8-bit memory bus and 16-bit address bus.
+It cam be prefilled with binary data from 'rom_filename'
+starting at 'rom_address'.
+"""
+
+from digsim.circuit.components.atoms import Component, PortIn, PortOutDelta, PortWire
+
+
+class Mem64kByte(Component):
+    """64kByte synchronous memory class"""
+
+    def __init__(self, circuit, rom_filename=None, rom_address=0):
+        super().__init__(circuit, "Memory")
+        self.add_port(PortIn(self, "clk"))
+        self.add_port(PortWire(self, "Address", width=16))
+        self.add_port(PortWire(self, "DataIn", width=8))
+        self.add_port(PortWire(self, "WE"))
+        self.add_port(PortOutDelta(self, "DataOut", width=8))
+        self._mem_array = [0] * 65536
+        if rom_filename is not None:
+            with open(rom_filename, mode="rb") as rom:
+                romdata = rom.read()
+                for idx, byte in enumerate(romdata):
+                    self._mem_array[rom_address + idx] = byte
+
+    def update(self):
+        rising_edge = self.clk.is_rising_edge()
+        if not rising_edge or self.Address.value == "X":
+            return
+        addr = self.Address.value
+        we = self.WE.value
+        if we == 1:
+            datain = self.DataIn.value
+            self._mem_array[addr] = datain
+        else:
+            dataout = self._mem_array[addr]
+            self.DataOut.value = dataout

digsim/circuit/components/_memstdout.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+This module implements a synchronous memory mapped stdout output
+with 8-bit memory bus and 16-bit address bus.
+The address is listens to can be changed with the 'address' parameter.
+"""
+
+from digsim.circuit.components.atoms import Component, PortIn, PortWire
+
+
+class MemStdOut(Component):
+    """Synchronous memory mapped stdout class"""
+
+    def __init__(self, circuit, address=0x8000):
+        super().__init__(circuit, "MemStdOut")
+        self._address = address
+        self.add_port(PortIn(self, "clk"))
+        self.add_port(PortWire(self, "Address", width=16))
+        self.add_port(PortWire(self, "DataIn", width=8))
+        self.add_port(PortWire(self, "WE"))
+        self._str = ""
+
+    def update(self):
+        rising_edge = self.clk.is_rising_edge()
+        if self.WE.value == 0 or self.Address.value != self._address:
+            return
+        if rising_edge:
+            datain = self.DataIn.value
+            if datain == 0x0A:
+                print(f"StringOutput [line]: '{self._str}'")
+                self._str = ""
+            else:
+                inchar = chr(datain)
+                print(f"StringOutput [char]: '{inchar}'")
+                self._str += inchar

digsim/circuit/components/_note.py

@@ -0,0 +1,25 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Components that only exist in the model"""
+
+from .atoms import Component
+
+
+class Note(Component):
+    """Note component"""
+
+    def __init__(self, circuit, name=None, text=""):
+        super().__init__(circuit, name)
+        self.parameter_set("text", text)
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "text": {
+                "type": "str",
+                "default": "Write something here...",
+                "description": "Note text",
+                "reconfigurable": True,
+            },
+        }

digsim/circuit/components/_on_off_switch.py

@@ -0,0 +1,54 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""An On/Off Switch  component"""
+
+import logging
+
+from .atoms import CallbackComponent, PortOutDelta
+
+
+class OnOffSwitch(CallbackComponent):
+    """On/Off Switch  component class"""
+
+    def __init__(self, circuit, name=None, start_on=False):
+        super().__init__(circuit, name)
+        portout = PortOutDelta(self, "O", delay_ns=0)
+        self.add_port(portout)
+        portout.update_parent(True)
+        self._on = False
+        if start_on:
+            logging.warning("Setting 'start_on' has been removed")
+
+    def _set(self, state):
+        self._on = state
+        self.O.value = 1 if state else 0
+
+    def default_state(self):
+        self._set(False)
+
+        self.turn_off()
+
+    def turn_on(self):
+        """Turn on the switch"""
+        self.O.value = 1
+        self._on = True
+
+    def turn_off(self):
+        """Turn off the switch"""
+        self._set(False)
+
+    def toggle(self):
+        """Toggle the switch"""
+        self._set(not self._on)
+
+    def onpress(self):
+        self.toggle()
+
+    @property
+    def has_action(self):
+        return True
+
+    @property
+    def active(self):
+        return self._on

digsim/circuit/components/_seven_segment.py

@@ -0,0 +1,28 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with 7-segment LED component"""
+
+from .atoms import CallbackComponent, PortIn
+
+
+class SevenSegment(CallbackComponent):
+    """7-segment LED component class"""
+
+    PORTLIST = ["A", "B", "C", "D", "E", "F", "G", "dot"]
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name)
+        for portname in self.PORTLIST:
+            self.add_port(PortIn(self, portname))
+
+    def segments(self):
+        """Get the active segments"""
+        segments = ""
+        for portname in self.PORTLIST:
+            if self.port(portname).value == 1:
+                if portname == "dot":
+                    segments += "."
+                else:
+                    segments += portname
+        return segments

digsim/circuit/components/_static_level.py

@@ -0,0 +1,28 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with the Static Logic components"""
+
+from .atoms import Component, PortOutDelta
+
+
+class VDD(Component):
+    """VDD / Logic1 component class"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name)
+        self.add_port(PortOutDelta(self, "O", delay_ns=0))
+
+    def default_state(self):
+        self.O.value = 1
+
+
+class GND(Component):
+    """GND / Logic0 component class"""
+
+    def __init__(self, circuit, name=None):
+        super().__init__(circuit, name)
+        self.add_port(PortOutDelta(self, "O", delay_ns=0))
+
+    def default_state(self):
+        self.O.value = 0

digsim/circuit/components/_static_value.py

@@ -0,0 +1,44 @@
+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Module with the Static Leve component"""
+
+from .atoms import Component, PortOutImmediate
+
+
+class StaticValue(Component):
+    """Static value component class"""
+
+    def __init__(self, circuit, name=None, width=1, value=0):
+        super().__init__(circuit, name)
+        self.parameter_set("width", width)
+        self.parameter_set("value", value)
+        self.add_port(PortOutImmediate(self, "O", width=width))
+
+    def default_state(self):
+        self.O.value = self.parameter_get("value")
+
+    def reconfigure(self):
+        self.O.value = self.parameter_get("value")
+
+    @property
+    def active(self):
+        return self.parameter_get("width") == 1 and self.parameter_get("value") == 1
+
+    @classmethod
+    def get_parameters(cls):
+        return {
+            "value": {
+                "type": "width_pow2",
+                "default": 0,
+                "description": "Static value",
+                "reconfigurable": True,
+            },
+            "width": {
+                "type": "int",
+                "min": 1,
+                "max": 16,
+                "default": 1,
+                "description": "Static value bitwidth",
+            },
+        }