digsim-logic-simulator 0.22.0__py3-none-any.whl

digsim/storage_model/__init__.py

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+# Copyright (c) Fredrik Andersson, 2024
+# All rights reserved
+
+"""All classes within digsim.storage_model namespace"""
+
+from ._app import AppFileDataClass, GuiPositionDataClass, ModelDataClass
+from ._circuit import CircuitDataClass, CircuitFileDataClass, ComponentDataClass, WireDataClass

digsim/storage_model/_app.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+Module that handles the dataclasses for application
+"""
+
+from __future__ import annotations
+
+import json
+from dataclasses import asdict
+from typing import Any
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+from ._circuit import CircuitDataClass
+
+
+@dataclass
+class GuiPositionDataClass:
+    x: int = 100
+    y: int = 100
+    z: int = 0
+
+
+@dataclass
+class AppFileDataClass:
+    circuit: CircuitDataClass
+    gui: dict[str, GuiPositionDataClass] = Field(default_factory=dict)
+    shortcuts: dict[str, str] = Field(default_factory=dict)
+    settings: dict[str, Any] = Field(default_factory=dict)
+
+    @staticmethod
+    def load(filename):
+        try:
+            with open(filename, mode="r", encoding="utf-8") as json_file:
+                app_filedata_class = AppFileDataClass(**json.load(json_file))
+        except json.JSONDecodeError as exc:
+            raise ValueError(f"Malformed JSON file: {filename} - {exc}") from exc
+        except FileNotFoundError as exc:
+            raise FileNotFoundError(f"File not found: {filename}") from exc
+        return app_filedata_class
+
+    def save(self, filename):
+        json_object = json.dumps(asdict(self), indent=4)
+        with open(filename, mode="w", encoding="utf-8") as json_file:
+            json_file.write(json_object)
+
+
+@dataclass
+class ModelDataClass:
+    circuit: CircuitDataClass
+    gui: dict[str, GuiPositionDataClass]
+
+    @staticmethod
+    def from_app_file_dc(app_file_dc):
+        return ModelDataClass(circuit=app_file_dc.circuit, gui=app_file_dc.gui)

digsim/storage_model/_circuit.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+Module that handles the dataclasses for circuit load/save
+"""
+
+from __future__ import annotations
+
+import importlib
+import json
+from dataclasses import asdict
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+
+@dataclass
+class WireDataClass:
+    src: str
+    dst: str
+
+    def connect(self, circuit):
+        src_comp_name, src_port_name = self.src.split(".")
+        dst_comp_name, dst_port_name = self.dst.split(".")
+        src_comp = circuit.get_component(src_comp_name)
+        dst_comp = circuit.get_component(dst_comp_name)
+        src_comp.port(src_port_name).wire = dst_comp.port(dst_port_name)
+
+    @classmethod
+    def list_from_port(cls, src_port):
+        wires = []
+        for port in src_port.wired_ports:
+            # Only add port on top-level components
+            if port.parent().is_toplevel():
+                wires.append(
+                    WireDataClass(
+                        src=f"{src_port.parent().name()}.{src_port.name()}",
+                        dst=f"{port.parent().name()}.{port.name()}",
+                    )
+                )
+        return wires
+
+
+@dataclass
+class ComponentDataClass:
+    """Component data class"""
+
+    name: str
+    type: str
+    display_name: str = Field(default="")
+    settings: dict = Field(default_factory=dict)
+
+    def create(self, circuit):
+        """Factory: Create a component from a dict"""
+        if "path" in self.settings:
+            self.settings["path"] = circuit.load_path(self.settings["path"])
+
+        py_module_name = ".".join(self.type.split(".")[0:-1])
+        py_class_name = self.type.split(".")[-1]
+
+        module = importlib.import_module(py_module_name)
+        class_ = getattr(module, py_class_name)
+        component = class_(circuit=circuit, **self.settings)
+        component.set_name(self.name)
+        if self.display_name is not None:
+            component.set_display_name(self.display_name)
+        return component
+
+    @staticmethod
+    def from_component(component):
+        """Return the component information as a dict, used when storing a circuit"""
+        module_split = type(component).__module__.split(".")
+        type_str = ""
+        for module in module_split:
+            if not module.startswith("_"):
+                type_str += f"{module}."
+        type_str += type(component).__name__
+
+        return ComponentDataClass(
+            name=component.name(),
+            display_name=component.display_name(),
+            type=type_str,
+            settings=component.settings_to_dict(),
+        )
+
+
+@dataclass
+class CircuitDataClass:
+    name: str = "unnamed"
+    components: list[ComponentDataClass] = Field(default_factory=list)
+    wires: list[WireDataClass] = Field(default_factory=list)
+
+    @staticmethod
+    def from_circuit(circuit):
+        dc = CircuitDataClass(name=circuit.name)
+        toplevel_components = circuit.get_toplevel_components()
+        for comp in toplevel_components:
+            dc.components.append(ComponentDataClass.from_component(comp))
+
+        for comp in toplevel_components:
+            for port in comp.ports:
+                dc.wires.extend(WireDataClass.list_from_port(port))
+
+        return dc
+
+
+@dataclass
+class CircuitFileDataClass:
+    circuit: CircuitDataClass
+
+    @staticmethod
+    def load(filename):
+        try:
+            with open(filename, mode="r", encoding="utf-8") as json_file:
+                dc = CircuitFileDataClass(**json.load(json_file))
+        except json.JSONDecodeError as exc:
+            raise ValueError(f"Malformed JSON file: {filename} - {exc}") from exc
+        except FileNotFoundError as exc:
+            raise FileNotFoundError(f"File not found: {filename}") from exc
+        return dc
+
+    def save(self, filename):
+        json_object = json.dumps(asdict(self), indent=4)
+        with open(filename, mode="w", encoding="utf-8") as json_file:
+            json_file.write(json_object)

digsim/synth/__init__.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""All classes within digsim.synth namespace"""
+
+from ._synthesis import Synthesis, SynthesisException  # noqa: F401

digsim/synth/__main__.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""The main class module of the digsim.synth namespace"""
+
+import argparse
+import sys
+import time
+
+from . import Synthesis, SynthesisException
+
+
+def _synth_modules(args):
+    print("Synthesis started...")
+    for infile in args.input_files:
+        print(f" - Reading {infile}")
+    print(f"Generating {args.output_file}...")
+    start_time = time.monotonic()
+    synthesis = Synthesis(args.input_files, args.top)
+    try:
+        synthesis.synth_to_json_file(args.output_file, silent=args.silent)
+        print(f"Synthesis complete in {time.monotonic() - start_time:.2f}s")
+    except SynthesisException as exc:
+        print(f"ERROR: {str(exc)}")
+        return -1
+    return 0
+
+
+def _list_modules(args):
+    try:
+        modules = Synthesis.list_modules(args.input_files)
+        print("Modules:")
+        print("========")
+        for idx, module in enumerate(modules):
+            print(f"{idx}: {module}")
+        print("========")
+    except SynthesisException as exc:
+        print(f"ERROR: {str(exc)}")
+        return -1
+    return 0
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser("Yosys synthesizer helper")
+    subparser = parser.add_subparsers(required=True)
+    synth_parser = subparser.add_parser("synth")
+    synth_parser.add_argument(
+        "--input-files", "-i", type=str, nargs="+", required=True, help="The verilog input files"
+    )
+    synth_parser.add_argument(
+        "--output-file", "-o", type=str, required=True, help="The json output file"
+    )
+    synth_parser.add_argument(
+        "--top", "-t", type=str, required=True, help="The verilog top module"
+    )
+    synth_parser.add_argument(
+        "--silent", "-s", action="store_true", help="Silent the yosys output"
+    )
+    synth_parser.set_defaults(func=_synth_modules)
+    list_parser = subparser.add_parser("list")
+    list_parser.add_argument(
+        "--input-files", "-i", type=str, nargs="+", required=True, help="The verilog input files"
+    )
+    list_parser.set_defaults(func=_list_modules)
+    arguments = parser.parse_args()
+    returncode = arguments.func(arguments)
+    sys.exit(returncode)

digsim/synth/_synthesis.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""Helper module for yosys synthesis"""
+
+import json
+import pathlib
+import shutil
+import site
+import sys
+
+import pexpect
+import pexpect.popen_spawn
+
+from digsim.circuit.components.atoms import DigsimException
+
+
+class SynthesisException(DigsimException):
+    """Exception class for yosys synthesis"""
+
+
+class Synthesis:
+    """Helper class for yosys synthesis"""
+
+    @classmethod
+    def _pexpect_wait_for_prompt(cls, pexp):
+        index = pexp.expect(["yosys>", pexpect.EOF])
+        before_lines = pexp.before.decode("utf8").replace("\r", "").split("\n")
+        if index == 0:
+            pass
+        elif index == 1:
+            # Unexpected EOF means ERROR
+            errorline = "ERROR"
+            for line in before_lines:
+                if "ERROR" in line:
+                    errorline = line
+                    break
+            raise SynthesisException(errorline)
+
+        # Remove escape sequence in output
+        out_lines = []
+        for line in before_lines:
+            if line.startswith("\x1b"):
+                continue
+            out_lines.append(line)
+        return out_lines
+
+    @staticmethod
+    def _find_win_yowasp_yosys_binary():
+        try:
+            # Use getusersitepackages if this is present, as it ensures that the
+            # value is initialised properly.
+            user_site = site.getusersitepackages()
+        except AttributeError:
+            user_site = site.USER_SITE
+        scripts_path = pathlib.Path(user_site).parent / "Scripts"
+        yowasp_yosys_path = scripts_path / "yowasp-yosys.exe"
+        if yowasp_yosys_path.is_file():
+            return str(yowasp_yosys_path)
+        return None
+
+    @classmethod
+    def _pexpect_spawn_yosys(cls):
+        # Find linux binary
+        yosys_exe = shutil.which("yosys") or shutil.which("yowasp-yosys")
+
+        # No binary found
+        if yosys_exe is None:
+            # Try to find windows binary
+            yosys_exe = cls._find_win_yowasp_yosys_binary()
+
+        if yosys_exe is None:
+            raise SynthesisException("Yosys executable not found")
+
+        if sys.platform == "win32":
+            return pexpect.popen_spawn.PopenSpawn(yosys_exe)
+
+        return pexpect.spawn(yosys_exe)
+
+    @classmethod
+    def list_modules(cls, verilog_files):
+        """List available modules in verilog files"""
+        if isinstance(verilog_files, str):
+            verilog_files = [verilog_files]
+
+        pexp = cls._pexpect_spawn_yosys()
+        cls._pexpect_wait_for_prompt(pexp)
+        pexp.sendline(f"read -sv {' '.join(verilog_files)}")
+        cls._pexpect_wait_for_prompt(pexp)
+        pexp.sendline("ls")
+        pexp.expect("\n")
+        ls_response = cls._pexpect_wait_for_prompt(pexp)
+        pexp.sendline("exit")
+
+        modules = []
+        for line in ls_response:
+            if len(line) == 0:
+                continue
+            if "modules:" in line:
+                continue
+            modules.append(line.replace("$abstract\\", "").strip())
+        return modules
+
+    def __init__(self, verilog_files, verilog_top_module):
+        if isinstance(verilog_files, str):
+            self._verilog_files = [verilog_files]
+        else:
+            self._verilog_files = verilog_files
+        self._verilog_top_module = verilog_top_module
+        self._yosys_log = []
+
+    def synth_to_json(self, silent=False):
+        """Execute yosys with generated synthesis script"""
+        script = f"read -sv {' '.join(self._verilog_files)}; "
+        script += f"hierarchy -top {self._verilog_top_module}; "
+        script += "proc; flatten; "
+        script += "memory_dff; "
+        script += "proc; opt; techmap; opt; "
+        script += f"synth -noabc -top {self._verilog_top_module}; "
+
+        pexp = self._pexpect_spawn_yosys()
+        self._pexpect_wait_for_prompt(pexp)
+        pexp.sendline(script)
+        yosys_log = self._pexpect_wait_for_prompt(pexp)
+        for line in yosys_log:
+            self._yosys_log.append(line)
+            if silent:
+                continue
+            print("Yosys:", line)
+        pexp.sendline("write_json")
+        pexp.expect("Executing JSON backend.")
+        json_lines = self._pexpect_wait_for_prompt(pexp)
+        pexp.sendline("exit")
+
+        return "\n".join(json_lines)
+
+    def synth_to_dict(self, silent=False):
+        """Execute yosys with generated synthesis script and return python dict"""
+        yosys_json = self.synth_to_json(silent)
+        try:
+            netlist_dict = json.loads(yosys_json)
+        except json.JSONDecodeError as exc:
+            raise SynthesisException(f"Malformed JSON output from Yosys: {exc}") from exc
+        return netlist_dict
+
+    def synth_to_json_file(self, filename, silent=False):
+        """Execute yosys with generated synthesis script and write to file"""
+        yosys_json = self.synth_to_json(silent)
+        if yosys_json is None:
+            raise SynthesisException("Yosys synthesis failed")
+        with open(filename, mode="w", encoding="utf-8") as json_file:
+            json_file.write(yosys_json)
+
+    def get_log(self):
+        """Get the yosys output"""
+        return self._yosys_log

digsim/utils/__init__.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""All classes within digsim.utils namespace"""
+
+from ._yosys_netlist import YosysCell, YosysModule, YosysNetlist  # noqa: F401

digsim/utils/_yosys_netlist.py

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+# Copyright (c) Fredrik Andersson, 2023-2025
+# All rights reserved
+
+"""
+Module with classes to parse a yosys netlist
+"""
+
+from __future__ import annotations
+
+from typing import Any, Literal, Optional, Union
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+
+BIT_TYPE = list[Union[int, Literal["X"], Literal["x"], Literal["0"], Literal["1"]]]
+
+
+@dataclass
+class NetPort:
+    parent: Union[YosysModule, YosysCell]
+    parent_name: str
+    name: str
+    bit_index: Optional[int] = None
+
+
+@dataclass
+class Nets:
+    source: dict[int, NetPort] = Field(default_factory=dict)
+    sinks: dict[int, list[NetPort]] = Field(default_factory=dict)
+
+
+@dataclass
+class YosysPort:
+    direction: str
+    bits: BIT_TYPE
+
+    @property
+    def is_output(self):
+        return self.direction == "output"
+
+    def is_same(self, compare_port):
+        return (compare_port.direction == self.direction) and (
+            len(compare_port.bits) == len(self.bits)
+        )
+
+
+@dataclass
+class YosysCell:
+    type: str
+    port_directions: dict[str, str] = Field(default_factory=dict)
+    connections: dict[str, BIT_TYPE] = Field(default_factory=dict)
+    hide_name: int = 0
+    parameters: dict[str, Any] = Field(default_factory=dict)
+    attributes: dict[str, Any] = Field(default_factory=dict)
+
+    def get_nets(self, name, nets):
+        for port_name, net_list in self.connections.items():
+            if not net_list:
+                # Handle empty net_list, e.g., by skipping or raising an error
+                continue
+            net = net_list[0]
+            port = NetPort(parent=self, parent_name=name, name=port_name)
+            if self.port_directions[port_name] == "input":
+                if net not in nets.sinks:
+                    nets.sinks[net] = []
+                nets.sinks[net].append(port)
+            else:
+                nets.source[net] = port
+
+    def component_name(self, name):
+        """Return a friendly name for a netlist cell"""
+        return f"{name.split('$')[-1]}_{self.component_type()}"
+
+    def component_type(self):
+        """Return a friendly type for a netlist cell"""
+        return f"_{self.type[2:-1]}_"
+
+
+@dataclass
+class YosysNetName:
+    bits: BIT_TYPE
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    hide_name: int = 0
+
+
+@dataclass
+class YosysModule:
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    parameter_default_values: dict[str, Any] = Field(default_factory=dict)
+    ports: dict[str, YosysPort] = Field(default_factory=dict)
+    cells: dict[str, YosysCell] = Field(default_factory=dict)
+    netnames: dict[str, YosysNetName] = Field(default_factory=dict)
+
+    def is_same_interface(self, netlist):
+        is_same = True
+        if len(netlist.ports) == len(self.ports):
+            for netlist_port_name, netlist_port in netlist.ports.items():
+                module_port = self.ports.get(netlist_port_name)
+                if module_port is None or not module_port.is_same(netlist_port):
+                    # Port does not exist or has a different bitwidth
+                    is_same = False
+                    break
+        else:
+            # The number of ports does not match
+            is_same = False
+        return is_same
+
+    def get_nets(self):
+        nets = Nets()
+
+        for port_name, port_item in self.ports.items():
+            for bit_index, net in enumerate(port_item.bits):
+                port = NetPort(parent=self, parent_name="top", name=port_name, bit_index=bit_index)
+                if port_item.is_output:
+                    if net not in nets.sinks:
+                        nets.sinks[net] = []
+                    nets.sinks[net].append(port)
+                else:
+                    nets.source[net] = port
+
+        for cell_name, cell in self.cells.items():
+            cell.get_nets(cell_name, nets)
+
+        return nets
+
+
+@dataclass
+class YosysNetlist:
+    creator: Optional[str] = None
+    modules: dict[str, YosysModule] = Field(default_factory=dict)
+
+    def get_modules(self):
+        return self.modules