v86 0.3.6 → 0.4.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (369) hide show
  1. package/Readme.md +17 -6
  2. package/bios/seabios/.config +113 -0
  3. package/bios/seabios/.config.old +114 -0
  4. package/bios/seabios/.gitignore +4 -0
  5. package/bios/seabios/COPYING +674 -0
  6. package/bios/seabios/COPYING.LESSER +165 -0
  7. package/bios/seabios/Makefile +286 -0
  8. package/bios/seabios/README +17 -0
  9. package/bios/seabios/docs/Build_overview.md +104 -0
  10. package/bios/seabios/docs/Contributing.md +20 -0
  11. package/bios/seabios/docs/Debugging.md +111 -0
  12. package/bios/seabios/docs/Developer_Documentation.md +25 -0
  13. package/bios/seabios/docs/Developer_links.md +86 -0
  14. package/bios/seabios/docs/Download.md +27 -0
  15. package/bios/seabios/docs/Execution_and_code_flow.md +178 -0
  16. package/bios/seabios/docs/Linking_overview.md +160 -0
  17. package/bios/seabios/docs/Mailinglist.md +8 -0
  18. package/bios/seabios/docs/Memory_Model.md +253 -0
  19. package/bios/seabios/docs/README +5 -0
  20. package/bios/seabios/docs/Releases.md +482 -0
  21. package/bios/seabios/docs/Runtime_config.md +193 -0
  22. package/bios/seabios/docs/SeaBIOS.md +17 -0
  23. package/bios/seabios/docs/SeaVGABIOS.md +39 -0
  24. package/bios/seabios/out/autoconf.h +117 -0
  25. package/bios/seabios/out/include/config/acpi/dsdt.h +0 -0
  26. package/bios/seabios/out/include/config/acpi.h +0 -0
  27. package/bios/seabios/out/include/config/ahci.h +0 -0
  28. package/bios/seabios/out/include/config/apmbios.h +0 -0
  29. package/bios/seabios/out/include/config/ata/dma.h +0 -0
  30. package/bios/seabios/out/include/config/ata/pio32.h +0 -0
  31. package/bios/seabios/out/include/config/ata.h +0 -0
  32. package/bios/seabios/out/include/config/auto.conf +69 -0
  33. package/bios/seabios/out/include/config/auto.conf.cmd +9 -0
  34. package/bios/seabios/out/include/config/boot.h +0 -0
  35. package/bios/seabios/out/include/config/bootorder.h +0 -0
  36. package/bios/seabios/out/include/config/build/vgabios.h +0 -0
  37. package/bios/seabios/out/include/config/call32/smm.h +0 -0
  38. package/bios/seabios/out/include/config/cdrom/boot.h +0 -0
  39. package/bios/seabios/out/include/config/cdrom/emu.h +0 -0
  40. package/bios/seabios/out/include/config/debug/level.h +0 -0
  41. package/bios/seabios/out/include/config/drives.h +0 -0
  42. package/bios/seabios/out/include/config/entry/extrastack.h +0 -0
  43. package/bios/seabios/out/include/config/esp/scsi.h +0 -0
  44. package/bios/seabios/out/include/config/flash/floppy.h +0 -0
  45. package/bios/seabios/out/include/config/floppy.h +0 -0
  46. package/bios/seabios/out/include/config/fw/romfile/load.h +0 -0
  47. package/bios/seabios/out/include/config/hardware/irq.h +0 -0
  48. package/bios/seabios/out/include/config/kbd/call/int15/4f.h +0 -0
  49. package/bios/seabios/out/include/config/keyboard.h +0 -0
  50. package/bios/seabios/out/include/config/lpt.h +0 -0
  51. package/bios/seabios/out/include/config/lsi/scsi.h +0 -0
  52. package/bios/seabios/out/include/config/malloc/uppermemory.h +0 -0
  53. package/bios/seabios/out/include/config/megasas.h +0 -0
  54. package/bios/seabios/out/include/config/mouse.h +0 -0
  55. package/bios/seabios/out/include/config/mpt/scsi.h +0 -0
  56. package/bios/seabios/out/include/config/mptable.h +0 -0
  57. package/bios/seabios/out/include/config/mtrr/init.h +0 -0
  58. package/bios/seabios/out/include/config/optionroms.h +0 -0
  59. package/bios/seabios/out/include/config/override/pci/id.h +0 -0
  60. package/bios/seabios/out/include/config/pcibios.h +0 -0
  61. package/bios/seabios/out/include/config/pirtable.h +0 -0
  62. package/bios/seabios/out/include/config/pmm.h +0 -0
  63. package/bios/seabios/out/include/config/pmtimer.h +0 -0
  64. package/bios/seabios/out/include/config/pnpbios.h +0 -0
  65. package/bios/seabios/out/include/config/ps2port.h +0 -0
  66. package/bios/seabios/out/include/config/pvscsi.h +0 -0
  67. package/bios/seabios/out/include/config/qemu/hardware.h +0 -0
  68. package/bios/seabios/out/include/config/qemu.h +0 -0
  69. package/bios/seabios/out/include/config/rom/size.h +0 -0
  70. package/bios/seabios/out/include/config/rtc/timer.h +0 -0
  71. package/bios/seabios/out/include/config/s3/resume.h +0 -0
  72. package/bios/seabios/out/include/config/sdcard.h +0 -0
  73. package/bios/seabios/out/include/config/serial.h +0 -0
  74. package/bios/seabios/out/include/config/tcgbios.h +0 -0
  75. package/bios/seabios/out/include/config/threads.h +0 -0
  76. package/bios/seabios/out/include/config/tristate.conf +4 -0
  77. package/bios/seabios/out/include/config/tsc/timer.h +0 -0
  78. package/bios/seabios/out/include/config/use/smm.h +0 -0
  79. package/bios/seabios/out/include/config/vga/allocate/extra/stack.h +0 -0
  80. package/bios/seabios/out/include/config/vga/bochs/stdvga.h +0 -0
  81. package/bios/seabios/out/include/config/vga/bochs.h +0 -0
  82. package/bios/seabios/out/include/config/vga/did.h +0 -0
  83. package/bios/seabios/out/include/config/vga/extra/stack/size.h +0 -0
  84. package/bios/seabios/out/include/config/vga/fixup/asm.h +0 -0
  85. package/bios/seabios/out/include/config/vga/pci.h +0 -0
  86. package/bios/seabios/out/include/config/vga/stdvga/ports.h +0 -0
  87. package/bios/seabios/out/include/config/vga/vbe.h +0 -0
  88. package/bios/seabios/out/include/config/vga/vid.h +0 -0
  89. package/bios/seabios/out/include/config/vgahooks.h +0 -0
  90. package/bios/seabios/out/include/config/virtio/blk.h +0 -0
  91. package/bios/seabios/out/include/config/virtio/scsi.h +0 -0
  92. package/bios/seabios/out/include/config/xen.h +0 -0
  93. package/bios/seabios/out/scripts/kconfig/conf +0 -0
  94. package/bios/seabios/out/scripts/kconfig/conf.o +0 -0
  95. package/bios/seabios/out/scripts/kconfig/zconf.hash.c +289 -0
  96. package/bios/seabios/out/scripts/kconfig/zconf.lex.c +2420 -0
  97. package/bios/seabios/out/scripts/kconfig/zconf.tab.c +2538 -0
  98. package/bios/seabios/out/scripts/kconfig/zconf.tab.o +0 -0
  99. package/bios/seabios/scripts/acpi_extract.py +366 -0
  100. package/bios/seabios/scripts/acpi_extract_preprocess.py +41 -0
  101. package/bios/seabios/scripts/buildrom.py +56 -0
  102. package/bios/seabios/scripts/buildversion.py +134 -0
  103. package/bios/seabios/scripts/checkrom.py +95 -0
  104. package/bios/seabios/scripts/checkstack.py +226 -0
  105. package/bios/seabios/scripts/checksum.py +16 -0
  106. package/bios/seabios/scripts/encodeint.py +21 -0
  107. package/bios/seabios/scripts/gen-offsets.sh +17 -0
  108. package/bios/seabios/scripts/kconfig/.gitignore +22 -0
  109. package/bios/seabios/scripts/kconfig/Makefile +331 -0
  110. package/bios/seabios/scripts/kconfig/POTFILES.in +12 -0
  111. package/bios/seabios/scripts/kconfig/check.sh +13 -0
  112. package/bios/seabios/scripts/kconfig/conf.c +718 -0
  113. package/bios/seabios/scripts/kconfig/confdata.c +1250 -0
  114. package/bios/seabios/scripts/kconfig/expr.c +1168 -0
  115. package/bios/seabios/scripts/kconfig/expr.h +241 -0
  116. package/bios/seabios/scripts/kconfig/gconf.c +1542 -0
  117. package/bios/seabios/scripts/kconfig/gconf.glade +661 -0
  118. package/bios/seabios/scripts/kconfig/images.c +326 -0
  119. package/bios/seabios/scripts/kconfig/kxgettext.c +235 -0
  120. package/bios/seabios/scripts/kconfig/lex.zconf.c +2430 -0
  121. package/bios/seabios/scripts/kconfig/list.h +131 -0
  122. package/bios/seabios/scripts/kconfig/lkc.h +200 -0
  123. package/bios/seabios/scripts/kconfig/lkc_proto.h +57 -0
  124. package/bios/seabios/scripts/kconfig/lxdialog/.gitignore +4 -0
  125. package/bios/seabios/scripts/kconfig/lxdialog/BIG.FAT.WARNING +4 -0
  126. package/bios/seabios/scripts/kconfig/lxdialog/check-lxdialog.sh +87 -0
  127. package/bios/seabios/scripts/kconfig/lxdialog/checklist.c +332 -0
  128. package/bios/seabios/scripts/kconfig/lxdialog/dialog.h +257 -0
  129. package/bios/seabios/scripts/kconfig/lxdialog/inputbox.c +301 -0
  130. package/bios/seabios/scripts/kconfig/lxdialog/menubox.c +437 -0
  131. package/bios/seabios/scripts/kconfig/lxdialog/textbox.c +408 -0
  132. package/bios/seabios/scripts/kconfig/lxdialog/util.c +713 -0
  133. package/bios/seabios/scripts/kconfig/lxdialog/yesno.c +114 -0
  134. package/bios/seabios/scripts/kconfig/mconf.c +1036 -0
  135. package/bios/seabios/scripts/kconfig/menu.c +697 -0
  136. package/bios/seabios/scripts/kconfig/merge_config.sh +150 -0
  137. package/bios/seabios/scripts/kconfig/nconf.c +1556 -0
  138. package/bios/seabios/scripts/kconfig/nconf.gui.c +656 -0
  139. package/bios/seabios/scripts/kconfig/nconf.h +96 -0
  140. package/bios/seabios/scripts/kconfig/qconf.cc +1795 -0
  141. package/bios/seabios/scripts/kconfig/qconf.h +338 -0
  142. package/bios/seabios/scripts/kconfig/streamline_config.pl +647 -0
  143. package/bios/seabios/scripts/kconfig/symbol.c +1373 -0
  144. package/bios/seabios/scripts/kconfig/util.c +157 -0
  145. package/bios/seabios/scripts/kconfig/zconf.gperf +48 -0
  146. package/bios/seabios/scripts/kconfig/zconf.hash.c_shipped +289 -0
  147. package/bios/seabios/scripts/kconfig/zconf.l +363 -0
  148. package/bios/seabios/scripts/kconfig/zconf.lex.c_shipped +2420 -0
  149. package/bios/seabios/scripts/kconfig/zconf.tab.c_shipped +2538 -0
  150. package/bios/seabios/scripts/kconfig/zconf.y +733 -0
  151. package/bios/seabios/scripts/layoutrom.py +705 -0
  152. package/bios/seabios/scripts/python23compat.py +14 -0
  153. package/bios/seabios/scripts/readserial.py +190 -0
  154. package/bios/seabios/scripts/tarball.sh +36 -0
  155. package/bios/seabios/scripts/test-build.sh +90 -0
  156. package/bios/seabios/scripts/transdump.py +53 -0
  157. package/bios/seabios/scripts/vgafixup.py +96 -0
  158. package/bios/seabios/src/Kconfig +579 -0
  159. package/bios/seabios/src/apm.c +215 -0
  160. package/bios/seabios/src/asm-offsets.c +23 -0
  161. package/bios/seabios/src/biosvar.h +130 -0
  162. package/bios/seabios/src/block.c +623 -0
  163. package/bios/seabios/src/block.h +121 -0
  164. package/bios/seabios/src/bmp.c +117 -0
  165. package/bios/seabios/src/boot.c +793 -0
  166. package/bios/seabios/src/bootsplash.c +255 -0
  167. package/bios/seabios/src/bregs.h +80 -0
  168. package/bios/seabios/src/byteorder.h +71 -0
  169. package/bios/seabios/src/cdrom.c +322 -0
  170. package/bios/seabios/src/clock.c +506 -0
  171. package/bios/seabios/src/code16gcc.s +1 -0
  172. package/bios/seabios/src/config.h +108 -0
  173. package/bios/seabios/src/cp437.c +275 -0
  174. package/bios/seabios/src/cp437.h +1 -0
  175. package/bios/seabios/src/disk.c +779 -0
  176. package/bios/seabios/src/e820map.c +152 -0
  177. package/bios/seabios/src/e820map.h +26 -0
  178. package/bios/seabios/src/entryfuncs.S +165 -0
  179. package/bios/seabios/src/farptr.h +208 -0
  180. package/bios/seabios/src/font.c +139 -0
  181. package/bios/seabios/src/fw/acpi-dsdt-cpu-hotplug.dsl +78 -0
  182. package/bios/seabios/src/fw/acpi-dsdt-dbug.dsl +26 -0
  183. package/bios/seabios/src/fw/acpi-dsdt-hpet.dsl +36 -0
  184. package/bios/seabios/src/fw/acpi-dsdt-isa.dsl +102 -0
  185. package/bios/seabios/src/fw/acpi-dsdt-pci-crs.dsl +90 -0
  186. package/bios/seabios/src/fw/acpi-dsdt.dsl +342 -0
  187. package/bios/seabios/src/fw/acpi-dsdt.hex +554 -0
  188. package/bios/seabios/src/fw/acpi.c +685 -0
  189. package/bios/seabios/src/fw/biostables.c +491 -0
  190. package/bios/seabios/src/fw/coreboot.c +569 -0
  191. package/bios/seabios/src/fw/csm.c +347 -0
  192. package/bios/seabios/src/fw/dev-pci.h +52 -0
  193. package/bios/seabios/src/fw/dev-piix.h +29 -0
  194. package/bios/seabios/src/fw/dev-q35.h +52 -0
  195. package/bios/seabios/src/fw/lzmadecode.c +398 -0
  196. package/bios/seabios/src/fw/lzmadecode.h +67 -0
  197. package/bios/seabios/src/fw/mptable.c +197 -0
  198. package/bios/seabios/src/fw/mtrr.c +105 -0
  199. package/bios/seabios/src/fw/multiboot.c +111 -0
  200. package/bios/seabios/src/fw/paravirt.c +624 -0
  201. package/bios/seabios/src/fw/paravirt.h +63 -0
  202. package/bios/seabios/src/fw/pciinit.c +1187 -0
  203. package/bios/seabios/src/fw/pirtable.c +103 -0
  204. package/bios/seabios/src/fw/q35-acpi-dsdt.dsl +450 -0
  205. package/bios/seabios/src/fw/romfile_loader.c +259 -0
  206. package/bios/seabios/src/fw/romfile_loader.h +91 -0
  207. package/bios/seabios/src/fw/shadow.c +208 -0
  208. package/bios/seabios/src/fw/smbios.c +585 -0
  209. package/bios/seabios/src/fw/smm.c +269 -0
  210. package/bios/seabios/src/fw/smp.c +194 -0
  211. package/bios/seabios/src/fw/ssdt-misc.dsl +104 -0
  212. package/bios/seabios/src/fw/ssdt-misc.hex +88 -0
  213. package/bios/seabios/src/fw/ssdt-pcihp.dsl +36 -0
  214. package/bios/seabios/src/fw/ssdt-pcihp.hex +38 -0
  215. package/bios/seabios/src/fw/ssdt-proc.dsl +48 -0
  216. package/bios/seabios/src/fw/ssdt-proc.hex +35 -0
  217. package/bios/seabios/src/fw/xen.c +149 -0
  218. package/bios/seabios/src/fw/xen.h +125 -0
  219. package/bios/seabios/src/gen-defs.h +19 -0
  220. package/bios/seabios/src/hw/ahci.c +697 -0
  221. package/bios/seabios/src/hw/ahci.h +201 -0
  222. package/bios/seabios/src/hw/ata.c +1046 -0
  223. package/bios/seabios/src/hw/ata.h +163 -0
  224. package/bios/seabios/src/hw/blockcmd.c +372 -0
  225. package/bios/seabios/src/hw/blockcmd.h +114 -0
  226. package/bios/seabios/src/hw/dma.c +67 -0
  227. package/bios/seabios/src/hw/esp-scsi.c +241 -0
  228. package/bios/seabios/src/hw/esp-scsi.h +8 -0
  229. package/bios/seabios/src/hw/floppy.c +741 -0
  230. package/bios/seabios/src/hw/lsi-scsi.c +221 -0
  231. package/bios/seabios/src/hw/lsi-scsi.h +8 -0
  232. package/bios/seabios/src/hw/megasas.c +405 -0
  233. package/bios/seabios/src/hw/megasas.h +8 -0
  234. package/bios/seabios/src/hw/mpt-scsi.c +319 -0
  235. package/bios/seabios/src/hw/mpt-scsi.h +8 -0
  236. package/bios/seabios/src/hw/nvme-int.h +199 -0
  237. package/bios/seabios/src/hw/nvme.c +708 -0
  238. package/bios/seabios/src/hw/nvme.h +17 -0
  239. package/bios/seabios/src/hw/pci.c +133 -0
  240. package/bios/seabios/src/hw/pci.h +47 -0
  241. package/bios/seabios/src/hw/pci_ids.h +2632 -0
  242. package/bios/seabios/src/hw/pci_regs.h +556 -0
  243. package/bios/seabios/src/hw/pcidevice.c +192 -0
  244. package/bios/seabios/src/hw/pcidevice.h +76 -0
  245. package/bios/seabios/src/hw/pic.c +115 -0
  246. package/bios/seabios/src/hw/pic.h +60 -0
  247. package/bios/seabios/src/hw/ps2port.c +543 -0
  248. package/bios/seabios/src/hw/ps2port.h +67 -0
  249. package/bios/seabios/src/hw/pvscsi.c +333 -0
  250. package/bios/seabios/src/hw/pvscsi.h +8 -0
  251. package/bios/seabios/src/hw/ramdisk.c +108 -0
  252. package/bios/seabios/src/hw/rtc.c +100 -0
  253. package/bios/seabios/src/hw/rtc.h +75 -0
  254. package/bios/seabios/src/hw/sdcard.c +572 -0
  255. package/bios/seabios/src/hw/serialio.c +113 -0
  256. package/bios/seabios/src/hw/serialio.h +29 -0
  257. package/bios/seabios/src/hw/timer.c +259 -0
  258. package/bios/seabios/src/hw/tpm_drivers.c +636 -0
  259. package/bios/seabios/src/hw/tpm_drivers.h +127 -0
  260. package/bios/seabios/src/hw/usb-ehci.c +650 -0
  261. package/bios/seabios/src/hw/usb-ehci.h +177 -0
  262. package/bios/seabios/src/hw/usb-hid.c +442 -0
  263. package/bios/seabios/src/hw/usb-hid.h +29 -0
  264. package/bios/seabios/src/hw/usb-hub.c +205 -0
  265. package/bios/seabios/src/hw/usb-hub.h +64 -0
  266. package/bios/seabios/src/hw/usb-msc.c +222 -0
  267. package/bios/seabios/src/hw/usb-msc.h +10 -0
  268. package/bios/seabios/src/hw/usb-ohci.c +568 -0
  269. package/bios/seabios/src/hw/usb-ohci.h +144 -0
  270. package/bios/seabios/src/hw/usb-uas.c +289 -0
  271. package/bios/seabios/src/hw/usb-uas.h +9 -0
  272. package/bios/seabios/src/hw/usb-uhci.c +571 -0
  273. package/bios/seabios/src/hw/usb-uhci.h +128 -0
  274. package/bios/seabios/src/hw/usb-xhci.c +1161 -0
  275. package/bios/seabios/src/hw/usb-xhci.h +133 -0
  276. package/bios/seabios/src/hw/usb.c +499 -0
  277. package/bios/seabios/src/hw/usb.h +254 -0
  278. package/bios/seabios/src/hw/virtio-blk.c +211 -0
  279. package/bios/seabios/src/hw/virtio-blk.h +43 -0
  280. package/bios/seabios/src/hw/virtio-pci.c +501 -0
  281. package/bios/seabios/src/hw/virtio-pci.h +151 -0
  282. package/bios/seabios/src/hw/virtio-ring.c +147 -0
  283. package/bios/seabios/src/hw/virtio-ring.h +121 -0
  284. package/bios/seabios/src/hw/virtio-scsi.c +220 -0
  285. package/bios/seabios/src/hw/virtio-scsi.h +47 -0
  286. package/bios/seabios/src/jpeg.c +1055 -0
  287. package/bios/seabios/src/kbd.c +599 -0
  288. package/bios/seabios/src/list.h +91 -0
  289. package/bios/seabios/src/malloc.c +561 -0
  290. package/bios/seabios/src/malloc.h +70 -0
  291. package/bios/seabios/src/memmap.h +21 -0
  292. package/bios/seabios/src/misc.c +195 -0
  293. package/bios/seabios/src/mouse.c +342 -0
  294. package/bios/seabios/src/optionroms.c +475 -0
  295. package/bios/seabios/src/output.c +584 -0
  296. package/bios/seabios/src/output.h +68 -0
  297. package/bios/seabios/src/pcibios.c +241 -0
  298. package/bios/seabios/src/pmm.c +176 -0
  299. package/bios/seabios/src/pnpbios.c +88 -0
  300. package/bios/seabios/src/post.c +337 -0
  301. package/bios/seabios/src/resume.c +157 -0
  302. package/bios/seabios/src/romfile.c +146 -0
  303. package/bios/seabios/src/romfile.h +21 -0
  304. package/bios/seabios/src/romlayout.S +698 -0
  305. package/bios/seabios/src/sercon.c +677 -0
  306. package/bios/seabios/src/serial.c +317 -0
  307. package/bios/seabios/src/sha1.c +147 -0
  308. package/bios/seabios/src/sha1.h +8 -0
  309. package/bios/seabios/src/stacks.c +771 -0
  310. package/bios/seabios/src/stacks.h +68 -0
  311. package/bios/seabios/src/std/LegacyBios.h +985 -0
  312. package/bios/seabios/src/std/acpi.h +323 -0
  313. package/bios/seabios/src/std/bda.h +174 -0
  314. package/bios/seabios/src/std/disk.h +175 -0
  315. package/bios/seabios/src/std/mptable.h +77 -0
  316. package/bios/seabios/src/std/multiboot.h +260 -0
  317. package/bios/seabios/src/std/optionrom.h +59 -0
  318. package/bios/seabios/src/std/pirtable.h +35 -0
  319. package/bios/seabios/src/std/pmm.h +19 -0
  320. package/bios/seabios/src/std/pnpbios.h +24 -0
  321. package/bios/seabios/src/std/smbios.h +167 -0
  322. package/bios/seabios/src/std/tcg.h +554 -0
  323. package/bios/seabios/src/std/vbe.h +156 -0
  324. package/bios/seabios/src/std/vga.h +63 -0
  325. package/bios/seabios/src/string.c +251 -0
  326. package/bios/seabios/src/string.h +31 -0
  327. package/bios/seabios/src/system.c +357 -0
  328. package/bios/seabios/src/tcgbios.c +2014 -0
  329. package/bios/seabios/src/tcgbios.h +19 -0
  330. package/bios/seabios/src/types.h +156 -0
  331. package/bios/seabios/src/util.h +251 -0
  332. package/bios/seabios/src/version.c +5 -0
  333. package/bios/seabios/src/vgahooks.c +355 -0
  334. package/bios/seabios/src/x86.c +23 -0
  335. package/bios/seabios/src/x86.h +277 -0
  336. package/bios/seabios/vgasrc/Kconfig +211 -0
  337. package/bios/seabios/vgasrc/bochsdisplay.c +59 -0
  338. package/bios/seabios/vgasrc/bochsvga.c +447 -0
  339. package/bios/seabios/vgasrc/bochsvga.h +57 -0
  340. package/bios/seabios/vgasrc/cbvga.c +337 -0
  341. package/bios/seabios/vgasrc/clext.c +627 -0
  342. package/bios/seabios/vgasrc/geodevga.c +434 -0
  343. package/bios/seabios/vgasrc/geodevga.h +89 -0
  344. package/bios/seabios/vgasrc/ramfb.c +163 -0
  345. package/bios/seabios/vgasrc/stdvga.c +485 -0
  346. package/bios/seabios/vgasrc/stdvga.h +81 -0
  347. package/bios/seabios/vgasrc/stdvgaio.c +186 -0
  348. package/bios/seabios/vgasrc/stdvgamodes.c +534 -0
  349. package/bios/seabios/vgasrc/swcursor.c +96 -0
  350. package/bios/seabios/vgasrc/vbe.c +432 -0
  351. package/bios/seabios/vgasrc/vgabios.c +1131 -0
  352. package/bios/seabios/vgasrc/vgabios.h +88 -0
  353. package/bios/seabios/vgasrc/vgaentry.S +161 -0
  354. package/bios/seabios/vgasrc/vgafb.c +661 -0
  355. package/bios/seabios/vgasrc/vgafb.h +42 -0
  356. package/bios/seabios/vgasrc/vgafonts.c +785 -0
  357. package/bios/seabios/vgasrc/vgahw.h +152 -0
  358. package/bios/seabios/vgasrc/vgainit.c +202 -0
  359. package/bios/seabios/vgasrc/vgalayout.lds.S +23 -0
  360. package/bios/seabios/vgasrc/vgautil.h +103 -0
  361. package/bios/seabios/vgasrc/vgaversion.c +6 -0
  362. package/build/binaries.js +1 -1
  363. package/build/index-debug.cjs +1 -1
  364. package/build/index-debug.js +1 -1
  365. package/build/index.cjs +1 -1
  366. package/build/index.js +1 -1
  367. package/build/v86-debug.wasm +0 -0
  368. package/build/v86.wasm +0 -0
  369. package/package.json +1 -1
@@ -0,0 +1,543 @@
1
+ // Support for handling the PS/2 mouse/keyboard ports.
2
+ //
3
+ // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4
+ // Several ideas taken from code Copyright (c) 1999-2004 Vojtech Pavlik
5
+ //
6
+ // This file may be distributed under the terms of the GNU LGPLv3 license.
7
+
8
+ #include "biosvar.h" // GET_LOW
9
+ #include "output.h" // dprintf
10
+ #include "pic.h" // pic_eoi1
11
+ #include "ps2port.h" // ps2_kbd_command
12
+ #include "romfile.h" // romfile_loadint
13
+ #include "stacks.h" // yield
14
+ #include "util.h" // udelay
15
+ #include "x86.h" // inb
16
+
17
+
18
+ /****************************************************************
19
+ * Low level i8042 commands.
20
+ ****************************************************************/
21
+
22
+ // Timeout value.
23
+ #define I8042_CTL_TIMEOUT 10000
24
+
25
+ #define I8042_BUFFER_SIZE 16
26
+
27
+ static int
28
+ i8042_wait_read(void)
29
+ {
30
+ dprintf(7, "i8042_wait_read\n");
31
+ int i;
32
+ for (i=0; i<I8042_CTL_TIMEOUT; i++) {
33
+ u8 status = inb(PORT_PS2_STATUS);
34
+ if (status & I8042_STR_OBF)
35
+ return 0;
36
+ udelay(50);
37
+ }
38
+ warn_timeout();
39
+ return -1;
40
+ }
41
+
42
+ static int
43
+ i8042_wait_write(void)
44
+ {
45
+ dprintf(7, "i8042_wait_write\n");
46
+ int i;
47
+ for (i=0; i<I8042_CTL_TIMEOUT; i++) {
48
+ u8 status = inb(PORT_PS2_STATUS);
49
+ if (! (status & I8042_STR_IBF))
50
+ return 0;
51
+ udelay(50);
52
+ }
53
+ warn_timeout();
54
+ return -1;
55
+ }
56
+
57
+ static int
58
+ i8042_flush(void)
59
+ {
60
+ dprintf(7, "i8042_flush\n");
61
+ int i;
62
+ for (i=0; i<I8042_BUFFER_SIZE; i++) {
63
+ u8 status = inb(PORT_PS2_STATUS);
64
+ if (! (status & I8042_STR_OBF))
65
+ return 0;
66
+ udelay(50);
67
+ u8 data = inb(PORT_PS2_DATA);
68
+ dprintf(7, "i8042 flushed %x (status=%x)\n", data, status);
69
+ }
70
+
71
+ warn_timeout();
72
+ return -1;
73
+ }
74
+
75
+ static int
76
+ __i8042_command(int command, u8 *param)
77
+ {
78
+ int receive = (command >> 8) & 0xf;
79
+ int send = (command >> 12) & 0xf;
80
+
81
+ // Send the command.
82
+ int ret = i8042_wait_write();
83
+ if (ret)
84
+ return ret;
85
+ outb(command, PORT_PS2_STATUS);
86
+
87
+ // Send parameters (if any).
88
+ int i;
89
+ for (i = 0; i < send; i++) {
90
+ ret = i8042_wait_write();
91
+ if (ret)
92
+ return ret;
93
+ outb(param[i], PORT_PS2_DATA);
94
+ }
95
+
96
+ // Receive parameters (if any).
97
+ for (i = 0; i < receive; i++) {
98
+ ret = i8042_wait_read();
99
+ if (ret)
100
+ return ret;
101
+ param[i] = inb(PORT_PS2_DATA);
102
+ dprintf(7, "i8042 param=%x\n", param[i]);
103
+ }
104
+
105
+ return 0;
106
+ }
107
+
108
+ static int
109
+ i8042_command(int command, u8 *param)
110
+ {
111
+ dprintf(7, "i8042_command cmd=%x\n", command);
112
+ int ret = __i8042_command(command, param);
113
+ if (ret)
114
+ dprintf(2, "i8042 command %x failed\n", command);
115
+ return ret;
116
+ }
117
+
118
+ static int
119
+ i8042_kbd_write(u8 c)
120
+ {
121
+ dprintf(7, "i8042_kbd_write c=%d\n", c);
122
+ int ret = i8042_wait_write();
123
+ if (! ret)
124
+ outb(c, PORT_PS2_DATA);
125
+ return ret;
126
+ }
127
+
128
+ static int
129
+ i8042_aux_write(u8 c)
130
+ {
131
+ return i8042_command(I8042_CMD_AUX_SEND, &c);
132
+ }
133
+
134
+ void
135
+ i8042_reboot(void)
136
+ {
137
+ if (! CONFIG_PS2PORT)
138
+ return;
139
+ int i;
140
+ for (i=0; i<10; i++) {
141
+ i8042_wait_write();
142
+ udelay(50);
143
+ outb(0xfe, PORT_PS2_STATUS); /* pulse reset low */
144
+ udelay(50);
145
+ }
146
+ }
147
+
148
+
149
+ /****************************************************************
150
+ * Device commands.
151
+ ****************************************************************/
152
+
153
+ #define PS2_RET_ACK 0xfa
154
+ #define PS2_RET_NAK 0xfe
155
+
156
+ static int
157
+ ps2_recvbyte(int aux, int needack, int timeout)
158
+ {
159
+ u32 end = timer_calc(timeout);
160
+ for (;;) {
161
+ u8 status = inb(PORT_PS2_STATUS);
162
+ if (status & I8042_STR_OBF) {
163
+ u8 data = inb(PORT_PS2_DATA);
164
+ dprintf(7, "ps2 read %x\n", data);
165
+
166
+ if (!!(status & I8042_STR_AUXDATA) == aux) {
167
+ if (!needack)
168
+ return data;
169
+ if (data == PS2_RET_ACK)
170
+ return data;
171
+ if (data == PS2_RET_NAK) {
172
+ dprintf(1, "Got ps2 nak (status=%x)\n", status);
173
+ return data;
174
+ }
175
+ }
176
+
177
+ // This data not part of command - just discard it.
178
+ dprintf(1, "Discarding ps2 data %02x (status=%02x)\n", data, status);
179
+ }
180
+
181
+ if (timer_check(end)) {
182
+ warn_timeout();
183
+ return -1;
184
+ }
185
+ yield();
186
+ }
187
+ }
188
+
189
+ static int
190
+ ps2_sendbyte(int aux, u8 command, int timeout)
191
+ {
192
+ dprintf(7, "ps2_sendbyte aux=%d cmd=%x\n", aux, command);
193
+ int ret;
194
+ if (aux)
195
+ ret = i8042_aux_write(command);
196
+ else
197
+ ret = i8042_kbd_write(command);
198
+ if (ret)
199
+ return ret;
200
+
201
+ // Read ack.
202
+ ret = ps2_recvbyte(aux, 1, timeout);
203
+ if (ret < 0)
204
+ return ret;
205
+ if (ret != PS2_RET_ACK)
206
+ return -1;
207
+
208
+ return 0;
209
+ }
210
+
211
+ u8 Ps2ctr VARLOW = I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
212
+
213
+ static int
214
+ __ps2_command(int aux, int command, u8 *param)
215
+ {
216
+ int ret2;
217
+ int receive = (command >> 8) & 0xf;
218
+ int send = (command >> 12) & 0xf;
219
+
220
+ // Disable interrupts and keyboard/mouse.
221
+ u8 ps2ctr = GET_LOW(Ps2ctr);
222
+ u8 newctr = ((ps2ctr | I8042_CTR_AUXDIS | I8042_CTR_KBDDIS)
223
+ & ~(I8042_CTR_KBDINT|I8042_CTR_AUXINT));
224
+ dprintf(6, "i8042 ctr old=%x new=%x\n", ps2ctr, newctr);
225
+ int ret = i8042_command(I8042_CMD_CTL_WCTR, &newctr);
226
+ if (ret)
227
+ return ret;
228
+
229
+ // Flush any interrupts already pending.
230
+ yield();
231
+
232
+ // Enable port command is being sent to.
233
+ SET_LOW(Ps2ctr, newctr);
234
+ if (aux)
235
+ newctr &= ~I8042_CTR_AUXDIS;
236
+ else
237
+ newctr &= ~I8042_CTR_KBDDIS;
238
+ ret = i8042_command(I8042_CMD_CTL_WCTR, &newctr);
239
+ if (ret)
240
+ goto fail;
241
+
242
+ if ((u8)command == (u8)ATKBD_CMD_RESET_BAT) {
243
+ // Reset is special wrt timeouts.
244
+
245
+ // Send command.
246
+ ret = ps2_sendbyte(aux, command, 1000);
247
+ if (ret)
248
+ goto fail;
249
+
250
+ // Receive parameters.
251
+ ret = ps2_recvbyte(aux, 0, 4000);
252
+ if (ret < 0)
253
+ goto fail;
254
+ param[0] = ret;
255
+ if (receive > 1) {
256
+ ret = ps2_recvbyte(aux, 0, 500);
257
+ if (ret < 0)
258
+ goto fail;
259
+ param[1] = ret;
260
+ }
261
+ } else if (command == ATKBD_CMD_GETID) {
262
+ // Getid is special wrt bytes received.
263
+
264
+ // Send command.
265
+ ret = ps2_sendbyte(aux, command, 200);
266
+ if (ret)
267
+ goto fail;
268
+
269
+ // Receive parameters.
270
+ ret = ps2_recvbyte(aux, 0, 500);
271
+ if (ret < 0)
272
+ goto fail;
273
+ param[0] = ret;
274
+ if (ret == 0xab || ret == 0xac || ret == 0x2b || ret == 0x5d
275
+ || ret == 0x60 || ret == 0x47) {
276
+ // These ids (keyboards) return two bytes.
277
+ ret = ps2_recvbyte(aux, 0, 500);
278
+ if (ret < 0)
279
+ goto fail;
280
+ param[1] = ret;
281
+ } else {
282
+ param[1] = 0;
283
+ }
284
+ } else {
285
+ // Send command.
286
+ ret = ps2_sendbyte(aux, command, 200);
287
+ if (ret)
288
+ goto fail;
289
+
290
+ // Send parameters (if any).
291
+ int i;
292
+ for (i = 0; i < send; i++) {
293
+ ret = ps2_sendbyte(aux, param[i], 200);
294
+ if (ret)
295
+ goto fail;
296
+ }
297
+
298
+ // Receive parameters (if any).
299
+ for (i = 0; i < receive; i++) {
300
+ ret = ps2_recvbyte(aux, 0, 500);
301
+ if (ret < 0)
302
+ goto fail;
303
+ param[i] = ret;
304
+ }
305
+ }
306
+
307
+ ret = 0;
308
+
309
+ fail:
310
+ // Restore interrupts and keyboard/mouse.
311
+ SET_LOW(Ps2ctr, ps2ctr);
312
+ ret2 = i8042_command(I8042_CMD_CTL_WCTR, &ps2ctr);
313
+ if (ret2)
314
+ return ret2;
315
+
316
+ return ret;
317
+ }
318
+
319
+ static int
320
+ ps2_command(int aux, int command, u8 *param)
321
+ {
322
+ dprintf(7, "ps2_command aux=%d cmd=%x\n", aux, command);
323
+ int ret = __ps2_command(aux, command, param);
324
+ if (ret)
325
+ dprintf(2, "ps2 command %x failed (aux=%d)\n", command, aux);
326
+ return ret;
327
+ }
328
+
329
+ int
330
+ ps2_kbd_command(int command, u8 *param)
331
+ {
332
+ if (! CONFIG_PS2PORT)
333
+ return -1;
334
+ return ps2_command(0, command, param);
335
+ }
336
+
337
+ int
338
+ ps2_mouse_command(int command, u8 *param)
339
+ {
340
+ if (! CONFIG_PS2PORT)
341
+ return -1;
342
+
343
+ // Update ps2ctr for mouse enable/disable.
344
+ if (command == PSMOUSE_CMD_ENABLE || command == PSMOUSE_CMD_DISABLE) {
345
+ u8 ps2ctr = GET_LOW(Ps2ctr);
346
+ if (command == PSMOUSE_CMD_ENABLE)
347
+ ps2ctr = ((ps2ctr | (CONFIG_HARDWARE_IRQ ? I8042_CTR_AUXINT : 0))
348
+ & ~I8042_CTR_AUXDIS);
349
+ else
350
+ ps2ctr = (ps2ctr | I8042_CTR_AUXDIS) & ~I8042_CTR_AUXINT;
351
+ SET_LOW(Ps2ctr, ps2ctr);
352
+ }
353
+
354
+ return ps2_command(1, command, param);
355
+ }
356
+
357
+
358
+ /****************************************************************
359
+ * IRQ handlers
360
+ ****************************************************************/
361
+
362
+ // INT74h : PS/2 mouse hardware interrupt
363
+ void VISIBLE16
364
+ handle_74(void)
365
+ {
366
+ if (! CONFIG_PS2PORT)
367
+ return;
368
+
369
+ debug_isr(DEBUG_ISR_74);
370
+
371
+ u8 v = inb(PORT_PS2_STATUS);
372
+ if ((v & (I8042_STR_OBF|I8042_STR_AUXDATA))
373
+ != (I8042_STR_OBF|I8042_STR_AUXDATA)) {
374
+ dprintf(1, "ps2 mouse irq but no mouse data.\n");
375
+ goto done;
376
+ }
377
+ v = inb(PORT_PS2_DATA);
378
+
379
+ if (!(GET_LOW(Ps2ctr) & I8042_CTR_AUXINT))
380
+ // Interrupts not enabled.
381
+ goto done;
382
+
383
+ process_mouse(v);
384
+
385
+ done:
386
+ pic_eoi2();
387
+ }
388
+
389
+ // INT09h : Keyboard Hardware Service Entry Point
390
+ void VISIBLE16
391
+ handle_09(void)
392
+ {
393
+ if (! CONFIG_PS2PORT)
394
+ return;
395
+
396
+ debug_isr(DEBUG_ISR_09);
397
+
398
+ // read key from keyboard controller
399
+ u8 v = inb(PORT_PS2_STATUS);
400
+ if (v & I8042_STR_AUXDATA) {
401
+ dprintf(1, "ps2 keyboard irq but found mouse data?!\n");
402
+ goto done;
403
+ }
404
+ v = inb(PORT_PS2_DATA);
405
+
406
+ if (!(GET_LOW(Ps2ctr) & I8042_CTR_KBDINT))
407
+ // Interrupts not enabled.
408
+ goto done;
409
+
410
+ process_key(v);
411
+
412
+ // Some old programs expect ISR to turn keyboard back on.
413
+ i8042_command(I8042_CMD_KBD_ENABLE, NULL);
414
+
415
+ done:
416
+ pic_eoi1();
417
+ }
418
+
419
+ // Check for ps2 activity on machines without hardware irqs
420
+ void
421
+ ps2_check_event(void)
422
+ {
423
+ if (! CONFIG_PS2PORT || CONFIG_HARDWARE_IRQ)
424
+ return;
425
+ u8 ps2ctr = GET_LOW(Ps2ctr);
426
+ if ((ps2ctr & (I8042_CTR_KBDDIS|I8042_CTR_AUXDIS))
427
+ == (I8042_CTR_KBDDIS|I8042_CTR_AUXDIS))
428
+ return;
429
+ for (;;) {
430
+ u8 status = inb(PORT_PS2_STATUS);
431
+ if (!(status & I8042_STR_OBF))
432
+ break;
433
+ u8 data = inb(PORT_PS2_DATA);
434
+ if (status & I8042_STR_AUXDATA) {
435
+ if (!(ps2ctr & I8042_CTR_AUXDIS))
436
+ process_mouse(data);
437
+ } else {
438
+ if (!(ps2ctr & I8042_CTR_KBDDIS))
439
+ process_key(data);
440
+ }
441
+ }
442
+ }
443
+
444
+
445
+ /****************************************************************
446
+ * Setup
447
+ ****************************************************************/
448
+
449
+ static void
450
+ ps2_keyboard_setup(void *data)
451
+ {
452
+ // flush incoming keys (also verifies port is likely present)
453
+ int ret = i8042_flush();
454
+ if (ret)
455
+ return;
456
+
457
+ // Disable keyboard / mouse and drain any input they may have sent
458
+ ret = i8042_command(I8042_CMD_KBD_DISABLE, NULL);
459
+ if (ret)
460
+ return;
461
+ ret = i8042_command(I8042_CMD_AUX_DISABLE, NULL);
462
+ if (ret)
463
+ return;
464
+ ret = i8042_flush();
465
+ if (ret)
466
+ return;
467
+
468
+ // Controller self-test.
469
+ u8 param[2];
470
+ ret = i8042_command(I8042_CMD_CTL_TEST, param);
471
+ if (ret)
472
+ return;
473
+ if (param[0] != 0x55) {
474
+ dprintf(1, "i8042 self test failed (got %x not 0x55)\n", param[0]);
475
+ return;
476
+ }
477
+
478
+ // Controller keyboard test.
479
+ ret = i8042_command(I8042_CMD_KBD_TEST, param);
480
+ if (ret)
481
+ return;
482
+ if (param[0] != 0x00) {
483
+ dprintf(1, "i8042 keyboard test failed (got %x not 0x00)\n", param[0]);
484
+ return;
485
+ }
486
+
487
+
488
+ /* ------------------- keyboard side ------------------------*/
489
+ /* reset keyboard and self test (keyboard side) */
490
+ int spinupdelay = romfile_loadint("etc/ps2-keyboard-spinup", 0);
491
+ u32 end = timer_calc(spinupdelay);
492
+ for (;;) {
493
+ ret = ps2_kbd_command(ATKBD_CMD_RESET_BAT, param);
494
+ if (!ret)
495
+ break;
496
+ if (timer_check(end)) {
497
+ if (spinupdelay)
498
+ warn_timeout();
499
+ return;
500
+ }
501
+ yield();
502
+ }
503
+ if (param[0] != 0xaa) {
504
+ dprintf(1, "keyboard self test failed (got %x not 0xaa)\n", param[0]);
505
+ return;
506
+ }
507
+
508
+ /* Disable keyboard */
509
+ ret = ps2_kbd_command(ATKBD_CMD_RESET_DIS, NULL);
510
+ if (ret)
511
+ return;
512
+
513
+ // Set scancode command (mode 2)
514
+ param[0] = 0x02;
515
+ ret = ps2_kbd_command(ATKBD_CMD_SSCANSET, param);
516
+ if (ret)
517
+ return;
518
+
519
+ // Keyboard Mode: disable mouse, scan code convert, enable kbd IRQ
520
+ Ps2ctr = (I8042_CTR_AUXDIS | I8042_CTR_XLATE
521
+ | (CONFIG_HARDWARE_IRQ ? I8042_CTR_KBDINT : 0));
522
+
523
+ /* Enable keyboard */
524
+ ret = ps2_kbd_command(ATKBD_CMD_ENABLE, NULL);
525
+ if (ret)
526
+ return;
527
+
528
+ dprintf(1, "PS2 keyboard initialized\n");
529
+ }
530
+
531
+ void
532
+ ps2port_setup(void)
533
+ {
534
+ ASSERT32FLAT();
535
+ if (! CONFIG_PS2PORT)
536
+ return;
537
+ dprintf(3, "init ps2port\n");
538
+
539
+ enable_hwirq(1, FUNC16(entry_09));
540
+ enable_hwirq(12, FUNC16(entry_74));
541
+
542
+ run_thread(ps2_keyboard_setup, NULL);
543
+ }
@@ -0,0 +1,67 @@
1
+ // Basic ps2 port (keyboard/mouse) command handling.
2
+ #ifndef __PS2PORT_H
3
+ #define __PS2PORT_H
4
+
5
+ #include "types.h" // u8
6
+
7
+ #define PORT_PS2_DATA 0x0060
8
+ #define PORT_PS2_STATUS 0x0064
9
+
10
+ // Standard commands.
11
+ #define I8042_CMD_CTL_RCTR 0x0120
12
+ #define I8042_CMD_CTL_WCTR 0x1060
13
+ #define I8042_CMD_CTL_TEST 0x01aa
14
+
15
+ #define I8042_CMD_KBD_TEST 0x01ab
16
+ #define I8042_CMD_KBD_DISABLE 0x00ad
17
+ #define I8042_CMD_KBD_ENABLE 0x00ae
18
+
19
+ #define I8042_CMD_AUX_DISABLE 0x00a7
20
+ #define I8042_CMD_AUX_ENABLE 0x00a8
21
+ #define I8042_CMD_AUX_SEND 0x10d4
22
+
23
+ // Keyboard commands
24
+ #define ATKBD_CMD_SETLEDS 0x10ed
25
+ #define ATKBD_CMD_SSCANSET 0x10f0
26
+ #define ATKBD_CMD_GETID 0x02f2
27
+ #define ATKBD_CMD_ENABLE 0x00f4
28
+ #define ATKBD_CMD_RESET_DIS 0x00f5
29
+ #define ATKBD_CMD_RESET_BAT 0x01ff
30
+
31
+ // Mouse commands
32
+ #define PSMOUSE_CMD_SETSCALE11 0x00e6
33
+ #define PSMOUSE_CMD_SETSCALE21 0x00e7
34
+ #define PSMOUSE_CMD_SETRES 0x10e8
35
+ #define PSMOUSE_CMD_GETINFO 0x03e9
36
+ #define PSMOUSE_CMD_GETID 0x02f2
37
+ #define PSMOUSE_CMD_SETRATE 0x10f3
38
+ #define PSMOUSE_CMD_ENABLE 0x00f4
39
+ #define PSMOUSE_CMD_DISABLE 0x00f5
40
+ #define PSMOUSE_CMD_RESET_BAT 0x02ff
41
+
42
+ // Status register bits.
43
+ #define I8042_STR_PARITY 0x80
44
+ #define I8042_STR_TIMEOUT 0x40
45
+ #define I8042_STR_AUXDATA 0x20
46
+ #define I8042_STR_KEYLOCK 0x10
47
+ #define I8042_STR_CMDDAT 0x08
48
+ #define I8042_STR_MUXERR 0x04
49
+ #define I8042_STR_IBF 0x02
50
+ #define I8042_STR_OBF 0x01
51
+
52
+ // Control register bits.
53
+ #define I8042_CTR_KBDINT 0x01
54
+ #define I8042_CTR_AUXINT 0x02
55
+ #define I8042_CTR_IGNKEYLOCK 0x08
56
+ #define I8042_CTR_KBDDIS 0x10
57
+ #define I8042_CTR_AUXDIS 0x20
58
+ #define I8042_CTR_XLATE 0x40
59
+
60
+ // ps2port.c
61
+ void i8042_reboot(void);
62
+ int ps2_kbd_command(int command, u8 *param);
63
+ int ps2_mouse_command(int command, u8 *param);
64
+ void ps2_check_event(void);
65
+ void ps2port_setup(void);
66
+
67
+ #endif // ps2port.h