v86 0.3.6 → 0.4.0

package/bios/seabios/src/pcibios.c

@@ -0,0 +1,241 @@
+// PCI BIOS (int 1a/b1) calls
+//
+// Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2002  MandrakeSoft S.A.
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "biosvar.h" // GET_GLOBAL
+#include "bregs.h" // struct bregs
+#include "hw/pci.h" // pci_config_readl
+#include "hw/pcidevice.h" // MaxPCIBus
+#include "hw/pci_regs.h" // PCI_VENDOR_ID
+#include "output.h" // dprintf
+#include "std/pirtable.h" // struct pir_header
+#include "string.h" // checksum
+#include "util.h" // handle_1ab1
+
+// romlayout.S
+extern void entry_bios32(void);
+extern void entry_pcibios32(void);
+
+#define RET_FUNC_NOT_SUPPORTED 0x81
+#define RET_BAD_VENDOR_ID      0x83
+#define RET_DEVICE_NOT_FOUND   0x86
+#define RET_BUFFER_TOO_SMALL   0x89
+
+// installation check
+static void
+handle_1ab101(struct bregs *regs)
+{
+    regs->al = 0x01; // Flags - "Config Mechanism #1" supported.
+    regs->bx = 0x0210; // PCI version 2.10
+    regs->cl = GET_GLOBAL(MaxPCIBus);
+    regs->edx = 0x20494350; // "PCI "
+    regs->edi = (u32)entry_pcibios32 + BUILD_BIOS_ADDR;
+    set_code_success(regs);
+}
+
+// find pci device
+static void
+handle_1ab102(struct bregs *regs)
+{
+    u32 id = (regs->cx << 16) | regs->dx;
+    int count = regs->si;
+    int bus = -1;
+    while (bus < GET_GLOBAL(MaxPCIBus)) {
+        bus++;
+        int bdf;
+        foreachbdf(bdf, bus) {
+            u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
+            if (v != id)
+                continue;
+            if (count--)
+                continue;
+            regs->bx = bdf;
+            set_code_success(regs);
+            return;
+        }
+    }
+    set_code_invalid(regs, RET_DEVICE_NOT_FOUND);
+}
+
+// find class code
+static void
+handle_1ab103(struct bregs *regs)
+{
+    int count = regs->si;
+    u32 classprog = regs->ecx;
+    int bus = -1;
+    while (bus < GET_GLOBAL(MaxPCIBus)) {
+        bus++;
+        int bdf;
+        foreachbdf(bdf, bus) {
+            u32 v = pci_config_readl(bdf, PCI_CLASS_REVISION);
+            if ((v>>8) != classprog)
+                continue;
+            if (count--)
+                continue;
+            regs->bx = bdf;
+            set_code_success(regs);
+            return;
+        }
+    }
+    set_code_invalid(regs, RET_DEVICE_NOT_FOUND);
+}
+
+// read configuration byte
+static void
+handle_1ab108(struct bregs *regs)
+{
+    regs->cl = pci_config_readb(regs->bx, regs->di);
+    set_code_success(regs);
+}
+
+// read configuration word
+static void
+handle_1ab109(struct bregs *regs)
+{
+    regs->cx = pci_config_readw(regs->bx, regs->di);
+    set_code_success(regs);
+}
+
+// read configuration dword
+static void
+handle_1ab10a(struct bregs *regs)
+{
+    regs->ecx = pci_config_readl(regs->bx, regs->di);
+    set_code_success(regs);
+}
+
+// write configuration byte
+static void
+handle_1ab10b(struct bregs *regs)
+{
+    pci_config_writeb(regs->bx, regs->di, regs->cl);
+    set_code_success(regs);
+}
+
+// write configuration word
+static void
+handle_1ab10c(struct bregs *regs)
+{
+    pci_config_writew(regs->bx, regs->di, regs->cx);
+    set_code_success(regs);
+}
+
+// write configuration dword
+static void
+handle_1ab10d(struct bregs *regs)
+{
+    pci_config_writel(regs->bx, regs->di, regs->ecx);
+    set_code_success(regs);
+}
+
+// get irq routing options
+static void
+handle_1ab10e(struct bregs *regs)
+{
+    struct pir_header *pirtable_gf = GET_GLOBAL(PirAddr);
+    if (! pirtable_gf) {
+        set_code_invalid(regs, RET_FUNC_NOT_SUPPORTED);
+        return;
+    }
+    struct pir_header *pirtable_g = GLOBALFLAT2GLOBAL(pirtable_gf);
+
+    struct param_s {
+        u16 size;
+        u16 buf_off;
+        u16 buf_seg;
+    } *param_far = (void*)(regs->di+0);
+
+    // Validate and update size.
+    u16 bufsize = GET_FARVAR(regs->es, param_far->size);
+    u16 pirsize = GET_GLOBAL(pirtable_g->size) - sizeof(struct pir_header);
+    SET_FARVAR(regs->es, param_far->size, pirsize);
+    if (bufsize < pirsize) {
+        set_code_invalid(regs, RET_BUFFER_TOO_SMALL);
+        return;
+    }
+
+    // Get dest buffer.
+    void *buf_far = (void*)(GET_FARVAR(regs->es, param_far->buf_off)+0);
+    u16 buf_seg = GET_FARVAR(regs->es, param_far->buf_seg);
+
+    // Memcpy pir table slots to dest buffer.
+    memcpy_far(buf_seg, buf_far
+               , get_global_seg()
+               , (void*)(pirtable_g->slots) + get_global_offset()
+               , pirsize);
+
+    // XXX - bochs bios sets bx to (1 << 9) | (1 << 11)
+    regs->bx = GET_GLOBAL(pirtable_g->exclusive_irqs);
+    set_code_success(regs);
+}
+
+static void
+handle_1ab1XX(struct bregs *regs)
+{
+    set_code_unimplemented(regs, RET_FUNC_NOT_SUPPORTED);
+}
+
+void
+handle_1ab1(struct bregs *regs)
+{
+    //debug_stub(regs);
+
+    if (! CONFIG_PCIBIOS) {
+        set_invalid(regs);
+        return;
+    }
+
+    switch (regs->al) {
+    case 0x01: handle_1ab101(regs); break;
+    case 0x02: handle_1ab102(regs); break;
+    case 0x03: handle_1ab103(regs); break;
+    case 0x08: handle_1ab108(regs); break;
+    case 0x09: handle_1ab109(regs); break;
+    case 0x0a: handle_1ab10a(regs); break;
+    case 0x0b: handle_1ab10b(regs); break;
+    case 0x0c: handle_1ab10c(regs); break;
+    case 0x0d: handle_1ab10d(regs); break;
+    case 0x0e: handle_1ab10e(regs); break;
+    default:   handle_1ab1XX(regs); break;
+    }
+}
+
+// Entry point for pci bios functions.
+void VISIBLE16 VISIBLE32SEG
+handle_pcibios(struct bregs *regs)
+{
+    debug_enter(regs, DEBUG_HDL_pcibios);
+    handle_1ab1(regs);
+}
+
+
+/****************************************************************
+ * 32bit interface
+ ****************************************************************/
+
+struct bios32_s {
+    u32 signature;
+    u32 entry;
+    u8 version;
+    u8 length;
+    u8 checksum;
+    u8 reserved[5];
+} PACKED;
+
+struct bios32_s BIOS32HEADER __aligned(16) VARFSEG = {
+    .signature = 0x5f32335f, // _32_
+    .length = sizeof(BIOS32HEADER) / 16,
+};
+
+void
+bios32_init(void)
+{
+    dprintf(3, "init bios32\n");
+
+    BIOS32HEADER.entry = (u32)entry_bios32;
+    BIOS32HEADER.checksum -= checksum(&BIOS32HEADER, sizeof(BIOS32HEADER));
+}

package/bios/seabios/src/pmm.c

@@ -0,0 +1,176 @@
+// Post memory manager (PMM) calls
+//
+// Copyright (C) 2009-2013  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "biosvar.h" // FUNC16
+#include "config.h" // CONFIG_*
+#include "malloc.h" // _malloc
+#include "output.h" // dprintf
+#include "e820map.h" // struct e820entry
+#include "std/pmm.h" // PMM_SIGNATURE
+#include "string.h" // checksum
+#include "util.h" // pmm_init
+#include "x86.h" // __ffs
+
+extern struct pmmheader PMMHEADER;
+
+#if CONFIG_PMM
+struct pmmheader PMMHEADER __aligned(16) VARFSEG = {
+    .signature = PMM_SIGNATURE,
+    .version = 0x01,
+    .length = sizeof(PMMHEADER),
+};
+#endif
+
+// PMM - allocate
+static u32
+handle_pmm00(u16 *args)
+{
+    u32 length = *(u32*)&args[1], handle = *(u32*)&args[3];
+    u16 flags = args[5];
+    dprintf(3, "pmm00: length=%x handle=%x flags=%x\n"
+            , length, handle, flags);
+    struct zone_s *lowzone = &ZoneTmpLow, *highzone = &ZoneTmpHigh;
+    if (flags & 8) {
+        // Permanent memory request.
+        lowzone = &ZoneLow;
+        highzone = &ZoneHigh;
+    }
+    if (!length) {
+        // Memory size request
+        switch (flags & 3) {
+        default:
+        case 0:
+            return 0;
+        case 1:
+            return malloc_getspace(lowzone);
+        case 2:
+            return malloc_getspace(highzone);
+        case 3: {
+            u32 spacelow = malloc_getspace(lowzone);
+            u32 spacehigh = malloc_getspace(highzone);
+            if (spacelow > spacehigh)
+                return spacelow;
+            return spacehigh;
+        }
+        }
+    }
+    u32 size = length * 16;
+    if ((s32)size <= 0)
+        return 0;
+    u32 align = MALLOC_MIN_ALIGN;
+    if (flags & 4) {
+        align = 1<<__ffs(size);
+        if (align < MALLOC_MIN_ALIGN)
+            align = MALLOC_MIN_ALIGN;
+    }
+    u32 data;
+    switch (flags & 3) {
+    default:
+    case 0:
+        return 0;
+    case 1:
+        data = malloc_palloc(lowzone, size, align);
+        break;
+    case 2:
+        data = malloc_palloc(highzone, size, align);
+        if (!data && (flags & 8)) {
+            /*
+             * We are out of meory.  So go allocate from the (big)
+             * ZoneTmpHigh instead and reserve the block in the e820
+             * map so the OS will not override it.  That way we can
+             * handle big permanent allocations without needing a big
+             * ZoneHigh.
+             */
+            data = malloc_palloc(&ZoneTmpHigh, size, align);
+            if (data)
+                e820_add(data, size, E820_RESERVED);
+        }
+        break;
+    case 3: {
+        data = malloc_palloc(lowzone, size, align);
+        if (!data)
+            data = malloc_palloc(highzone, size, align);
+    }
+    }
+    if (data && handle != MALLOC_DEFAULT_HANDLE)
+        malloc_sethandle(data, handle);
+    return data;
+}
+
+// PMM - find
+static u32
+handle_pmm01(u16 *args)
+{
+    u32 handle = *(u32*)&args[1];
+    dprintf(3, "pmm01: handle=%x\n", handle);
+    if (handle == MALLOC_DEFAULT_HANDLE)
+        return 0;
+    return malloc_findhandle(handle);
+}
+
+// PMM - deallocate
+static u32
+handle_pmm02(u16 *args)
+{
+    u32 buffer = *(u32*)&args[1];
+    dprintf(3, "pmm02: buffer=%x\n", buffer);
+    int ret = malloc_pfree(buffer);
+    if (ret)
+        // Error
+        return 1;
+    return 0;
+}
+
+static u32
+handle_pmmXX(u16 *args)
+{
+    return PMM_FUNCTION_NOT_SUPPORTED;
+}
+
+u32 VISIBLE32INIT
+handle_pmm(u16 *args)
+{
+    ASSERT32FLAT();
+    if (! CONFIG_PMM)
+        return PMM_FUNCTION_NOT_SUPPORTED;
+
+    u16 arg1 = args[0];
+    dprintf(DEBUG_HDL_pmm, "pmm call arg1=%x\n", arg1);
+
+    u32 ret;
+    switch (arg1) {
+    case 0x00: ret = handle_pmm00(args); break;
+    case 0x01: ret = handle_pmm01(args); break;
+    case 0x02: ret = handle_pmm02(args); break;
+    default:   ret = handle_pmmXX(args); break;
+    }
+
+    return ret;
+}
+
+void
+pmm_init(void)
+{
+    if (! CONFIG_PMM)
+        return;
+
+    dprintf(3, "init PMM\n");
+
+    PMMHEADER.entry = FUNC16(entry_pmm);
+    PMMHEADER.checksum -= checksum(&PMMHEADER, sizeof(PMMHEADER));
+}
+
+void
+pmm_prepboot(void)
+{
+    if (! CONFIG_PMM)
+        return;
+
+    dprintf(3, "finalize PMM\n");
+
+    PMMHEADER.signature = 0;
+    PMMHEADER.entry.segoff = 0;
+}

package/bios/seabios/src/pnpbios.c

@@ -0,0 +1,88 @@
+// PNP BIOS calls
+//
+// Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "config.h" // BUILD_BIOS_ADDR
+#include "farptr.h" // SET_FARVAR
+#include "output.h" // dprintf
+#include "std/pnpbios.h" // PNP_SIGNATURE
+#include "string.h" // checksum
+#include "util.h" // pnp_init
+
+extern struct pnpheader PNPHEADER;
+extern char pnp_string[];
+
+#if CONFIG_PNPBIOS
+struct pnpheader PNPHEADER __aligned(16) VARFSEG = {
+    .signature = PNP_SIGNATURE,
+    .version = 0x10,
+    .length = sizeof(PNPHEADER),
+    .real_cs = SEG_BIOS,
+    .prot_base = BUILD_BIOS_ADDR,
+    .real_ds = SEG_BIOS,
+    .prot_database = BUILD_BIOS_ADDR,
+};
+#else
+// We need a copy of this string in the 0xf000 segment, but we are not
+// actually a PnP BIOS, so make sure it is *not* aligned, so OSes will
+// not see it if they scan.
+char pnp_string[] __aligned(2) VARFSEG = " $PnP";
+#endif
+
+// BBS - Get Version and Installation Check
+static u16
+handle_pnp60(u16 *args)
+{
+    u16 version_ptr = args[1];
+    u16 version_seg = args[2];
+    SET_FARVAR(version_seg, *(u16*)(version_ptr+0), 0x0101);
+    return 0;
+}
+
+static u16
+handle_pnpXX(u16 *args)
+{
+    return FUNCTION_NOT_SUPPORTED;
+}
+
+u16 VISIBLE16
+handle_pnp(u16 *args)
+{
+    if (! CONFIG_PNPBIOS)
+        return FUNCTION_NOT_SUPPORTED;
+
+    u16 arg1 = args[0];
+    dprintf(DEBUG_HDL_pnp, "pnp call arg1=%x\n", arg1);
+
+    switch (arg1) {
+    case 0x60: return handle_pnp60(args);
+    default:   return handle_pnpXX(args);
+    }
+}
+
+u16
+get_pnp_offset(void)
+{
+    if (! CONFIG_PNPBIOS)
+        return (u32)pnp_string + 1 - BUILD_BIOS_ADDR;
+    return (u32)&PNPHEADER - BUILD_BIOS_ADDR;
+}
+
+// romlayout.S
+extern void entry_pnp_real(void);
+extern void entry_pnp_prot(void);
+
+void
+pnp_init(void)
+{
+    if (! CONFIG_PNPBIOS)
+        return;
+
+    dprintf(3, "init PNPBIOS table\n");
+
+    PNPHEADER.real_ip = (u32)entry_pnp_real - BUILD_BIOS_ADDR;
+    PNPHEADER.prot_ip = (u32)entry_pnp_prot - BUILD_BIOS_ADDR;
+    PNPHEADER.checksum -= checksum(&PNPHEADER, sizeof(PNPHEADER));
+}