v86 0.3.6 → 0.4.0

package/bios/seabios/src/vgahooks.c

@@ -0,0 +1,355 @@
+// Hooks for via vgabios calls into main bios.
+//
+// Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "biosvar.h" // GET_GLOBAL
+#include "bregs.h" // set_code_invalid
+#include "config.h" // CONFIG_*
+#include "hw/pci.h" // pci_config_readb
+#include "hw/pcidevice.h" // pci_find_device
+#include "hw/pci_ids.h" // PCI_VENDOR_ID_VIA
+#include "hw/pci_regs.h" // PCI_VENDOR_ID
+#include "output.h" // dprintf
+#include "string.h" // strcmp
+#include "util.h" // handle_155f, handle_157f
+
+#define VH_VIA 1
+#define VH_INTEL 2
+#define VH_SMI 3
+
+int VGAHookHandlerType VARFSEG;
+
+static void
+handle_155fXX(struct bregs *regs)
+{
+    set_code_unimplemented(regs, RET_EUNSUPPORTED);
+}
+
+static void
+handle_157fXX(struct bregs *regs)
+{
+    set_code_unimplemented(regs, RET_EUNSUPPORTED);
+}
+
+/****************************************************************
+ * Via hooks
+ ****************************************************************/
+
+int ViaFBsize VARFSEG, ViaRamSpeed VARFSEG;
+
+static void
+via_155f01(struct bregs *regs)
+{
+    regs->eax = 0x5f;
+    regs->cl = 2; // panel type =  2 = 1024 * 768
+    set_success(regs);
+    dprintf(1, "Warning: VGA panel type is hardcoded\n");
+}
+
+static void
+via_155f02(struct bregs *regs)
+{
+    regs->eax = 0x5f;
+    regs->bx = 2;
+    regs->cx = 0x401;  // PAL + crt only
+    regs->dx = 0;  // TV Layout - default
+    set_success(regs);
+    dprintf(1, "Warning: VGA TV/CRT output type is hardcoded\n");
+}
+
+static void
+via_155f18(struct bregs *regs)
+{
+    int fbsize = GET_GLOBAL(ViaFBsize), ramspeed = GET_GLOBAL(ViaRamSpeed);
+    if (fbsize < 0 || ramspeed < 0) {
+        set_code_invalid(regs, RET_EUNSUPPORTED);
+        return;
+    }
+    regs->eax = 0x5f;
+    regs->ebx = 0x500 | (ramspeed << 4) | fbsize;
+    regs->ecx = 0x060;
+    set_success(regs);
+}
+
+static void
+via_155f19(struct bregs *regs)
+{
+    set_invalid_silent(regs);
+}
+
+static void
+via_155f(struct bregs *regs)
+{
+    switch (regs->al) {
+    case 0x01: via_155f01(regs); break;
+    case 0x02: via_155f02(regs); break;
+    case 0x18: via_155f18(regs); break;
+    case 0x19: via_155f19(regs); break;
+    default:   handle_155fXX(regs); break;
+    }
+}
+
+static int
+getFBSize(struct pci_device *pci)
+{
+    /* FB config */
+    u8 reg = pci_config_readb(pci->bdf, 0xa1);
+
+    /* GFX disabled ? */
+    if (!(reg & 0x80))
+        return -1;
+
+    static u8 mem_power[] = {0, 3, 4, 5, 6, 7, 8, 9};
+    return mem_power[(reg >> 4) & 0x7];
+}
+
+static int
+getViaRamSpeed(struct pci_device *pci)
+{
+    return (pci_config_readb(pci->bdf, 0x90) & 0x07) + 3;
+}
+
+static int
+getAMDRamSpeed(void)
+{
+    struct pci_device *pci = pci_find_device(PCI_VENDOR_ID_AMD
+                                             , PCI_DEVICE_ID_AMD_K8_NB_MEMCTL);
+    if (!pci)
+        return -1;
+
+    /* mem clk 0 = DDR2 400 */
+    return (pci_config_readb(pci->bdf, 0x94) & 0x7) + 6;
+}
+
+/* int 0x15 - 5f18
+
+   ECX = unknown/don't care
+   EBX[3..0] Frame Buffer Size 2^N MiB
+   EBX[7..4] Memory speed:
+       0: SDR  66Mhz
+       1: SDR 100Mhz
+       2: SDR 133Mhz
+       3: DDR 100Mhz (PC1600 or DDR200)
+       4: DDR 133Mhz (PC2100 or DDR266)
+       5: DDR 166Mhz (PC2700 or DDR333)
+       6: DDR 200Mhz (PC3200 or DDR400)
+       7: DDR2 133Mhz (DDR2 533)
+       8: DDR2 166Mhz (DDR2 667)
+       9: DDR2 200Mhz (DDR2 800)
+       A: DDR2 233Mhz (DDR2 1066)
+       B: and above: Unknown
+   EBX[?..8] Total memory size?
+   EAX = 0x5f for success
+*/
+
+#define PCI_DEVICE_ID_VIA_K8M890CE_3    0x3336
+#define PCI_DEVICE_ID_VIA_VX855_MEMCTRL 0x3409
+
+static void
+via_setup(struct pci_device *pci)
+{
+    VGAHookHandlerType = VH_VIA;
+
+    struct pci_device *d = pci_find_device(PCI_VENDOR_ID_VIA
+                                           , PCI_DEVICE_ID_VIA_K8M890CE_3);
+    if (d) {
+        ViaFBsize = getFBSize(d);
+        ViaRamSpeed = getAMDRamSpeed();
+        return;
+    }
+    d = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_MEMCTRL);
+    if (d) {
+        ViaFBsize = getFBSize(d);
+        ViaRamSpeed = getViaRamSpeed(d);
+        return;
+    }
+
+    dprintf(1, "Warning: VGA memory size and speed is hardcoded\n");
+    ViaFBsize = 5; // 32M frame buffer
+    ViaRamSpeed = 4; // MCLK = DDR266
+}
+
+
+/****************************************************************
+ * Intel VGA hooks
+ ****************************************************************/
+
+u8 IntelDisplayType VARFSEG, IntelDisplayId VARFSEG;
+
+static void
+intel_155f35(struct bregs *regs)
+{
+    regs->ax = 0x005f;
+    regs->cl = GET_GLOBAL(IntelDisplayType);
+    set_success(regs);
+}
+
+static void
+intel_155f40(struct bregs *regs)
+{
+    regs->ax = 0x005f;
+    regs->cl = GET_GLOBAL(IntelDisplayId);
+    set_success(regs);
+}
+
+static void
+intel_155f50(struct bregs *regs)
+{
+    /* Mandatory hook on some Dell laptops */
+    regs->ax = 0x005f;
+    set_success(regs);
+}
+
+static void
+intel_155f(struct bregs *regs)
+{
+    switch (regs->al) {
+    case 0x35: intel_155f35(regs); break;
+    case 0x40: intel_155f40(regs); break;
+    case 0x50: intel_155f50(regs); break;
+    default:   handle_155fXX(regs); break;
+    }
+}
+
+#define BOOT_DISPLAY_DEFAULT    (0)
+#define BOOT_DISPLAY_CRT        (1 << 0)
+#define BOOT_DISPLAY_TV         (1 << 1)
+#define BOOT_DISPLAY_EFP        (1 << 2)
+#define BOOT_DISPLAY_LCD        (1 << 3)
+#define BOOT_DISPLAY_CRT2       (1 << 4)
+#define BOOT_DISPLAY_TV2        (1 << 5)
+#define BOOT_DISPLAY_EFP2       (1 << 6)
+#define BOOT_DISPLAY_LCD2       (1 << 7)
+
+static void
+intel_setup(struct pci_device *pci)
+{
+    VGAHookHandlerType = VH_INTEL;
+
+    IntelDisplayType = BOOT_DISPLAY_DEFAULT;
+    IntelDisplayId = 3;
+}
+
+static void
+roda_setup(struct pci_device *pci)
+{
+    VGAHookHandlerType = VH_INTEL;
+    // IntelDisplayType = BOOT_DISPLAY_DEFAULT;
+    IntelDisplayType = BOOT_DISPLAY_LCD;
+    // IntelDisplayId = inb(0x60f) & 0x0f; // Correct according to Crete
+    IntelDisplayId = 3; // Correct according to empirical studies
+}
+
+static void
+kontron_setup(struct pci_device *pci)
+{
+    VGAHookHandlerType = VH_INTEL;
+    IntelDisplayType = BOOT_DISPLAY_CRT;
+    IntelDisplayId = 3;
+}
+
+static void
+getac_setup(struct pci_device *pci)
+{
+}
+
+/****************************************************************
+ * Silicon Motion hooks
+ ****************************************************************/
+
+u8 SmiBootDisplay VARFSEG; // 1: LCD, 2: CRT, 3: Both */
+
+static void
+smi_157f02(struct bregs *regs)
+{
+    /* Boot Display Device Override */
+    regs->ax = 0x007f;
+    regs->bl = GET_GLOBAL(SmiBootDisplay);
+    set_success(regs);
+}
+
+static void
+smi_157f14(struct bregs *regs)
+{
+    /* ReduceOn support default status */
+    regs->ax = 0x007f;
+    regs->bl = 0x00;
+    set_success(regs);
+}
+
+static void
+smi_157f(struct bregs *regs)
+{
+    switch (regs->al) {
+    case 0x02: smi_157f02(regs); break;
+    case 0x14: smi_157f14(regs); break;
+    default:   handle_157fXX(regs); break;
+    }
+}
+
+static void
+winent_mb6047_setup(struct pci_device *pci)
+{
+    VGAHookHandlerType = VH_SMI;
+    SmiBootDisplay = 0x02;
+}
+
+/****************************************************************
+ * Entry and setup
+ ****************************************************************/
+
+// Main 16bit entry point
+void
+handle_155f(struct bregs *regs)
+{
+    if (!CONFIG_VGAHOOKS) {
+        handle_155fXX(regs);
+        return;
+    }
+
+    int htype = GET_GLOBAL(VGAHookHandlerType);
+    switch (htype) {
+    case VH_VIA:   via_155f(regs); break;
+    case VH_INTEL: intel_155f(regs); break;
+    default:       handle_155fXX(regs); break;
+    }
+}
+
+// Main 16bit entry point
+void
+handle_157f(struct bregs *regs)
+{
+    if (!CONFIG_VGAHOOKS) {
+        handle_157fXX(regs);
+        return;
+    }
+
+    int htype = GET_GLOBAL(VGAHookHandlerType);
+    switch (htype) {
+    case VH_SMI:   smi_157f(regs); break;
+    default:       handle_157fXX(regs); break;
+    }
+}
+
+// Setup
+void
+vgahook_setup(struct pci_device *pci)
+{
+    if (!CONFIG_VGAHOOKS)
+        return;
+
+    if (strcmp(CBvendor, "KONTRON") == 0 && strcmp(CBpart, "986LCD-M") == 0)
+        kontron_setup(pci);
+    else if (strcmp(CBvendor, "GETAC") == 0 && strcmp(CBpart, "P470") == 0)
+        getac_setup(pci);
+    else if (strcmp(CBvendor, "RODA") == 0 && strcmp(CBpart, "RK886EX") == 0)
+        roda_setup(pci);
+    else if (strcmp(CBvendor, "Win Enterprise") == 0 && strcmp(CBpart, "MB6047") == 0)
+        winent_mb6047_setup(pci);
+    else if (pci->vendor == PCI_VENDOR_ID_VIA)
+        via_setup(pci);
+    else if (pci->vendor == PCI_VENDOR_ID_INTEL)
+        intel_setup(pci);
+}

package/bios/seabios/src/x86.c

@@ -0,0 +1,23 @@
+// X86 utility functions.
+//
+// Copyright (C) 2013  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "x86.h" // __cpuid
+
+void
+cpuid(u32 index, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
+{
+    // Check for cpu id
+    u32 origflags = save_flags();
+    restore_flags(origflags ^ F_ID);
+    u32 newflags = save_flags();
+    restore_flags(origflags);
+
+    if (((origflags ^ newflags) & F_ID) != F_ID)
+        // no cpuid
+        *eax = *ebx = *ecx = *edx = 0;
+    else
+        __cpuid(index, eax, ebx, ecx, edx);
+}

package/bios/seabios/src/x86.h

@@ -0,0 +1,277 @@
+// Basic x86 asm functions.
+#ifndef __X86_H
+#define __X86_H
+
+// CPU flag bitdefs
+#define F_CF (1<<0)
+#define F_ZF (1<<6)
+#define F_IF (1<<9)
+#define F_ID (1<<21)
+
+// CR0 flags
+#define CR0_PG (1<<31) // Paging
+#define CR0_CD (1<<30) // Cache disable
+#define CR0_NW (1<<29) // Not Write-through
+#define CR0_PE (1<<0)  // Protection enable
+
+// PORT_A20 bitdefs
+#define PORT_A20 0x0092
+#define A20_ENABLE_BIT 0x02
+
+#ifndef __ASSEMBLY__
+
+#include "types.h" // u32
+
+static inline void irq_disable(void)
+{
+    asm volatile("cli": : :"memory");
+}
+
+static inline void irq_enable(void)
+{
+    asm volatile("sti": : :"memory");
+}
+
+static inline u32 save_flags(void)
+{
+    u32 flags;
+    asm volatile("pushfl ; popl %0" : "=rm" (flags));
+    return flags;
+}
+
+static inline void restore_flags(u32 flags)
+{
+    asm volatile("pushl %0 ; popfl" : : "g" (flags) : "memory", "cc");
+}
+
+static inline void cpu_relax(void)
+{
+    asm volatile("rep ; nop": : :"memory");
+}
+
+static inline void nop(void)
+{
+    asm volatile("nop");
+}
+
+static inline void hlt(void)
+{
+    asm volatile("hlt": : :"memory");
+}
+
+static inline void wbinvd(void)
+{
+    asm volatile("wbinvd": : :"memory");
+}
+
+#define CPUID_TSC (1 << 4)
+#define CPUID_MSR (1 << 5)
+#define CPUID_APIC (1 << 9)
+#define CPUID_MTRR (1 << 12)
+#define CPUID_X2APIC (1 << 21)
+static inline void __cpuid(u32 index, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
+{
+    asm("cpuid"
+        : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+        : "0" (index));
+}
+
+static inline u32 cr0_read(void) {
+    u32 cr0;
+    asm("movl %%cr0, %0" : "=r"(cr0));
+    return cr0;
+}
+static inline void cr0_write(u32 cr0) {
+    asm("movl %0, %%cr0" : : "r"(cr0));
+}
+static inline void cr0_mask(u32 off, u32 on) {
+    cr0_write((cr0_read() & ~off) | on);
+}
+static inline u16 cr0_vm86_read(void) {
+    u16 cr0;
+    asm("smsww %0" : "=r"(cr0));
+    return cr0;
+}
+
+static inline u64 rdmsr(u32 index)
+{
+    u64 ret;
+    asm ("rdmsr" : "=A"(ret) : "c"(index));
+    return ret;
+}
+
+static inline void wrmsr(u32 index, u64 val)
+{
+    asm volatile ("wrmsr" : : "c"(index), "A"(val));
+}
+
+static inline u64 rdtscll(void)
+{
+    u64 val;
+    asm volatile("rdtsc" : "=A" (val));
+    return val;
+}
+
+static inline u32 __ffs(u32 word)
+{
+    asm("bsf %1,%0"
+        : "=r" (word)
+        : "rm" (word));
+    return word;
+}
+static inline u32 __fls(u32 word)
+{
+    asm("bsr %1,%0"
+        : "=r" (word)
+        : "rm" (word));
+    return word;
+}
+
+static inline u32 getesp(void) {
+    u32 esp;
+    asm("movl %%esp, %0" : "=rm"(esp));
+    return esp;
+}
+
+static inline u32 rol(u32 val, u16 rol) {
+    u32 res;
+    asm volatile("roll %%cl, %%eax"
+                 : "=a" (res) : "a" (val), "c" (rol));
+    return res;
+}
+
+static inline void outb(u8 value, u16 port) {
+    __asm__ __volatile__("outb %b0, %w1" : : "a"(value), "Nd"(port));
+}
+static inline void outw(u16 value, u16 port) {
+    __asm__ __volatile__("outw %w0, %w1" : : "a"(value), "Nd"(port));
+}
+static inline void outl(u32 value, u16 port) {
+    __asm__ __volatile__("outl %0, %w1" : : "a"(value), "Nd"(port));
+}
+static inline u8 inb(u16 port) {
+    u8 value;
+    __asm__ __volatile__("inb %w1, %b0" : "=a"(value) : "Nd"(port));
+    return value;
+}
+static inline u16 inw(u16 port) {
+    u16 value;
+    __asm__ __volatile__("inw %w1, %w0" : "=a"(value) : "Nd"(port));
+    return value;
+}
+static inline u32 inl(u16 port) {
+    u32 value;
+    __asm__ __volatile__("inl %w1, %0" : "=a"(value) : "Nd"(port));
+    return value;
+}
+
+static inline void insb(u16 port, u8 *data, u32 count) {
+    asm volatile("rep insb (%%dx), %%es:(%%edi)"
+                 : "+c"(count), "+D"(data) : "d"(port) : "memory");
+}
+static inline void insw(u16 port, u16 *data, u32 count) {
+    asm volatile("rep insw (%%dx), %%es:(%%edi)"
+                 : "+c"(count), "+D"(data) : "d"(port) : "memory");
+}
+static inline void insl(u16 port, u32 *data, u32 count) {
+    asm volatile("rep insl (%%dx), %%es:(%%edi)"
+                 : "+c"(count), "+D"(data) : "d"(port) : "memory");
+}
+// XXX - outs not limited to es segment
+static inline void outsb(u16 port, u8 *data, u32 count) {
+    asm volatile("rep outsb %%es:(%%esi), (%%dx)"
+                 : "+c"(count), "+S"(data) : "d"(port) : "memory");
+}
+static inline void outsw(u16 port, u16 *data, u32 count) {
+    asm volatile("rep outsw %%es:(%%esi), (%%dx)"
+                 : "+c"(count), "+S"(data) : "d"(port) : "memory");
+}
+static inline void outsl(u16 port, u32 *data, u32 count) {
+    asm volatile("rep outsl %%es:(%%esi), (%%dx)"
+                 : "+c"(count), "+S"(data) : "d"(port) : "memory");
+}
+
+/* Compiler barrier is enough as an x86 CPU does not reorder reads or writes */
+static inline void smp_rmb(void) {
+    barrier();
+}
+static inline void smp_wmb(void) {
+    barrier();
+}
+
+static inline void writel(void *addr, u32 val) {
+    barrier();
+    *(volatile u32 *)addr = val;
+}
+static inline void writew(void *addr, u16 val) {
+    barrier();
+    *(volatile u16 *)addr = val;
+}
+static inline void writeb(void *addr, u8 val) {
+    barrier();
+    *(volatile u8 *)addr = val;
+}
+static inline u64 readq(const void *addr) {
+    u64 val = *(volatile const u64 *)addr;
+    barrier();
+    return val;
+}
+static inline u32 readl(const void *addr) {
+    u32 val = *(volatile const u32 *)addr;
+    barrier();
+    return val;
+}
+static inline u16 readw(const void *addr) {
+    u16 val = *(volatile const u16 *)addr;
+    barrier();
+    return val;
+}
+static inline u8 readb(const void *addr) {
+    u8 val = *(volatile const u8 *)addr;
+    barrier();
+    return val;
+}
+
+// GDT bits
+#define GDT_CODE     (0x9bULL << 40) // Code segment - P,R,A bits also set
+#define GDT_DATA     (0x93ULL << 40) // Data segment - W,A bits also set
+#define GDT_B        (0x1ULL << 54)  // Big flag
+#define GDT_G        (0x1ULL << 55)  // Granularity flag
+// GDT bits for segment base
+#define GDT_BASE(v)  ((((u64)(v) & 0xff000000) << 32)           \
+                      | (((u64)(v) & 0x00ffffff) << 16))
+// GDT bits for segment limit (0-1Meg)
+#define GDT_LIMIT(v) ((((u64)(v) & 0x000f0000) << 32)   \
+                      | (((u64)(v) & 0x0000ffff) << 0))
+// GDT bits for segment limit (0-4Gig in 4K chunks)
+#define GDT_GRANLIMIT(v) (GDT_G | GDT_LIMIT((v) >> 12))
+
+struct descloc_s {
+    u16 length;
+    u32 addr;
+} PACKED;
+
+static inline void sgdt(struct descloc_s *desc) {
+    asm("sgdtl %0" : "=m"(*desc));
+}
+static inline void lgdt(struct descloc_s *desc) {
+    asm("lgdtl %0" : : "m"(*desc) : "memory");
+}
+
+static inline u8 get_a20(void) {
+    return (inb(PORT_A20) & A20_ENABLE_BIT) != 0;
+}
+
+static inline u8 set_a20(u8 cond) {
+    u8 val = inb(PORT_A20), a20_enabled = (val & A20_ENABLE_BIT) != 0;
+    if (a20_enabled != !!cond)
+        outb(val ^ A20_ENABLE_BIT, PORT_A20);
+    return a20_enabled;
+}
+
+// x86.c
+void cpuid(u32 index, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx);
+
+#endif // !__ASSEMBLY__
+
+#endif // x86.h