romdev-mcp 0.1.1

package/src/platforms/snes/lib/pvsneslib/source/libtcc.asm

@@ -0,0 +1,374 @@
+.INCLUDE "hdr.asm"
+
+.ifdef FASTROM
+.BASE $80
+.endif
+
+.BANK 1
+
+.DEFINE ORG_0 0
+.ifdef HIROM
+.REDEFINE ORG_0 $8000
+.endif
+
+.SECTION ".libc_mem" SEMIFREE ORG ORG_0
+
+.accu 16
+.index 16
+.16bit
+
+; multiplication implementation lifted from WDC's "Programming the 65816"
+tcc__mul:
+	lda #0
+	.repeat 4
+	.repeat 4
+	ldx.b tcc__r9
+	beq ++
+	lsr.b tcc__r9
+	bcc +
+	clc
+	adc.b tcc__r10
++   asl.b tcc__r10
+	.endr
+++
+	.endr
+  rtl
+
+; adapted from 6502 16x16 mult (same manual)
+; this is a 32x32 => 32 multiplication routine
+; we actually only need 16x16 => 32, maybe there's something to optimize
+; here...
+; alternatively, one could fix tcc to use a 32x32 multiply.
+tcc__mull:
+      ldx #0
+      ldy #0
+-     lda.b tcc__r9
+      ora.b tcc__r9h
+      beq ++
+      lsr.b tcc__r9h
+      ror.b tcc__r9
+      bcc +
+      clc
+      tya
+      adc.b tcc__r10
+      tay
+      txa
+      adc.b tcc__r10h
+      tax
++     asl.b tcc__r10
+      rol.b tcc__r10h
+      bra -
+++    rtl
+
+
+; division implementation lifted from WDC's "Programming the 65816"
+; optimized by mic_
+tcc__udiv:
+	stz.b tcc__r9
+	ldy #1
+	.repeat 16
+ 	asl a
+	bcs tcc__udiv1
+	iny
+	.endr
+tcc__udiv1:
+ 	ror a
+- 	sta.b tcc__r5
+	cpx tcc__r5
+	bcc +
+	txa
+	sbc.b tcc__r5
+	tax
++ 	rol.b tcc__r9
+	lda.b tcc__r5
+	lsr a
+	dey
+	bne -
+	rtl
+
+; looks like the damn 6502 was designed before negative numbers...
+tcc__div:
+      pha
+      ldy #0	; number of negative operands
+      stz.b tcc__r10	; dividend negative?
+      txa
+      bpl +
+      eor #$ffff	; negate dividend
+      ina
+      iny
+      inc.b tcc__r10
+      tax
++     pla
+      bpl +
+      eor #$ffff	; negate divisor
+      ina
+      iny
++     phy
+      jsr.l tcc__udiv
+      ; do not overwrite x here (remainder!)
+      lda.b tcc__r9	; get quotient
+      ply	; get number of negative operands
+      cpy #1
+      bne +
+      eor #$ffff ; one neg. operand -> negate quotient
+      ina
+      sta.b tcc__r9
+      ; these extra insns graciously donated by C99
++     lda.b tcc__r10	 ; dividend negative?
+      beq +
+      txa	 ; give remainder same sign as dividend
+      eor #$ffff
+      ina
+      tax
++     rtl
+
+tcc__divl:
+      ldx.w #0	; bit 0 -> dividend neg?, bit 1 -> divisor neg?
+      bit.b tcc__r9h
+      bpl +	; dividend positive
+
+      ; negate dividend
+      inx	; set bit 0
+      lda.b tcc__r9h
+      eor.w #$ffff
+      sta.b tcc__r9h
+      lda.b tcc__r9
+      eor.w #$ffff
+      ina
+      sta.b tcc__r9
+      bne +
+      inc.b tcc__r9h
+
++     bit.b tcc__r10h
+      bpl +	; divisor positive
+
+      ; negate divisor
+      inx	; set bit 1
+      inx
+      lda.b tcc__r10h
+      eor.w #$ffff
+      sta.b tcc__r10h
+      lda.b tcc__r10
+      eor.w #$ffff
+      ina
+      sta.b tcc__r10
+      bne +
+      inc.b tcc__r10h
+
++     phx
+      jsr tcc__udivl
+      tay	; quot low word -> y (high word in x)
+      pla	; get sign flags
+      beq +++	; no sign -> all done
+      cmp.w #3
+      beq ++	; two signs -> only correct remainder
+
+      ; negate quotient
+      pha
+      txa
+      eor.w #$ffff
+      tax
+      tya
+      eor.w #$ffff
+      ina
+      bne +
+      inx
++     tay
+      pla
+
+++    bit.w #1	; dividend negative?
+      beq +++	; no -> done
+
+      ; negate remainder
+      lda.b tcc__r9h
+      eor.w #$ffff
+      sta.b tcc__r9h
+      lda.b tcc__r9
+      eor.w #$ffff
+      ina
+      sta.b tcc__r9
+      bne +++
+      inc.b tcc__r9h
+
++++   rts
+
+tcc__udivl:
+      lda.w #0
+      tax
+      pha
+      ldy.w #1
+      lda.b tcc__r10h
+      bmi _div2
+-     iny
+      asl.b tcc__r10
+      rol.b tcc__r10h
+      bmi _div2
+      cpy.w #33
+      bne -
+_div2:sec
+      lda.b tcc__r9
+      sbc.b tcc__r10
+      pha
+      lda.b tcc__r9h
+      sbc.b tcc__r10h
+      bcc +
+      sta.b tcc__r9h
+      pla
+      sta.b tcc__r9
+      pha
++     pla
+      pla
+      rol a
+      pha
+      txa
+      rol a
+      tax
+      lsr.b tcc__r10h
+      ror.b tcc__r10
+      dey
+      bne _div2
+
+      pla
+      rts
+
+tcc__divdi3:
+      lda.b 4,s
+      sta.b tcc__r9
+      lda.b 6,s
+      sta.b tcc__r9h
+      lda.b 8,s
+      sta.b tcc__r10
+      lda.b 10,s
+      sta.b tcc__r10h
+      jsr tcc__divl
+      stx.b tcc__r1	; LRET
+      sty.b tcc__r0	; IRET
+      rtl
+
+tcc__moddi3:
+      lda.b 4,s
+      sta.b tcc__r9
+      lda.b 6,s
+      sta.b tcc__r9h
+      lda.b 8,s
+      sta.b tcc__r10
+      lda.b 10,s
+      sta.b tcc__r10h
+      jsr tcc__divl
+      lda.b tcc__r9h
+      sta.b tcc__r1	; LRET
+      lda.b tcc__r9
+      sta.b tcc__r0	; IRET
+      rtl
+
+tcc__udivdi3:
+      lda.b 4,s
+      sta.b tcc__r9
+      lda.b 6,s
+      sta.b tcc__r9h
+      lda.b 8,s
+      sta.b tcc__r10
+      lda.b 10,s
+      sta.b tcc__r10h
+      jsr tcc__udivl
+      stx.b tcc__r1	; LRET
+      sta.b tcc__r0	; IRET
+      rtl
+
+tcc__umoddi3:
+      lda.b 4,s
+      sta.b tcc__r9
+      lda.b 6,s
+      sta.b tcc__r9h
+      lda.b 8,s
+      sta.b tcc__r10
+      lda.b 10,s
+      sta.b tcc__r10h
+      jsr tcc__udivl
+      lda.b tcc__r9h
+      sta.b tcc__r1	; LRET
+      lda.b tcc__r9
+      sta.b tcc__r0	; IRET
+      rtl
+
+;optimized version by mic_
+;however, it does not seem to be ever called in a fairly large project
+tcc__shldi3:
+	lda.b 6,s ; hi word
+	sta.b tcc__r1
+	lda.b 8,s ; shift count
+	beq +
+	tax
+	lda.b 4,s ; low word
+-	asl a
+	rol.b tcc__r1
+	dex
+	bne -
+	sta.b tcc__r0
+	rtl
++	lda.b 4,s ; low word
+	sta.b tcc__r0
+	rtl
+
+tcc__sardi3:
+      lda.b 4,s ; low word
+      sta.b tcc__r0
+      lda.b 6,s
+      sta.b tcc__r1
+      lda.b 8,s ; shift count
+      beq +
+      tax
+      lda.b tcc__r1
+      bpl _shr
+-     sec
+      ror.b tcc__r1
+      ror.b tcc__r0
+      dex
+      bne -
+      rtl
+_shr: lsr.b tcc__r1
+      ror.b tcc__r0
+      dex
+      bne _shr
++     rtl
+
+tcc__shrdi3:
+      lda.b 4,s
+      sta.b tcc__r0
+      lda.b 6,s
+      sta.b tcc__r1
+      lda.b 8,s
+      beq +
+      tax
+      bra _shr
++     rtl
+
+; long call to the subroutine pointed to in r10
+tcc__jsl_r10:
+      sep #$20
+      lda.b tcc__r10 + 2
+      pha
+      rep #$20
+      lda.b tcc__r10
+      dec a
+      pha
+      rtl
+
+; long call to the subroutine pointed to by the pointer r9 points to...
+tcc__jsl_ind_r9:
+      lda.b [tcc__r9]
+      sta.b tcc__r10
+      ldy.w #2
+      lda.b [tcc__r9],y
+      sta.b tcc__r10h
+      ;jmp.w tcc__jsl_r10
+      sep #$20
+      lda.b tcc__r10 + 2
+      pha
+      rep #$20
+      lda.b tcc__r10
+      dec a
+      pha
+      rtl
+.ENDS
+

package/src/platforms/snes/lib/pvsneslib/source/lzsss.asm

@@ -0,0 +1,256 @@
+;---------------------------------------------------------------------------------
+;
+;	Copyright (C) 2014-2022
+;		Alekmaul
+;
+;	This software is provided 'as-is', without any express or implied
+;	warranty.  In no event will the authors be held liable for any
+;	damages arising from the use of this software.
+;
+;	Permission is granted to anyone to use this software for any
+;	purpose, including commercial applications, and to alter it and
+;	redistribute it freely, subject to the following restrictions:
+;
+;	1.	The origin of this software must not be misrepresented; you
+;		must not claim that you wrote the original software. If you use
+;		this software in a product, an acknowledgment in the product
+;		documentation would be appreciated but is not required.
+;	2.	Altered source versions must be plainly marked as such, and
+;		must not be misrepresented as being the original software.
+;	3.	This notice may not be removed or altered from any source
+;		distribution.
+;
+; based on decompression routines for SNES by mukunda, 2009-2010
+;---------------------------------------------------------------------------------
+
+.EQU REG_VMAIN			$2115				                 ; Video Port Control			1B/W
+.EQU REG_VMADDL			$2116								 ;
+.EQU REG_VMDATAL			$2118							 ;
+.EQU REG_VMDATAH			$2119							 ;
+.EQU REG_VMDATALREAD			$2139	; VRAM Data Read Low			1B/R
+.EQU REG_VMDATAHREAD			$213A	; VRAM Data Read High			1B/R
+
+.BASE $00
+.RAMSECTION  ".reg_lzss7e" BANK $7E SLOT RAMSLOT_0
+
+m0					DW
+m4					DW
+m5					DW
+m6					DW
+
+.ENDS
+
+.BASE BASE_0
+.SECTION ".lz77_text" superfree
+
+.accu 16
+.index 16
+.16bit
+
+;*************************************************************************;
+; A = source bank
+; X = source address
+; Y = vram address
+;*************************************************************************;
+;count = m4
+;cflags = m5
+;bit_counter = m6
+
+;---------------------------------------------------------------------------
+; void LzssDecodeVram(u8 * source, u16 address);
+; 10-13 14-15
+LzssDecodeVram:
+	php
+	phb
+	phx
+	phy
+	sei
+
+	sep	#$20
+	lda	#$7e
+	pha
+	plb
+
+	rep #$20
+	lda 10,s
+	sta tcc__r0                          				  	  ; tcc_r0 = source address
+	sep #$20
+	lda 12,s
+	sta tcc__r0h
+
+	rep #$20
+	lda 14,s
+	asl a													  ; because adr is x2
+	sta  m0                                            		  ; m0 = vram target
+
+	sep #$20
+	lda	#$00                        						  ; setup VRAM access (increment on readlow)
+	sta.l REG_VMAIN
+
+	ldy	#0                                         		      ; y = 0 (source index)
+	lda	[tcc__r0]                         				      ; test compression type
+	and	#$F0
+	cmp	#$10                                     		      ; 1x = LZ77
+	beq	@LZ77source
+
+@ddv_exit:
+	ply
+	plx
+	plb
+	plp
+
+	rtl
+
+@LZ77source:												  ;=========================================================================
+	iny                                                       ; x = byte 1,2 (data length)
+	rep	#$20
+	lda	[tcc__r0], y
+	tax
+	sep	#$20
+	iny
+	iny
+	iny
+
+@LZ77_DecompressLoop:
+	lda	[tcc__r0], y                                     	 ; m5 = cflags
+	iny
+	sta	m5
+	lda	#8                                         			 ; m6 = bit counter
+	sta	m6
+
+@next_bit:
+	asl	m5                                        			 ; test bit
+	bcs @lz_byte
+
+@raw_byte:
+	rep #$20                                                 ; setup vram address (to target)
+	lda m0
+	inc m0
+	lsr
+	sta.l REG_VMADDL
+	sep #$20
+	lda	[tcc__r0], y										 ; copy one byte
+	iny
+	bcs	+                                                    ; write A to vram (carry = H/L)
+
+	sta.l	REG_VMDATAL
+	bra ++                                         ;
++:
+	sta.l	REG_VMDATAH                              ;
+
+++:                                                                             ;
+	dex
+	beq        @ddv_exit						; @next_block
+	dec        m6
+	bne        @next_bit
+	bra         @LZ77_DecompressLoop
+
+@lz_byte:
+	rep #$20                                     ; read 2 bytes
+	lda	[tcc__r0], y                       ;
+	iny
+	iny
+
+	phy                                                       ; preserve y
+	sep	#$20                                     ; y = target - disp - 1
+	pha                                                       ;
+	and	#$0F                                     ;
+	xba                                                        ;
+	rep #$20                                     ;
+	sec                                                        ;
+	sbc	m0                                         ;
+	eor	#$FFFF                                              ;
+	tay                                                         ;-----------------------------
+	sep	#$20                                     ; a = count (top 4 bits + 3)
+	pla                                                         ;
+	lsr                                                          ;
+	lsr                                                          ;
+	lsr                                                          ;
+	lsr                                                          ;
+	clc                                                          ;
+	adc	#3                                          ;-----------------------------
+
+	sta	m4                                         ; m4 = count (16bit)
+	stz	m4+1                                    ;-----------------------------
+	rep	#$20                                     ; m4 = count > x ? x : count
+	cpx	m4                                         ;
+	bcs +                                           ;
+	stx	m4                                         ;
+	sec                                                        ;-----------------------------
+
++:
+	txa                                                         ; push "x - count"
+	sbc	m4                                         ;
+	pha                                                       ;
+	sep	#$20                                     ;
+
+@copyloop:
+	rep	#$21                                     ; copy ONE byte..........
+	tya                                                         ;
+	iny                                                         ;
+	lsr                                                          ;
+	sta.l	REG_VMADDL                  ;
+	lda	m0                                         ;
+	inc	m0                                         ;
+	bcs	@copy_readH                  ;
+
+@copy_readL:                                                 ;
+	lsr                                                          ;
+	tax                                                         ;
+	sep	#$20                                     ;
+	phb
+	lda.b #0
+	pha
+	plb
+	lda.l	REG_VMDATALREAD                     ;
+	stx	REG_VMADDL                  ;
+	plb
+	bcs	@copy_writeH                 ;
+
+@copy_writeL:
+	sta.l	REG_VMDATAL
+	dec	m4
+	bne	@copyloop
+	bra	@copyexit
+
+@copy_readH:
+	lsr
+	tax
+	sep #$20
+	phb
+	lda.b #0
+	pha
+	plb
+	lda.l REG_VMDATAHREAD
+	stx REG_VMADDL
+	plb
+	bcc @copy_writeL
+
+@copy_writeH:
+	sta.l	REG_VMDATAH
+	dec	m4
+	bne	@copyloop
+
+@copyexit:
+	plx
+	ply
+	cpx	#0
+
+@next_block:
+	beq	@ddv_exit2                       					  ; exit on end of data
+	dec	m6
+	beq	+
+	jmp	@next_bit
+
++:
+	jmp	@LZ77_DecompressLoop
+
+@ddv_exit2:
+	ply
+	plx
+	plb
+	plp
+
+	rtl
+
+.ENDS