udb 0.1.14 → 0.1.16

data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml

@@ -0,0 +1,67 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabd.vv
+long_name: Vector Single-Width Signed Integer Absolute Difference
+description: |
+  Computes the element-wise absolute difference of two signed integer SEW-bit
+  source operands vs1 and vs2 and writes the result to vd according to mask vm.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010001-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(V[vs1][end_bit_pos:start_bit_pos])) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - V[vs1][end_bit_pos:start_bit_pos];
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs1][end_bit_pos:start_bit_pos] - V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml

@@ -0,0 +1,67 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabdu.vv
+long_name: Vector Single-Width Unsigned Integer Absolute Difference
+description: |
+  Computes the element-wise absolute difference of two unsigned integer SEW-bit
+  source operands vs1 and vs2 and writes the result to vd according to mask vm.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010011-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][end_bit_pos:start_bit_pos] >= V[vs1][end_bit_pos:start_bit_pos]) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - V[vs1][end_bit_pos:start_bit_pos];
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs1][end_bit_pos:start_bit_pos] - V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml

@@ -0,0 +1,61 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabs.v
+long_name: Vector Single-Width Signed Integer Absolute
+description: |
+  An absolute value operation is performed on each element of vs2, storing the
+  result in vector register vd according to mask vm.
+
+  vabs.v supports SEW of 8, 16, and 32 when Zve32x is implemented.
+  When Zve64x is implemented, vabs.v also supports SEW of 64.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------10000010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][end_bit_pos:end_bit_pos] == 1'b1) {
+        V[vd][end_bit_pos:start_bit_pos] = -$signed(V[vs2][end_bit_pos:start_bit_pos]);
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml

@@ -0,0 +1,72 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabda.vv
+long_name: Vector Widening Signed Integer Absolute Difference and Accumulate, Overwrite Addend
+description: |
+  Computes the element-wise absolute difference of two signed integer SEW-bit
+  source operands vs1 and vs2, and accumulates the results into the elements of
+  a 2*SEW-bit operand vd.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010101-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][src_end:src_start]) >= $signed(V[vs1][src_end:src_start])) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - V[vs1][src_end:src_start]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs1][src_end:src_start] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml

@@ -0,0 +1,72 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabdau.vv
+long_name: Vector Widening Unsigned Integer Absolute Difference and Accumulate, Overwrite Addend
+description: |
+  Computes the element-wise absolute difference of two unsigned integer SEW-bit
+  source operands vs1 and vs2, and accumulates the results into the elements of
+  a 2*SEW-bit operand vd.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010110-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][src_end:src_start] >= V[vs1][src_end:src_start]) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - V[vs1][src_end:src_start]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs1][src_end:src_start] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vv.yaml

@@ -11,7 +11,7 @@ description: |
   Performs a bitwise AND operation between vector register vs2 and the bitwise NOT of vector register vs1, storing results in vector register vd according to mask vm.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 000001-----------000-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vx.yaml

@@ -11,7 +11,7 @@ description: |
   Performs a bitwise AND operation between vector register vs2 and the bitwise NOT of scalar register xs1, storing results in vector register vd according to mask vm.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, xs1, vm
 encoding:
   match: 000001-----------100-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vbrev8.v.yaml

@@ -11,7 +11,7 @@ description: |
   Reverses the byte order within each element of vector register vs2, storing results in vector register vd according to mask vm. Similar to vrev8.v but with different encoding.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vm
 encoding:
   match: 010010------01000010-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrev8.v.yaml

@@ -11,7 +11,7 @@ description: |
   Reverses the byte order within each element of vector register vs2, storing results in vector register vd according to mask vm. This is equivalent to a byte-level reversal of each element.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vm
 encoding:
   match: 010010------01001010-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vv.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 left by the amount specified in vector register vs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 010101-----------000-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vx.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 left by the amount specified in scalar register xs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, xs1, vm
 encoding:
   match: 010101-----------100-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vi.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 right by the immediate shift amount, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, imm, vm
 encoding:
   match: 01010------------011-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vv.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 right by the amount specified in vector register vs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 010100-----------000-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vx.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 right by the amount specified in scalar register xs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, xs1, vm
 encoding:
   match: 010100-----------100-----1010111

data/.data/spec/std/isa/isa/fp.idl

@@ -405,6 +405,9 @@ function f32_muladd {
     Translated from Berkeley Softfloat softfloat_mulAddF32.
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b) || is_sp_signaling_nan?(c)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1>  signA    = signF32UI(a);
     Bits<16>  expA     = expF32UI(a);
     Bits<32> sigA     = fracF32UI(a);
@@ -584,8 +587,11 @@ function f32_sqrt {
     Translated from Berkeley Softfloat f32_sqrt.
   }
   body {
+    if (is_sp_signaling_nan?(a)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1> signA = signF32UI(a);
-    Bits<8> expA  = expF32UI(a);
+    Bits<16> expA  = expF32UI(a);
     Bits<32> fracA = fracF32UI(a);
 
     if (expA == 8'hFF) {
@@ -606,7 +612,8 @@ function f32_sqrt {
       fracA = norm.sig;
     }
 
-    Bits<16> expZ = ((expA - 16'h007F) >> 1) + 16'h007E;
+    Bits<16> adjExp = expA - 16'h007F;
+    Bits<16> expZ = ((adjExp >> 1) ^ (adjExp & 16'h8000)) + 16'h007E;
     Bits<1> oddExpA = expA[0];
     Bits<32> sigA32 = (fracA | 32'h00800000) << 8;
     Bits<32> sigZ = (sigA32 `* softfloat_approxRecipSqrt32_1(oddExpA, sigA32)) >> 32;
@@ -653,19 +660,22 @@ function softfloat_approxRecip32_1 {
   arguments
     Bits<32> a
   description {
-    Returns a 32-bit approximation of 1/a, where a is in [1, 2).
-    Translated from Berkeley Softfloat softfloat_approxRecip32_1.
+    Returns floor(0x7FFFFFFFFFFFFFFF / a), matching the platform-specific
+    Berkeley SoftFloat macro on 64-bit hosts. Computed via binary long division.
   }
   body {
-    Bits<32> index = (a >> 27) & 0xF;
-    Bits<16> eps = a >> 11;
-    Bits<32> r0 = softfloat_approxRecip_1k0s[index]
-                  - ((softfloat_approxRecip_1k1s[index] `* eps) >> 20);
-    Bits<32> sigma0 = ~((r0 `* a) >> 7);
-    Bits<32> r = (r0 << 16) + ((r0 `* sigma0) >> 24);
-    Bits<32> sqrSigma0 = (sigma0 `* sigma0) >> 32;
-    r = r + ((r `* sqrSigma0) >> 48);
-    return r;
+    Bits<64> a64 = {32'h0, a};
+    Bits<64> a_top = a64 << 31;
+    Bits<64> rem = 64'h7FFFFFFFFFFFFFFF;
+    Bits<32> q = 0;
+    for (U32 i = 0; i < 32; i++) {
+      Bits<64> d = a_top >> i;
+      if (rem >= d) {
+        q = q | (32'h1 << (31 - i));
+        rem = rem - d;
+      }
+    }
+    return q;
   }
 }
 
@@ -710,6 +720,9 @@ function f32_div {
     Translated from Berkeley Softfloat f32_div.
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1> signA = signF32UI(a);
     Bits<16> expA  = expF32UI(a);
     Bits<32> sigA = fracF32UI(a);
@@ -771,7 +784,7 @@ function f32_div {
     Bits<32> sigZ = (sigA `* recip32) >> 32;
     sigZ = sigZ + 2;
 
-    if ((sigZ & 0x3F) < 2) {
+    if ((sigZ & 7) <= 2) {
       sigZ = sigZ & ~32'h3;
       Bits<64> rem = (sigA `<< 31) - (sigZ `* sigB);
       if ((rem & 64'h8000000000000000) != 0) {
@@ -798,6 +811,9 @@ function f32_mul {
     Translated from Berkeley Softfloat f32_mul.
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1> signA = signF32UI(a);
     Bits<16> expA  = expF32UI(a);
     Bits<23> fracA = fracF32UI(a);
@@ -1326,6 +1342,9 @@ function softfloat_addMagsF32 {
     Returns sum of the magnitudes of 2 floating point numbers
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
 
     # extract exponents and significands of a and b
     Bits<16> expA = expF32UI(a);
@@ -1433,6 +1452,9 @@ function softfloat_subMagsF32 {
     Returns difference of the magnitudes of 2 floating point numbers
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
 
     # extract exponents and significands of a and b
     Bits<16> expA = expF32UI(a);
@@ -1886,7 +1908,7 @@ function round_f32_to_integral {
 }
 
 struct ExpAndSig {
-  Bits<8> exp;
+  Bits<16> exp;
   Bits<32> sig;
 }
 
@@ -1897,11 +1919,13 @@ function softfloat_normSubnormalF32Sig {
   description {
     Normalize a subnormal F32 significand.
     Returns (exp, sig32) where exp is the adjusted exponent (two's complement
-    in Bits<8>) and sig32 is the normalized significand with implicit leading 1
-    at bit 23.
+    in Bits<16>) and sig32 is the normalized significand with implicit leading 1
+    at bit 23. The exponent is widened to Bits<16> (rather than the natural
+    Bits<8>) so that callers can add two adjusted exponents together (e.g.
+    expA + expB - bias) without overflow.
   }
   body {
-    Bits<8> shiftDist = count_leading_zeros(32, sig) - 8;
+    Bits<16> shiftDist = count_leading_zeros(32, sig) - 8;
     ExpAndSig ret;
     ret.exp = 1 - shiftDist;
     ret.sig = sig << shiftDist;

data/.data/spec/std/isa/isa/globals.isa

@@ -3144,7 +3144,7 @@ function mstatus_sd_reset_value
       fs_value = (!implemented?(ExtensionName::F)) ? 0 : MSTATUS_FS_LEGAL_VALUES[0];
     }
     if ((!implemented?(ExtensionName::V)) || ($array_size(MSTATUS_VS_LEGAL_VALUES) == 1)) {
-      fs_value = (!implemented?(ExtensionName::V)) ? 0 : MSTATUS_VS_LEGAL_VALUES[0];
+      vs_value = (!implemented?(ExtensionName::V)) ? 0 : MSTATUS_VS_LEGAL_VALUES[0];
     }
 
     return ((fs_value == 3) || (vs_value == 3)) ? 1 : 0;

data/.data/spec/std/isa/isa/util.idl

@@ -73,9 +73,9 @@ function highest_set_bit {
     or -1 if value is zero.
   }
   body {
-    for (Bits<8> i=xlen()-1; i >= 0; i--) {
-      if (value[i] == 1) {
-        return i;
+    for (Bits<8> i=xlen(); i > 0; i--) {
+      if (value[i-1] == 1) {
+        return i-1;
       }
     }
 

data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml

@@ -6,14 +6,78 @@
 $schema: param_schema.json#
 kind: parameter
 name: CACHE_BLOCK_SIZE
-description: "The observable size of a cache block, in bytes
-
-  "
-long_name: TODO
+description: The observable size of a cache block, in bytes. A cache block is a
+  naturally aligned power-of-two (NAPOT) range of memory.
+long_name: cache block size
 schema:
   type: integer
-  minimum: 1
-  maximum: 18446744073709551615
+  enum:
+    [
+      0x1,
+      0x2,
+      0x4,
+      0x8,
+      0x10,
+      0x20,
+      0x40,
+      0x80,
+      0x100,
+      0x200,
+      0x400,
+      0x800,
+      0x1000,
+      0x2000,
+      0x4000,
+      0x8000,
+      0x10000,
+      0x20000,
+      0x40000,
+      0x80000,
+      0x100000,
+      0x200000,
+      0x400000,
+      0x800000,
+      0x1000000,
+      0x2000000,
+      0x4000000,
+      0x8000000,
+      0x10000000,
+      0x20000000,
+      0x40000000,
+      0x80000000,
+      0x100000000,
+      0x200000000,
+      0x400000000,
+      0x800000000,
+      0x1000000000,
+      0x2000000000,
+      0x4000000000,
+      0x8000000000,
+      0x10000000000,
+      0x20000000000,
+      0x40000000000,
+      0x80000000000,
+      0x100000000000,
+      0x200000000000,
+      0x400000000000,
+      0x800000000000,
+      0x1000000000000,
+      0x2000000000000,
+      0x4000000000000,
+      0x8000000000000,
+      0x10000000000000,
+      0x20000000000000,
+      0x40000000000000,
+      0x80000000000000,
+      0x100000000000000,
+      0x200000000000000,
+      0x400000000000000,
+      0x800000000000000,
+      0x1000000000000000,
+      0x2000000000000000,
+      0x4000000000000000,
+      0x8000000000000000,
+    ]
 definedBy:
   extension:
     anyOf: