udb 0.1.14 → 0.1.16

data/.data/spec/std/isa/inst/C/c.or.yaml

@@ -27,6 +27,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
   XReg t0 = X[creg2reg(xd)];
   XReg t1 = X[creg2reg(xs2)];

data/.data/spec/std/isa/inst/C/c.slli.yaml

@@ -36,6 +36,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
   # shamt is between 0-63
   X[xd] = X[xd] << shamt;

data/.data/spec/std/isa/inst/C/c.srai.yaml

@@ -37,6 +37,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
   # shamt is between 0-63
   X[creg2reg(xd)] = X[creg2reg(xd)] >>> shamt;

data/.data/spec/std/isa/inst/C/c.srli.yaml

@@ -37,6 +37,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
   # shamt is between 0-63
   X[creg2reg(xd)] = X[creg2reg(xd)] >> shamt;

data/.data/spec/std/isa/inst/C/c.sub.yaml

@@ -27,6 +27,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
   XReg t0 = X[creg2reg(xd)];
   XReg t1 = X[creg2reg(xs2)];

data/.data/spec/std/isa/inst/C/c.subw.yaml

@@ -29,6 +29,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
   Bits<32> t0 = X[creg2reg(xd)][31:0];
   Bits<32> t1 = X[creg2reg(xs2)][31:0];

data/.data/spec/std/isa/inst/C/c.xor.yaml

@@ -27,6 +27,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
   XReg t0 = X[creg2reg(xd)];
   XReg t1 = X[creg2reg(xs2)];

data/.data/spec/std/isa/inst/D/fld.yaml

@@ -21,6 +21,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fd

data/.data/spec/std/isa/inst/D/fsd.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: fs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/F/fadd.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml

@@ -29,7 +29,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml

@@ -37,7 +37,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml

@@ -56,7 +56,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml

@@ -55,7 +55,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fdiv.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/feq.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fle.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/flt.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/flw.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fd
@@ -29,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fmadd.s.yaml

@@ -31,7 +31,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fmax.s.yaml

@@ -37,7 +37,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fmin.s.yaml

@@ -37,7 +37,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fmsub.s.yaml

@@ -31,7 +31,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fmul.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fmv.w.x.yaml

@@ -27,7 +27,10 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
+pseudoinstructions:
+  - when: "true"
+    to: fmv.s.x fd, xs1
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fmv.x.w.yaml

@@ -28,7 +28,10 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
+pseudoinstructions:
+  - when: "true"
+    to: fmv.x.s xd, fs1
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fnmadd.s.yaml

@@ -32,7 +32,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fnmsub.s.yaml

@@ -32,7 +32,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fsgnj.s.yaml

@@ -31,7 +31,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
     to: fmv.s fd, fs1

data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
     to: fneg.s fd, fs1

data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml

@@ -30,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
     to: fabs.s fd, fs1

data/.data/spec/std/isa/inst/F/fsqrt.s.yaml

@@ -27,7 +27,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fsub.s.yaml

@@ -29,7 +29,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/F/fsw.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: fs2
       location: 24-20
     - name: xs1
@@ -29,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -51,7 +51,7 @@ operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
   if (xlen() == 32) {
-    if (implemented?(ExtensionName::Zclsd)) {
+    if (implemented?(ExtensionName::Zilsd)) {
       data = {X[xs2 + 1], X[xs2]};
     } else {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/inst/M/mul.yaml

@@ -22,9 +22,7 @@ description: |
 
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------000-----0110011

data/.data/spec/std/isa/inst/M/mulh.yaml

@@ -21,9 +21,7 @@ description: |
   Microarchitectures may look for that sequence and fuse the operations.
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------001-----0110011

data/.data/spec/std/isa/inst/M/mulhsu.yaml

@@ -21,9 +21,7 @@ description: |
   Microarchitectures may look for that sequence and fuse the operations.
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------010-----0110011

data/.data/spec/std/isa/inst/M/mulhu.yaml

@@ -21,9 +21,7 @@ description: |
   Microarchitectures may look for that sequence and fuse the operations.
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------011-----0110011

data/.data/spec/std/isa/inst/M/mulw.yaml

@@ -22,9 +22,7 @@ definedBy:
   allOf:
     - xlen: 64
     - extension:
-        anyOf:
-          - name: M
-          - name: Zmmul
+        name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------000-----0111011

data/.data/spec/std/isa/inst/Q/fadd.q.yaml

@@ -11,8 +11,8 @@ definedBy:
   extension:
     name: Q
 description: |
-  `fadd.q` is analogous to `fadd.d` and performs double-precision floating-point addition between
-  `qs1` and `qs2` and writes the final result to `qd`.
+  `fadd.q` is analogous to `fadd.d` and performs quad-precision floating-point addition between
+  `fs1` and `fs2` and writes the final result to `fd`.
 assembly: fd, fs1, fs2, rm
 encoding:
   match: 0000011------------------1010011

data/.data/spec/std/isa/inst/Q/fclass.q.yaml

@@ -8,13 +8,13 @@ kind: instruction
 name: fclass.q
 long_name: Floating-Point Classify Quad-Precision
 description: |
-  The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer
-  register `rd` a 10-bit mask that indicates the class of the floating-point number.
+  The `fclass.q` instruction examines the value in floating-point register `fs1` and writes to integer
+  register `xd` a 10-bit mask that indicates the class of the floating-point number.
 
-  The format of the mask is described in table given below. The corresponding bit in `rd`
-  will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
+  The format of the mask is described in table given below. The corresponding bit in `xd`
+  will be set if the property is true and clear otherwise. All other bits in `xd` are cleared.
 
-  Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point
+  Note that exactly one bit in `xd` will be set. `fclass.q` does not set the floating-point
   exception flags.
 
   .Format of result of `fclass` instruction.

data/.data/spec/std/isa/inst/Q/flq.yaml

@@ -24,6 +24,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fd

data/.data/spec/std/isa/inst/Q/fsq.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: fs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/V/vmv.v.i.yaml

@@ -24,6 +24,7 @@ encoding:
   variables:
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/Zbb/ctzw.yaml

@@ -36,4 +36,9 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[xd] = lowest_set_bit(X[xs1][31:0]);
+  # lowest_set_bit() reports xlen() (64 here) for a zero input, but ctzw must report 32
+  if (X[xs1][31:0] == 0) {
+    X[xd] = 32;
+  } else {
+    X[xd] = lowest_set_bit(X[xs1][31:0]);
+  }

data/.data/spec/std/isa/inst/Zcb/c.mul.yaml

@@ -28,6 +28,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
 
   if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {

data/.data/spec/std/isa/inst/Zcb/c.not.yaml

@@ -25,6 +25,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
 
   if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {

data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml

@@ -14,9 +14,7 @@ description: |
 
 definedBy:
   extension:
-    allOf:
-      - name: Zcb
-      - name: Zbb
+    name: Zcb
 assembly: xd
 encoding:
   match: 100111---1100001
@@ -28,12 +26,9 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |2
 
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }

data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml

@@ -17,7 +17,7 @@ definedBy:
     - extension:
         allOf:
           - name: Zcb
-          - name: Zbb
+          - name: Zba
 assembly: xd
 encoding:
   match: 100111---1110001

data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml

@@ -28,4 +28,6 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+hints:
+  - { $ref: inst/Zicfiss/c.sspush.yaml# }
 operation(): "" #do nothing

data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml

@@ -28,4 +28,6 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+hints:
+  - { $ref: inst/Zicfiss/c.sspopchk.yaml# }
 operation(): "" #do nothing

data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout

@@ -42,4 +42,11 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+<% if n == 1 -%>
+hints:
+  - { $ref: inst/Zicfiss/c.sspush.yaml# }
+<% elsif n == 5 -%>
+hints:
+  - { $ref: inst/Zicfiss/c.sspopchk.yaml# }
+<% end -%>
 operation(): "" #do nothing

data/.data/spec/std/isa/inst/{Q → Zfa}/fleq.q.yaml

@@ -13,7 +13,6 @@ description: |
 
   `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid
   operation exception flag to be set.
-  This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/{F → Zfa}/fleq.s.yaml

@@ -28,7 +28,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/{Q → Zfa}/fli.q.yaml

@@ -9,7 +9,7 @@ name: fli.q
 long_name: Floating-Point Load Immediate Quad-Precision
 description: |
   The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `xs1`
-  field, into floating-point register `rd`.
+  field, into floating-point register `fd`.
   `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q.
 definedBy:
   extension:

data/.data/spec/std/isa/inst/Zfa/fli.s.yaml

@@ -25,5 +25,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |