udb 0.1.14 → 0.1.16

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (343) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +6 -6
  3. data/.data/cfgs/mc100-32-full-example.yaml +3 -2
  4. data/.data/cfgs/profile/RVA20S64.yaml +2 -0
  5. data/.data/cfgs/profile/RVA20U64.yaml +2 -0
  6. data/.data/cfgs/profile/RVA22S64.yaml +2 -0
  7. data/.data/cfgs/profile/RVA22U64.yaml +2 -0
  8. data/.data/cfgs/profile/RVA23S64.yaml +2 -0
  9. data/.data/cfgs/profile/RVA23U64.yaml +2 -0
  10. data/.data/cfgs/profile/RVB23S64.yaml +2 -0
  11. data/.data/cfgs/profile/RVB23U64.yaml +2 -0
  12. data/.data/cfgs/qc_iu.yaml +3 -2
  13. data/.data/cfgs/rv32-riscv-tests.yaml +5 -4
  14. data/.data/cfgs/rv32-vector.yaml +5 -4
  15. data/.data/cfgs/rv64-riscv-tests.yaml +5 -4
  16. data/.data/cfgs/rv64-vector.yaml +5 -4
  17. data/.data/spec/schemas/README.adoc +3 -0
  18. data/.data/spec/schemas/schema_defs.json +3 -3
  19. data/.data/spec/std/isa/csr/H/hcounteren.layout +3 -3
  20. data/.data/spec/std/isa/csr/H/hcounteren.yaml +31 -31
  21. data/.data/spec/std/isa/csr/H/henvcfg.yaml +1 -1
  22. data/.data/spec/std/isa/csr/H/htimedeltah.yaml +1 -1
  23. data/.data/spec/std/isa/csr/H/htinst.yaml +3 -3
  24. data/.data/spec/std/isa/csr/H/htval.yaml +3 -3
  25. data/.data/spec/std/isa/csr/H/mtinst.yaml +1 -1
  26. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +1 -1
  27. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +1 -1
  28. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +1 -1
  29. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +1 -1
  30. data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml +1 -1
  31. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +1 -1
  32. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +29 -29
  33. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -4
  34. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +1 -1
  35. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -4
  36. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +1 -1
  37. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -4
  38. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +1 -1
  39. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -4
  40. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +1 -1
  41. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -4
  42. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +1 -1
  43. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -4
  44. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +1 -1
  45. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -4
  46. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +1 -1
  47. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -4
  48. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +1 -1
  49. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -4
  50. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +1 -1
  51. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -4
  52. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +1 -1
  53. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -4
  54. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +1 -1
  55. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -4
  56. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +1 -1
  57. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -4
  58. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +1 -1
  59. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -4
  60. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +1 -1
  61. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -4
  62. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +1 -1
  63. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -4
  64. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +1 -1
  65. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -4
  66. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +1 -1
  67. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -4
  68. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +1 -1
  69. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -4
  70. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +1 -1
  71. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -4
  72. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +1 -1
  73. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -4
  74. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -4
  75. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +1 -1
  76. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -4
  77. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +1 -1
  78. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +1 -1
  79. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -4
  80. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +1 -1
  81. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -4
  82. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +1 -1
  83. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -4
  84. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +1 -1
  85. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -4
  86. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +1 -1
  87. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -4
  88. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +1 -1
  89. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -4
  90. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +1 -1
  91. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -4
  92. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +1 -1
  93. data/.data/spec/std/isa/csr/hstateen0h.yaml +1 -1
  94. data/.data/spec/std/isa/csr/hstateen1h.yaml +1 -1
  95. data/.data/spec/std/isa/csr/hstateen2h.yaml +1 -1
  96. data/.data/spec/std/isa/csr/hstateen3h.yaml +1 -1
  97. data/.data/spec/std/isa/csr/hstatus.yaml +1 -1
  98. data/.data/spec/std/isa/csr/instreth.yaml +1 -3
  99. data/.data/spec/std/isa/csr/mcycle.yaml +6 -6
  100. data/.data/spec/std/isa/csr/minstret.yaml +3 -3
  101. data/.data/spec/std/isa/csr/minstreth.yaml +2 -2
  102. data/.data/spec/std/isa/csr/mstatus.yaml +14 -20
  103. data/.data/spec/std/isa/csr/mstatush.yaml +1 -1
  104. data/.data/spec/std/isa/csr/mtvec.yaml +16 -57
  105. data/.data/spec/std/isa/csr/senvcfg.yaml +1 -1
  106. data/.data/spec/std/isa/csr/sepc.yaml +4 -3
  107. data/.data/spec/std/isa/csr/sie.yaml +30 -4
  108. data/.data/spec/std/isa/csr/sip.yaml +17 -3
  109. data/.data/spec/std/isa/csr/sscratch.yaml +3 -2
  110. data/.data/spec/std/isa/csr/stval.yaml +3 -2
  111. data/.data/spec/std/isa/csr/stvec.yaml +14 -14
  112. data/.data/spec/std/isa/csr/time.yaml +1 -1
  113. data/.data/spec/std/isa/csr/timeh.yaml +1 -1
  114. data/.data/spec/std/isa/csr/vsepc.yaml +6 -5
  115. data/.data/spec/std/isa/csr/vstval.yaml +1 -1
  116. data/.data/spec/std/isa/csr/vstvec.yaml +17 -17
  117. data/.data/spec/std/isa/ext/M.yaml +4 -0
  118. data/.data/spec/std/isa/ext/Q.yaml +1 -1
  119. data/.data/spec/std/isa/ext/Shgatpa.yaml +1 -0
  120. data/.data/spec/std/isa/ext/Shlcofideleg.yaml +24 -0
  121. data/.data/spec/std/isa/ext/Shvstvecd.yaml +2 -2
  122. data/.data/spec/std/isa/ext/Sspm.yaml +5 -0
  123. data/.data/spec/std/isa/ext/Sstvecd.yaml +2 -2
  124. data/.data/spec/std/isa/ext/Sstvecv.yaml +2 -2
  125. data/.data/spec/std/isa/ext/Supm.yaml +17 -0
  126. data/.data/spec/std/isa/ext/Zcb.yaml +3 -0
  127. data/.data/spec/std/isa/ext/Zfbfmin.yaml +3 -5
  128. data/.data/spec/std/isa/ext/Zibi.yaml +29 -0
  129. data/.data/spec/std/isa/ext/Ziccid.yaml +29 -0
  130. data/.data/spec/std/isa/ext/Zicfilp.yaml +5 -1
  131. data/.data/spec/std/isa/ext/Zicfiss.yaml +20 -1
  132. data/.data/spec/std/isa/ext/Zihpm.yaml +3 -0
  133. data/.data/spec/std/isa/ext/Zilx.yaml +58 -0
  134. data/.data/spec/std/isa/ext/Zkt.yaml +33 -1
  135. data/.data/spec/std/isa/ext/Zvabd.yaml +21 -0
  136. data/.data/spec/std/isa/ext/Zvbc.yaml +3 -0
  137. data/.data/spec/std/isa/ext/Zvkb.yaml +3 -0
  138. data/.data/spec/std/isa/ext/Zvkg.yaml +3 -0
  139. data/.data/spec/std/isa/ext/Zvkned.yaml +3 -0
  140. data/.data/spec/std/isa/ext/Zvknha.yaml +3 -0
  141. data/.data/spec/std/isa/ext/Zvknhb.yaml +4 -2
  142. data/.data/spec/std/isa/ext/Zvksed.yaml +3 -0
  143. data/.data/spec/std/isa/ext/Zvksh.yaml +3 -0
  144. data/.data/spec/std/isa/ext/Zvkt.yaml +3 -0
  145. data/.data/spec/std/isa/inst/B/roriw.yaml +1 -1
  146. data/.data/spec/std/isa/inst/B/rorw.yaml +1 -1
  147. data/.data/spec/std/isa/inst/C/c.add.yaml +1 -0
  148. data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
  149. data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
  150. data/.data/spec/std/isa/inst/C/c.addw.yaml +1 -0
  151. data/.data/spec/std/isa/inst/C/c.and.yaml +1 -0
  152. data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
  153. data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
  154. data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -0
  155. data/.data/spec/std/isa/inst/C/c.nop.yaml +13 -2
  156. data/.data/spec/std/isa/inst/C/c.or.yaml +1 -0
  157. data/.data/spec/std/isa/inst/C/c.slli.yaml +1 -0
  158. data/.data/spec/std/isa/inst/C/c.srai.yaml +1 -0
  159. data/.data/spec/std/isa/inst/C/c.srli.yaml +1 -0
  160. data/.data/spec/std/isa/inst/C/c.sub.yaml +1 -0
  161. data/.data/spec/std/isa/inst/C/c.subw.yaml +1 -0
  162. data/.data/spec/std/isa/inst/C/c.xor.yaml +1 -0
  163. data/.data/spec/std/isa/inst/D/fld.yaml +1 -0
  164. data/.data/spec/std/isa/inst/D/fsd.yaml +1 -0
  165. data/.data/spec/std/isa/inst/F/fadd.s.yaml +1 -1
  166. data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
  167. data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
  168. data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
  169. data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
  170. data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
  171. data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
  172. data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
  173. data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
  174. data/.data/spec/std/isa/inst/F/feq.s.yaml +1 -1
  175. data/.data/spec/std/isa/inst/F/fle.s.yaml +1 -1
  176. data/.data/spec/std/isa/inst/F/flt.s.yaml +1 -1
  177. data/.data/spec/std/isa/inst/F/flw.yaml +2 -1
  178. data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
  179. data/.data/spec/std/isa/inst/F/fmax.s.yaml +1 -1
  180. data/.data/spec/std/isa/inst/F/fmin.s.yaml +1 -1
  181. data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
  182. data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
  183. data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +4 -1
  184. data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +4 -1
  185. data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +1 -1
  186. data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
  187. data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +1 -1
  188. data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +1 -1
  189. data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +1 -1
  190. data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
  191. data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
  192. data/.data/spec/std/isa/inst/F/fsw.yaml +2 -1
  193. data/.data/spec/std/isa/inst/I/sd.yaml +1 -1
  194. data/.data/spec/std/isa/inst/M/mul.yaml +1 -3
  195. data/.data/spec/std/isa/inst/M/mulh.yaml +1 -3
  196. data/.data/spec/std/isa/inst/M/mulhsu.yaml +1 -3
  197. data/.data/spec/std/isa/inst/M/mulhu.yaml +1 -3
  198. data/.data/spec/std/isa/inst/M/mulw.yaml +1 -3
  199. data/.data/spec/std/isa/inst/Q/fadd.q.yaml +2 -2
  200. data/.data/spec/std/isa/inst/Q/fclass.q.yaml +5 -5
  201. data/.data/spec/std/isa/inst/Q/flq.yaml +1 -0
  202. data/.data/spec/std/isa/inst/Q/fsq.yaml +1 -0
  203. data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +1 -0
  204. data/.data/spec/std/isa/inst/Zbb/ctzw.yaml +6 -1
  205. data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +1 -0
  206. data/.data/spec/std/isa/inst/Zcb/c.not.yaml +1 -0
  207. data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml +2 -7
  208. data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +1 -1
  209. data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml +2 -0
  210. data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml +2 -0
  211. data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout +7 -0
  212. data/.data/spec/std/isa/inst/{Q → Zfa}/fleq.q.yaml +0 -1
  213. data/.data/spec/std/isa/inst/{F → Zfa}/fleq.s.yaml +1 -1
  214. data/.data/spec/std/isa/inst/{Q → Zfa}/fli.q.yaml +1 -1
  215. data/.data/spec/std/isa/inst/Zfa/fli.s.yaml +1 -1
  216. data/.data/spec/std/isa/inst/{Q → Zfa}/fltq.q.yaml +2 -3
  217. data/.data/spec/std/isa/inst/{F → Zfa}/fltq.s.yaml +1 -1
  218. data/.data/spec/std/isa/inst/{Q → Zfa}/fmaxm.q.yaml +0 -1
  219. data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml +1 -1
  220. data/.data/spec/std/isa/inst/{Q → Zfa}/fminm.q.yaml +0 -1
  221. data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml +1 -1
  222. data/.data/spec/std/isa/inst/{Q → Zfa}/fmvp.q.x.yaml +1 -1
  223. data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
  224. data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml +1 -1
  225. data/.data/spec/std/isa/inst/Zfh/flh.yaml +5 -2
  226. data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +3 -1
  227. data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +3 -1
  228. data/.data/spec/std/isa/inst/Zfh/fsh.yaml +4 -1
  229. data/.data/spec/std/isa/inst/Zibi/beqi.yaml +45 -0
  230. data/.data/spec/std/isa/inst/Zibi/bnei.yaml +45 -0
  231. data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml +1 -1
  232. data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml +30 -0
  233. data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml +29 -0
  234. data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.d.yaml +1 -1
  235. data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.w.yaml +1 -1
  236. data/.data/spec/std/isa/inst/Zicfiss/sspopchk.yaml +63 -0
  237. data/.data/spec/std/isa/inst/Zicfiss/sspush.yaml +63 -0
  238. data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml +1 -1
  239. data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml +1 -1
  240. data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +12 -0
  241. data/.data/spec/std/isa/inst/Zilx/lxd.yaml +38 -0
  242. data/.data/spec/std/isa/inst/Zilx/lxh.yaml +35 -0
  243. data/.data/spec/std/isa/inst/Zilx/lxhu.yaml +35 -0
  244. data/.data/spec/std/isa/inst/Zilx/lxsb.yaml +40 -0
  245. data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml +40 -0
  246. data/.data/spec/std/isa/inst/Zilx/lxsd.yaml +38 -0
  247. data/.data/spec/std/isa/inst/Zilx/lxsh.yaml +35 -0
  248. data/.data/spec/std/isa/inst/Zilx/lxshu.yaml +35 -0
  249. data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml +40 -0
  250. data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml +40 -0
  251. data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml +39 -0
  252. data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml +40 -0
  253. data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml +40 -0
  254. data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml +40 -0
  255. data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml +40 -0
  256. data/.data/spec/std/isa/inst/Zilx/lxsw.yaml +35 -0
  257. data/.data/spec/std/isa/inst/Zilx/lxswu.yaml +39 -0
  258. data/.data/spec/std/isa/inst/Zilx/lxw.yaml +35 -0
  259. data/.data/spec/std/isa/inst/Zilx/lxwu.yaml +39 -0
  260. data/.data/spec/std/isa/inst/Zimop/mop.r.28.yaml +1 -2
  261. data/.data/spec/std/isa/inst/Zimop/mop.r.N.layout +1 -2
  262. data/.data/spec/std/isa/inst/Zimop/mop.rr.7.yaml +1 -2
  263. data/.data/spec/std/isa/inst/Zimop/mop.rr.N.layout +1 -2
  264. data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +67 -0
  265. data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +67 -0
  266. data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml +61 -0
  267. data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +72 -0
  268. data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +72 -0
  269. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vv.yaml +1 -1
  270. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vx.yaml +1 -1
  271. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vbrev8.v.yaml +1 -1
  272. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrev8.v.yaml +1 -1
  273. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vv.yaml +1 -1
  274. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vx.yaml +1 -1
  275. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vi.yaml +1 -1
  276. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vv.yaml +1 -1
  277. data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vx.yaml +1 -1
  278. data/.data/spec/std/isa/isa/fp.idl +42 -18
  279. data/.data/spec/std/isa/isa/globals.isa +1 -1
  280. data/.data/spec/std/isa/isa/util.idl +3 -3
  281. data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml +70 -6
  282. data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +9 -0
  283. data/.data/spec/std/isa/param/ELEN.yaml +27 -5
  284. data/.data/spec/std/isa/param/HCONTEXT_AVAILABLE.yaml +1 -1
  285. data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +13 -0
  286. data/.data/spec/std/isa/param/HPM_COUNTER_EN.yaml +13 -3
  287. data/.data/spec/std/isa/param/HPM_EVENTS.yaml +0 -3
  288. data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +8 -0
  289. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +71 -65
  290. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +71 -65
  291. data/.data/spec/std/isa/param/MUTABLE_MISA_H.yaml +1 -1
  292. data/.data/spec/std/isa/param/MUTABLE_MISA_S.yaml +1 -1
  293. data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +3 -2
  294. data/.data/spec/std/isa/param/STVEC_BASE_ALIGNMENT_VECTORED.yaml +100 -0
  295. data/.data/spec/std/isa/param/STVEC_MODES.yaml +31 -0
  296. data/.data/spec/std/isa/param/SV32_VSMODE_TRANSLATION.yaml +1 -1
  297. data/.data/spec/std/isa/param/SXLEN.yaml +2 -2
  298. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml +1 -1
  299. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml +1 -1
  300. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml +1 -1
  301. data/.data/spec/std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml +1 -1
  302. data/.data/spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml +1 -1
  303. data/.data/spec/std/isa/param/UXLEN.yaml +1 -1
  304. data/.data/spec/std/isa/param/VLEN.yaml +16 -7
  305. data/.data/spec/std/isa/param/VSTVEC_MODES.yaml +31 -0
  306. data/lib/udb/Z3_VERSION +1 -1
  307. data/lib/udb/config.rb +1 -1
  308. data/lib/udb/obj/csr.rb +1 -1
  309. data/lib/udb/obj/csr_field.rb +1 -1
  310. data/lib/udb/obj/extension.rb +1 -1
  311. data/lib/udb/version.rb +1 -1
  312. data/lib/udb/version_spec.rb +1 -1
  313. data/lib/udb/z3.rb +29 -7
  314. metadata +80 -50
  315. data/.data/spec/std/isa/inst/Zicfiss/sspopchk.x1.yaml +0 -25
  316. data/.data/spec/std/isa/inst/Zicfiss/sspopchk.x5.yaml +0 -25
  317. data/.data/spec/std/isa/inst/Zicfiss/sspush.x1.yaml +0 -25
  318. data/.data/spec/std/isa/inst/Zicfiss/sspush.x5.yaml +0 -25
  319. data/.data/spec/std/isa/param/STVEC_MODE_DIRECT.yaml +0 -21
  320. data/.data/spec/std/isa/param/STVEC_MODE_VECTORED.yaml +0 -19
  321. data/.data/spec/std/isa/param/VSTVEC_MODE_DIRECT.yaml +0 -21
  322. data/.data/spec/std/isa/param/VSTVEC_MODE_VECTORED.yaml +0 -21
  323. /data/.data/spec/std/isa/inst/{Smdbltrp → Smctr}/sctrclr.yaml +0 -0
  324. /data/.data/spec/std/isa/inst/{D → Zfa}/fcvtmod.w.d.yaml +0 -0
  325. /data/.data/spec/std/isa/inst/{D → Zfa}/fleq.d.yaml +0 -0
  326. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fleq.h.yaml +0 -0
  327. /data/.data/spec/std/isa/inst/{D → Zfa}/fli.d.yaml +0 -0
  328. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fli.h.yaml +0 -0
  329. /data/.data/spec/std/isa/inst/{D → Zfa}/fltq.d.yaml +0 -0
  330. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fltq.h.yaml +0 -0
  331. /data/.data/spec/std/isa/inst/{D → Zfa}/fmaxm.d.yaml +0 -0
  332. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fmaxm.h.yaml +0 -0
  333. /data/.data/spec/std/isa/inst/{D → Zfa}/fminm.d.yaml +0 -0
  334. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fminm.h.yaml +0 -0
  335. /data/.data/spec/std/isa/inst/{D → Zfa}/fmvh.x.d.yaml +0 -0
  336. /data/.data/spec/std/isa/inst/{Q → Zfa}/fmvh.x.q.yaml +0 -0
  337. /data/.data/spec/std/isa/inst/{D → Zfa}/fmvp.d.x.yaml +0 -0
  338. /data/.data/spec/std/isa/inst/{D → Zfa}/fround.d.yaml +0 -0
  339. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/fround.h.yaml +0 -0
  340. /data/.data/spec/std/isa/inst/{Q → Zfa}/fround.q.yaml +0 -0
  341. /data/.data/spec/std/isa/inst/{D → Zfa}/froundnx.d.yaml +0 -0
  342. /data/.data/spec/std/isa/inst/{Zfh → Zfa}/froundnx.h.yaml +0 -0
  343. /data/.data/spec/std/isa/inst/{Q → Zfa}/froundnx.q.yaml +0 -0
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data/.data/cfgs/example_rv64_with_overlay.yaml CHANGED
@@ -22,6 +22,7 @@ implemented_extensions:
22
22
  - [I, "2.1.0"]
23
23
  - [H, "1.0.0"]
24
24
  - [M, "2.0.0"]
25
+ - [Zmmul, "1.0.0"]
25
26
  - [S, "1.12.0"]
26
27
  - [Sm, "1.12.0"]
27
28
  - [U, "1.0.0"]
@@ -563,8 +564,8 @@ params:
563
564
  SV48X4_TRANSLATION: true
564
565
  SV57X4_TRANSLATION: false
565
566
  VMID_WIDTH: 8
566
- STVEC_MODE_DIRECT: true
567
- STVEC_MODE_VECTORED: true
567
+ STVEC_MODES: [0, 1]
568
+ STVEC_BASE_ALIGNMENT_VECTORED: 0x4
568
569
  SATP_MODE_BARE: true
569
570
  VSSTAGE_MODE_BARE: true
570
571
  REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT: true
@@ -591,16 +592,15 @@ params:
591
592
  MTVEC_MODES: [0, 1]
592
593
  MTVEC_ACCESS: rw
593
594
  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
594
- MTVEC_BASE_ALIGNMENT_DIRECT: 4
595
- MTVEC_BASE_ALIGNMENT_VECTORED: 4
595
+ MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
596
+ MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
596
597
  MSTATUS_FS_LEGAL_VALUES: [0, 1, 2, 3]
597
598
  HW_MSTATUS_FS_DIRTY_UPDATE: precise
598
599
  MSTATUS_VS_LEGAL_VALUES: [0, 1, 2, 3]
599
600
  HW_MSTATUS_VS_DIRTY_UPDATE: precise
600
601
  FORCE_UPGRADE_CBO_INVAL_TO_FLUSH: true
601
602
  REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT: true
602
- VSTVEC_MODE_DIRECT: true
603
- VSTVEC_MODE_VECTORED: true
603
+ VSTVEC_MODES: [0, 1]
604
604
  TRAP_ON_ECALL_FROM_VS: true
605
605
  TRAP_ON_ECALL_FROM_S: true
606
606
  TRAP_ON_ECALL_FROM_M: true
data/.data/cfgs/mc100-32-full-example.yaml CHANGED
@@ -11,6 +11,7 @@ implemented_extensions:
11
11
  - [C, "2.0"]
12
12
  - [Zca, "1.0"]
13
13
  - [M, "2.0"]
14
+ - [Zmmul, "1.0"]
14
15
  - [Zicsr, "2.0"]
15
16
  - [Zicntr, "2.0"]
16
17
  - [Smrnmi, "1.0"]
@@ -50,8 +51,8 @@ params:
50
51
  MTVEC_ACCESS: rw
51
52
  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
52
53
  MTVEC_MODES: [0, 1]
53
- MTVEC_BASE_ALIGNMENT_DIRECT: 4
54
- MTVEC_BASE_ALIGNMENT_VECTORED: 4
54
+ MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
55
+ MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
55
56
  MUTABLE_MISA_C: false
56
57
  MUTABLE_MISA_M: false
57
58
  TIME_CSR_IMPLEMENTED: false
data/.data/cfgs/profile/RVA20S64.yaml CHANGED
@@ -66,6 +66,8 @@ mandatory_extensions:
66
66
  version: "~> 2.0"
67
67
  - name: Zifencei
68
68
  version: "~> 2.0"
69
+ - name: Zmmul
70
+ version: "~> 1.0.0"
69
71
  non_mandatory_extensions:
70
72
  - name: Ssu64xl
71
73
  version: "~> 1.0"
data/.data/cfgs/profile/RVA20U64.yaml CHANGED
@@ -48,6 +48,8 @@ mandatory_extensions:
48
48
  version: "~> 2.0"
49
49
  - name: Zicsr
50
50
  version: "~> 2.0"
51
+ - name: Zmmul
52
+ version: "~> 1.0.0"
51
53
  non_mandatory_extensions:
52
54
  - name: Zca
53
55
  version: "~> 1.0"
data/.data/cfgs/profile/RVA22S64.yaml CHANGED
@@ -98,6 +98,8 @@ mandatory_extensions:
98
98
  version: "~> 2.0"
99
99
  - name: Zkt
100
100
  version: "~> 1.0"
101
+ - name: Zmmul
102
+ version: "~> 1.0.0"
101
103
  non_mandatory_extensions:
102
104
  - name: Sha
103
105
  version: "~> 1.0"
data/.data/cfgs/profile/RVA22U64.yaml CHANGED
@@ -74,6 +74,8 @@ mandatory_extensions:
74
74
  version: "~> 2.0"
75
75
  - name: Zkt
76
76
  version: "~> 1.0"
77
+ - name: Zmmul
78
+ version: "~> 1.0.0"
77
79
  non_mandatory_extensions:
78
80
  - name: V
79
81
  version: "~> 1.0"
data/.data/cfgs/profile/RVA23S64.yaml CHANGED
@@ -144,6 +144,8 @@ mandatory_extensions:
144
144
  version: "~> 1.0"
145
145
  - name: Zkt
146
146
  version: "~> 1.0"
147
+ - name: Zmmul
148
+ version: "~> 1.0.0"
147
149
  - name: Zvbb
148
150
  version: "~> 1.0"
149
151
  - name: Zve32f
data/.data/cfgs/profile/RVA23U64.yaml CHANGED
@@ -92,6 +92,8 @@ mandatory_extensions:
92
92
  version: "~> 1.0"
93
93
  - name: Zkt
94
94
  version: "~> 1.0"
95
+ - name: Zmmul
96
+ version: "~> 1.0.0"
95
97
  - name: Zvbb
96
98
  version: "~> 1.0"
97
99
  - name: Zve32f
data/.data/cfgs/profile/RVB23S64.yaml CHANGED
@@ -118,6 +118,8 @@ mandatory_extensions:
118
118
  version: "~> 1.0"
119
119
  - name: Zkt
120
120
  version: "~> 1.0"
121
+ - name: Zmmul
122
+ version: "~> 1.0.0"
121
123
  non_mandatory_extensions:
122
124
  - name: Sdtrig
123
125
  version: "~> 1.0"
data/.data/cfgs/profile/RVB23U64.yaml CHANGED
@@ -86,6 +86,8 @@ mandatory_extensions:
86
86
  version: "~> 1.0"
87
87
  - name: Zkt
88
88
  version: "~> 1.0"
89
+ - name: Zmmul
90
+ version: "~> 1.0.0"
89
91
  non_mandatory_extensions:
90
92
  - name: Supm
91
93
  version: "~> 1.0"
data/.data/cfgs/qc_iu.yaml CHANGED
@@ -12,6 +12,7 @@ implemented_extensions:
12
12
  - { name: Smdbltrp, version: "= 1.0" }
13
13
  - { name: I, version: "= 2.1" }
14
14
  - { name: M, version: "= 2.0" }
15
+ - { name: Zmmul, version: "= 1.0" }
15
16
  - { name: B, version: "= 1.0" }
16
17
  - { name: Zbs, version: "= 1.0" }
17
18
  - { name: Zbb, version: "= 1.0" }
@@ -186,6 +187,6 @@ params:
186
187
  MCOUNTINHIBIT_IMPLEMENTED: true
187
188
  MTVEC_ACCESS: rw
188
189
  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
189
- MTVEC_BASE_ALIGNMENT_DIRECT: 4
190
- MTVEC_BASE_ALIGNMENT_VECTORED: 4
190
+ MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
191
+ MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
191
192
  TIME_CSR_IMPLEMENTED: true
data/.data/cfgs/rv32-riscv-tests.yaml CHANGED
@@ -12,6 +12,7 @@ implemented_extensions:
12
12
  - [C, "2.0"]
13
13
  - [Zca, "1.0.0"]
14
14
  - [M, "2.0"]
15
+ - [Zmmul, "1.0"]
15
16
  - [Zicsr, "2.0"]
16
17
  - [Zicntr, "2.0"]
17
18
  - [Smrnmi, "1.0"]
@@ -58,8 +59,8 @@ params:
58
59
  MCOUNTINHIBIT_IMPLEMENTED: true
59
60
  MTVEC_ACCESS: rw
60
61
  MTVEC_MODES: [0, 1]
61
- MTVEC_BASE_ALIGNMENT_DIRECT: 4
62
- MTVEC_BASE_ALIGNMENT_VECTORED: 4
62
+ MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
63
+ MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
63
64
  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
64
65
  MUTABLE_MISA_C: false
65
66
  MUTABLE_MISA_M: false
@@ -188,8 +189,8 @@ params:
188
189
  false,
189
190
  false,
190
191
  ]
191
- STVEC_MODE_DIRECT: true
192
- STVEC_MODE_VECTORED: true
192
+ STVEC_MODES: [0, 1]
193
+ STVEC_BASE_ALIGNMENT_VECTORED: 0x4
193
194
  SATP_MODE_BARE: true
194
195
  TRAP_ON_ECALL_FROM_S: true
195
196
  MSTATUS_VS_LEGAL_VALUES: [0]
data/.data/cfgs/rv32-vector.yaml CHANGED
@@ -16,6 +16,7 @@ implemented_extensions:
16
16
  - [D, "2.2.0"]
17
17
  - [F, "2.2.0"]
18
18
  - [M, "2.0"]
19
+ - [Zmmul, "1.0"]
19
20
  - [Zicsr, "2.0"]
20
21
  - [Zicntr, "2.0"]
21
22
  - [Smrnmi, "1.0"]
@@ -68,8 +69,8 @@ params:
68
69
  MCOUNTINHIBIT_IMPLEMENTED: true
69
70
  MTVEC_ACCESS: rw
70
71
  MTVEC_MODES: [0, 1]
71
- MTVEC_BASE_ALIGNMENT_DIRECT: 4
72
- MTVEC_BASE_ALIGNMENT_VECTORED: 4
72
+ MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
73
+ MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
73
74
  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
74
75
  MUTABLE_MISA_C: false
75
76
  MUTABLE_MISA_D: false
@@ -200,8 +201,8 @@ params:
200
201
  false,
201
202
  false,
202
203
  ]
203
- STVEC_MODE_DIRECT: true
204
- STVEC_MODE_VECTORED: true
204
+ STVEC_MODES: [0, 1]
205
+ STVEC_BASE_ALIGNMENT_VECTORED: 0x4
205
206
  SATP_MODE_BARE: true
206
207
  TRAP_ON_ECALL_FROM_S: true
207
208
  TRAP_ON_ECALL_FROM_U: true
data/.data/cfgs/rv64-riscv-tests.yaml CHANGED
@@ -11,6 +11,7 @@ implemented_extensions:
11
11
  - [I, "2.1"]
12
12
  - [C, "2.0"]
13
13
  - [M, "2.0"]
14
+ - [Zmmul, "1.0"]
14
15
  - [Zicsr, "2.0"]
15
16
  - [Zicntr, "2.0"]
16
17
  - [Smrnmi, "1.0"]
@@ -56,8 +57,8 @@ params:
56
57
  MCOUNTINHIBIT_IMPLEMENTED: true
57
58
  MTVEC_ACCESS: rw
58
59
  MTVEC_MODES: [0, 1]
59
- MTVEC_BASE_ALIGNMENT_DIRECT: 4
60
- MTVEC_BASE_ALIGNMENT_VECTORED: 4
60
+ MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
61
+ MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
61
62
  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
62
63
  MUTABLE_MISA_C: false
63
64
  MUTABLE_MISA_M: false
@@ -186,8 +187,8 @@ params:
186
187
  false,
187
188
  false,
188
189
  ]
189
- STVEC_MODE_DIRECT: true
190
- STVEC_MODE_VECTORED: true
190
+ STVEC_MODES: [0, 1]
191
+ STVEC_BASE_ALIGNMENT_VECTORED: 0x4
191
192
  SATP_MODE_BARE: true
192
193
  TRAP_ON_ECALL_FROM_S: true
193
194
  TRAP_ON_ECALL_FROM_U: true
data/.data/cfgs/rv64-vector.yaml CHANGED
@@ -13,6 +13,7 @@ implemented_extensions:
13
13
  - [Zca, "1.0.0"]
14
14
  - [Zcd, "1.0.0"]
15
15
  - [M, "2.0"]
16
+ - [Zmmul, "1.0"]
16
17
  - [Zicsr, "2.0"]
17
18
  - [Zicntr, "2.0"]
18
19
  - [Smrnmi, "1.0"]
@@ -67,8 +68,8 @@ params:
67
68
  MCOUNTINHIBIT_IMPLEMENTED: true
68
69
  MTVEC_ACCESS: rw
69
70
  MTVEC_MODES: [0, 1]
70
- MTVEC_BASE_ALIGNMENT_DIRECT: 4
71
- MTVEC_BASE_ALIGNMENT_VECTORED: 4
71
+ MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
72
+ MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
72
73
  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
73
74
  MUTABLE_MISA_C: false
74
75
  MUTABLE_MISA_D: false
@@ -198,8 +199,8 @@ params:
198
199
  false,
199
200
  false,
200
201
  ]
201
- STVEC_MODE_DIRECT: true
202
- STVEC_MODE_VECTORED: true
202
+ STVEC_MODES: [0, 1]
203
+ STVEC_BASE_ALIGNMENT_VECTORED: 0x4
203
204
  SATP_MODE_BARE: true
204
205
  TRAP_ON_ECALL_FROM_S: true
205
206
  TRAP_ON_ECALL_FROM_U: true
data/.data/spec/schemas/README.adoc CHANGED
@@ -80,6 +80,9 @@ version should be released. Follow these steps:
80
80
  . The CI `schema-release` workflow will automatically publish the new version
81
81
  as a GitHub release under the tag `schemas/<schema_name>/<version>` when the
82
82
  changes are merged to `main`.
83
+ . Published schema version assets are immutable. If a release already exists
84
+ with different content, the publish workflow fails; bump the schema `$id`
85
+ instead of overwriting an existing version.
83
86
  . Previous schema versions remain available via their GitHub release tags and
84
87
  at `https://riscv.github.io/riscv-unified-db/schemas/<schema_name>/<old-version>/<schema_name>`.
85
88
 
data/.data/spec/schemas/schema_defs.json CHANGED
@@ -1,6 +1,6 @@
1
1
  {
2
2
  "$schema": "http://json-schema.org/draft-07/schema#",
3
- "$id": "v0.1",
3
+ "$id": "v0.2",
4
4
  "title": "Common patterns used by all schemas",
5
5
  "$defs": {
6
6
  "$source": {
@@ -863,7 +863,7 @@
863
863
  "description": "An unsigned power of 2 that fits in 32 bits",
864
864
  "type": "integer",
865
865
  "enum": [
866
- 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, 16384,
866
+ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384,
867
867
  32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304,
868
868
  8388608, 16777216, 33554432, 67108864, 134217728, 268435456, 536870912,
869
869
  1073741824, 2147483648
@@ -873,7 +873,7 @@
873
873
  "description": "An unsigned power of 2 that fits in 64 bits",
874
874
  "type": "integer",
875
875
  "enum": [
876
- 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, 16384,
876
+ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384,
877
877
  32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304,
878
878
  8388608, 16777216, 33554432, 67108864, 134217728, 268435456, 536870912,
879
879
  1073741824, 2147483648, 4294967296, 8589934592, 17179869184,
data/.data/spec/std/isa/csr/H/hcounteren.layout CHANGED
@@ -76,7 +76,7 @@ fields:
76
76
 
77
77
  [separator="!",%autowidth]
78
78
  !===
79
- .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `cycle` access behavior
79
+ .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `time` access behavior
80
80
  .>h! VS-mode .>h! VU-mode
81
81
 
82
82
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -116,7 +116,7 @@ fields:
116
116
 
117
117
  [separator="!",%autowidth]
118
118
  !===
119
- .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `cycle` access behavior
119
+ .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `instret` access behavior
120
120
  .>h! VS-mode .>h! VU-mode
121
121
 
122
122
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -154,7 +154,7 @@ fields:
154
154
 
155
155
  [separator="!",%autowidth]
156
156
  !===
157
- .2+h! [.rotate]#`hcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`mcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`scounteren.HPM<%= hpm_num %>`# 2+^.>! `cycle` access behavior
157
+ .2+h! [.rotate]#`hcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`mcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`scounteren.HPM<%= hpm_num %>`# 2+^.>! `hpmcounter<%= hpm_num %>` access behavior
158
158
  .>h! VS-mode .>h! VU-mode
159
159
 
160
160
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
data/.data/spec/std/isa/csr/H/hcounteren.yaml CHANGED
@@ -79,7 +79,7 @@ fields:
79
79
 
80
80
  [separator="!",%autowidth]
81
81
  !===
82
- .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `cycle` access behavior
82
+ .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `time` access behavior
83
83
  .>h! VS-mode .>h! VU-mode
84
84
 
85
85
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -119,7 +119,7 @@ fields:
119
119
 
120
120
  [separator="!",%autowidth]
121
121
  !===
122
- .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `cycle` access behavior
122
+ .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `instret` access behavior
123
123
  .>h! VS-mode .>h! VU-mode
124
124
 
125
125
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -156,7 +156,7 @@ fields:
156
156
 
157
157
  [separator="!",%autowidth]
158
158
  !===
159
- .2+h! [.rotate]#`hcounteren.HPM3`# .2+h! [.rotate]#`mcounteren.HPM3`# .2+h! [.rotate]#`scounteren.HPM3`# 2+^.>! `cycle` access behavior
159
+ .2+h! [.rotate]#`hcounteren.HPM3`# .2+h! [.rotate]#`mcounteren.HPM3`# .2+h! [.rotate]#`scounteren.HPM3`# 2+^.>! `hpmcounter3` access behavior
160
160
  .>h! VS-mode .>h! VU-mode
161
161
 
162
162
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -193,7 +193,7 @@ fields:
193
193
 
194
194
  [separator="!",%autowidth]
195
195
  !===
196
- .2+h! [.rotate]#`hcounteren.HPM4`# .2+h! [.rotate]#`mcounteren.HPM4`# .2+h! [.rotate]#`scounteren.HPM4`# 2+^.>! `cycle` access behavior
196
+ .2+h! [.rotate]#`hcounteren.HPM4`# .2+h! [.rotate]#`mcounteren.HPM4`# .2+h! [.rotate]#`scounteren.HPM4`# 2+^.>! `hpmcounter4` access behavior
197
197
  .>h! VS-mode .>h! VU-mode
198
198
 
199
199
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -230,7 +230,7 @@ fields:
230
230
 
231
231
  [separator="!",%autowidth]
232
232
  !===
233
- .2+h! [.rotate]#`hcounteren.HPM5`# .2+h! [.rotate]#`mcounteren.HPM5`# .2+h! [.rotate]#`scounteren.HPM5`# 2+^.>! `cycle` access behavior
233
+ .2+h! [.rotate]#`hcounteren.HPM5`# .2+h! [.rotate]#`mcounteren.HPM5`# .2+h! [.rotate]#`scounteren.HPM5`# 2+^.>! `hpmcounter5` access behavior
234
234
  .>h! VS-mode .>h! VU-mode
235
235
 
236
236
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -267,7 +267,7 @@ fields:
267
267
 
268
268
  [separator="!",%autowidth]
269
269
  !===
270
- .2+h! [.rotate]#`hcounteren.HPM6`# .2+h! [.rotate]#`mcounteren.HPM6`# .2+h! [.rotate]#`scounteren.HPM6`# 2+^.>! `cycle` access behavior
270
+ .2+h! [.rotate]#`hcounteren.HPM6`# .2+h! [.rotate]#`mcounteren.HPM6`# .2+h! [.rotate]#`scounteren.HPM6`# 2+^.>! `hpmcounter6` access behavior
271
271
  .>h! VS-mode .>h! VU-mode
272
272
 
273
273
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -304,7 +304,7 @@ fields:
304
304
 
305
305
  [separator="!",%autowidth]
306
306
  !===
307
- .2+h! [.rotate]#`hcounteren.HPM7`# .2+h! [.rotate]#`mcounteren.HPM7`# .2+h! [.rotate]#`scounteren.HPM7`# 2+^.>! `cycle` access behavior
307
+ .2+h! [.rotate]#`hcounteren.HPM7`# .2+h! [.rotate]#`mcounteren.HPM7`# .2+h! [.rotate]#`scounteren.HPM7`# 2+^.>! `hpmcounter7` access behavior
308
308
  .>h! VS-mode .>h! VU-mode
309
309
 
310
310
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -341,7 +341,7 @@ fields:
341
341
 
342
342
  [separator="!",%autowidth]
343
343
  !===
344
- .2+h! [.rotate]#`hcounteren.HPM8`# .2+h! [.rotate]#`mcounteren.HPM8`# .2+h! [.rotate]#`scounteren.HPM8`# 2+^.>! `cycle` access behavior
344
+ .2+h! [.rotate]#`hcounteren.HPM8`# .2+h! [.rotate]#`mcounteren.HPM8`# .2+h! [.rotate]#`scounteren.HPM8`# 2+^.>! `hpmcounter8` access behavior
345
345
  .>h! VS-mode .>h! VU-mode
346
346
 
347
347
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -378,7 +378,7 @@ fields:
378
378
 
379
379
  [separator="!",%autowidth]
380
380
  !===
381
- .2+h! [.rotate]#`hcounteren.HPM9`# .2+h! [.rotate]#`mcounteren.HPM9`# .2+h! [.rotate]#`scounteren.HPM9`# 2+^.>! `cycle` access behavior
381
+ .2+h! [.rotate]#`hcounteren.HPM9`# .2+h! [.rotate]#`mcounteren.HPM9`# .2+h! [.rotate]#`scounteren.HPM9`# 2+^.>! `hpmcounter9` access behavior
382
382
  .>h! VS-mode .>h! VU-mode
383
383
 
384
384
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -415,7 +415,7 @@ fields:
415
415
 
416
416
  [separator="!",%autowidth]
417
417
  !===
418
- .2+h! [.rotate]#`hcounteren.HPM10`# .2+h! [.rotate]#`mcounteren.HPM10`# .2+h! [.rotate]#`scounteren.HPM10`# 2+^.>! `cycle` access behavior
418
+ .2+h! [.rotate]#`hcounteren.HPM10`# .2+h! [.rotate]#`mcounteren.HPM10`# .2+h! [.rotate]#`scounteren.HPM10`# 2+^.>! `hpmcounter10` access behavior
419
419
  .>h! VS-mode .>h! VU-mode
420
420
 
421
421
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -452,7 +452,7 @@ fields:
452
452
 
453
453
  [separator="!",%autowidth]
454
454
  !===
455
- .2+h! [.rotate]#`hcounteren.HPM11`# .2+h! [.rotate]#`mcounteren.HPM11`# .2+h! [.rotate]#`scounteren.HPM11`# 2+^.>! `cycle` access behavior
455
+ .2+h! [.rotate]#`hcounteren.HPM11`# .2+h! [.rotate]#`mcounteren.HPM11`# .2+h! [.rotate]#`scounteren.HPM11`# 2+^.>! `hpmcounter11` access behavior
456
456
  .>h! VS-mode .>h! VU-mode
457
457
 
458
458
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -489,7 +489,7 @@ fields:
489
489
 
490
490
  [separator="!",%autowidth]
491
491
  !===
492
- .2+h! [.rotate]#`hcounteren.HPM12`# .2+h! [.rotate]#`mcounteren.HPM12`# .2+h! [.rotate]#`scounteren.HPM12`# 2+^.>! `cycle` access behavior
492
+ .2+h! [.rotate]#`hcounteren.HPM12`# .2+h! [.rotate]#`mcounteren.HPM12`# .2+h! [.rotate]#`scounteren.HPM12`# 2+^.>! `hpmcounter12` access behavior
493
493
  .>h! VS-mode .>h! VU-mode
494
494
 
495
495
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -526,7 +526,7 @@ fields:
526
526
 
527
527
  [separator="!",%autowidth]
528
528
  !===
529
- .2+h! [.rotate]#`hcounteren.HPM13`# .2+h! [.rotate]#`mcounteren.HPM13`# .2+h! [.rotate]#`scounteren.HPM13`# 2+^.>! `cycle` access behavior
529
+ .2+h! [.rotate]#`hcounteren.HPM13`# .2+h! [.rotate]#`mcounteren.HPM13`# .2+h! [.rotate]#`scounteren.HPM13`# 2+^.>! `hpmcounter13` access behavior
530
530
  .>h! VS-mode .>h! VU-mode
531
531
 
532
532
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -563,7 +563,7 @@ fields:
563
563
 
564
564
  [separator="!",%autowidth]
565
565
  !===
566
- .2+h! [.rotate]#`hcounteren.HPM14`# .2+h! [.rotate]#`mcounteren.HPM14`# .2+h! [.rotate]#`scounteren.HPM14`# 2+^.>! `cycle` access behavior
566
+ .2+h! [.rotate]#`hcounteren.HPM14`# .2+h! [.rotate]#`mcounteren.HPM14`# .2+h! [.rotate]#`scounteren.HPM14`# 2+^.>! `hpmcounter14` access behavior
567
567
  .>h! VS-mode .>h! VU-mode
568
568
 
569
569
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -600,7 +600,7 @@ fields:
600
600
 
601
601
  [separator="!",%autowidth]
602
602
  !===
603
- .2+h! [.rotate]#`hcounteren.HPM15`# .2+h! [.rotate]#`mcounteren.HPM15`# .2+h! [.rotate]#`scounteren.HPM15`# 2+^.>! `cycle` access behavior
603
+ .2+h! [.rotate]#`hcounteren.HPM15`# .2+h! [.rotate]#`mcounteren.HPM15`# .2+h! [.rotate]#`scounteren.HPM15`# 2+^.>! `hpmcounter15` access behavior
604
604
  .>h! VS-mode .>h! VU-mode
605
605
 
606
606
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -637,7 +637,7 @@ fields:
637
637
 
638
638
  [separator="!",%autowidth]
639
639
  !===
640
- .2+h! [.rotate]#`hcounteren.HPM16`# .2+h! [.rotate]#`mcounteren.HPM16`# .2+h! [.rotate]#`scounteren.HPM16`# 2+^.>! `cycle` access behavior
640
+ .2+h! [.rotate]#`hcounteren.HPM16`# .2+h! [.rotate]#`mcounteren.HPM16`# .2+h! [.rotate]#`scounteren.HPM16`# 2+^.>! `hpmcounter16` access behavior
641
641
  .>h! VS-mode .>h! VU-mode
642
642
 
643
643
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -674,7 +674,7 @@ fields:
674
674
 
675
675
  [separator="!",%autowidth]
676
676
  !===
677
- .2+h! [.rotate]#`hcounteren.HPM17`# .2+h! [.rotate]#`mcounteren.HPM17`# .2+h! [.rotate]#`scounteren.HPM17`# 2+^.>! `cycle` access behavior
677
+ .2+h! [.rotate]#`hcounteren.HPM17`# .2+h! [.rotate]#`mcounteren.HPM17`# .2+h! [.rotate]#`scounteren.HPM17`# 2+^.>! `hpmcounter17` access behavior
678
678
  .>h! VS-mode .>h! VU-mode
679
679
 
680
680
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -711,7 +711,7 @@ fields:
711
711
 
712
712
  [separator="!",%autowidth]
713
713
  !===
714
- .2+h! [.rotate]#`hcounteren.HPM18`# .2+h! [.rotate]#`mcounteren.HPM18`# .2+h! [.rotate]#`scounteren.HPM18`# 2+^.>! `cycle` access behavior
714
+ .2+h! [.rotate]#`hcounteren.HPM18`# .2+h! [.rotate]#`mcounteren.HPM18`# .2+h! [.rotate]#`scounteren.HPM18`# 2+^.>! `hpmcounter18` access behavior
715
715
  .>h! VS-mode .>h! VU-mode
716
716
 
717
717
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -748,7 +748,7 @@ fields:
748
748
 
749
749
  [separator="!",%autowidth]
750
750
  !===
751
- .2+h! [.rotate]#`hcounteren.HPM19`# .2+h! [.rotate]#`mcounteren.HPM19`# .2+h! [.rotate]#`scounteren.HPM19`# 2+^.>! `cycle` access behavior
751
+ .2+h! [.rotate]#`hcounteren.HPM19`# .2+h! [.rotate]#`mcounteren.HPM19`# .2+h! [.rotate]#`scounteren.HPM19`# 2+^.>! `hpmcounter19` access behavior
752
752
  .>h! VS-mode .>h! VU-mode
753
753
 
754
754
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -785,7 +785,7 @@ fields:
785
785
 
786
786
  [separator="!",%autowidth]
787
787
  !===
788
- .2+h! [.rotate]#`hcounteren.HPM20`# .2+h! [.rotate]#`mcounteren.HPM20`# .2+h! [.rotate]#`scounteren.HPM20`# 2+^.>! `cycle` access behavior
788
+ .2+h! [.rotate]#`hcounteren.HPM20`# .2+h! [.rotate]#`mcounteren.HPM20`# .2+h! [.rotate]#`scounteren.HPM20`# 2+^.>! `hpmcounter20` access behavior
789
789
  .>h! VS-mode .>h! VU-mode
790
790
 
791
791
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -822,7 +822,7 @@ fields:
822
822
 
823
823
  [separator="!",%autowidth]
824
824
  !===
825
- .2+h! [.rotate]#`hcounteren.HPM21`# .2+h! [.rotate]#`mcounteren.HPM21`# .2+h! [.rotate]#`scounteren.HPM21`# 2+^.>! `cycle` access behavior
825
+ .2+h! [.rotate]#`hcounteren.HPM21`# .2+h! [.rotate]#`mcounteren.HPM21`# .2+h! [.rotate]#`scounteren.HPM21`# 2+^.>! `hpmcounter21` access behavior
826
826
  .>h! VS-mode .>h! VU-mode
827
827
 
828
828
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -859,7 +859,7 @@ fields:
859
859
 
860
860
  [separator="!",%autowidth]
861
861
  !===
862
- .2+h! [.rotate]#`hcounteren.HPM22`# .2+h! [.rotate]#`mcounteren.HPM22`# .2+h! [.rotate]#`scounteren.HPM22`# 2+^.>! `cycle` access behavior
862
+ .2+h! [.rotate]#`hcounteren.HPM22`# .2+h! [.rotate]#`mcounteren.HPM22`# .2+h! [.rotate]#`scounteren.HPM22`# 2+^.>! `hpmcounter22` access behavior
863
863
  .>h! VS-mode .>h! VU-mode
864
864
 
865
865
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -896,7 +896,7 @@ fields:
896
896
 
897
897
  [separator="!",%autowidth]
898
898
  !===
899
- .2+h! [.rotate]#`hcounteren.HPM23`# .2+h! [.rotate]#`mcounteren.HPM23`# .2+h! [.rotate]#`scounteren.HPM23`# 2+^.>! `cycle` access behavior
899
+ .2+h! [.rotate]#`hcounteren.HPM23`# .2+h! [.rotate]#`mcounteren.HPM23`# .2+h! [.rotate]#`scounteren.HPM23`# 2+^.>! `hpmcounter23` access behavior
900
900
  .>h! VS-mode .>h! VU-mode
901
901
 
902
902
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -933,7 +933,7 @@ fields:
933
933
 
934
934
  [separator="!",%autowidth]
935
935
  !===
936
- .2+h! [.rotate]#`hcounteren.HPM24`# .2+h! [.rotate]#`mcounteren.HPM24`# .2+h! [.rotate]#`scounteren.HPM24`# 2+^.>! `cycle` access behavior
936
+ .2+h! [.rotate]#`hcounteren.HPM24`# .2+h! [.rotate]#`mcounteren.HPM24`# .2+h! [.rotate]#`scounteren.HPM24`# 2+^.>! `hpmcounter24` access behavior
937
937
  .>h! VS-mode .>h! VU-mode
938
938
 
939
939
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -970,7 +970,7 @@ fields:
970
970
 
971
971
  [separator="!",%autowidth]
972
972
  !===
973
- .2+h! [.rotate]#`hcounteren.HPM25`# .2+h! [.rotate]#`mcounteren.HPM25`# .2+h! [.rotate]#`scounteren.HPM25`# 2+^.>! `cycle` access behavior
973
+ .2+h! [.rotate]#`hcounteren.HPM25`# .2+h! [.rotate]#`mcounteren.HPM25`# .2+h! [.rotate]#`scounteren.HPM25`# 2+^.>! `hpmcounter25` access behavior
974
974
  .>h! VS-mode .>h! VU-mode
975
975
 
976
976
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1007,7 +1007,7 @@ fields:
1007
1007
 
1008
1008
  [separator="!",%autowidth]
1009
1009
  !===
1010
- .2+h! [.rotate]#`hcounteren.HPM26`# .2+h! [.rotate]#`mcounteren.HPM26`# .2+h! [.rotate]#`scounteren.HPM26`# 2+^.>! `cycle` access behavior
1010
+ .2+h! [.rotate]#`hcounteren.HPM26`# .2+h! [.rotate]#`mcounteren.HPM26`# .2+h! [.rotate]#`scounteren.HPM26`# 2+^.>! `hpmcounter26` access behavior
1011
1011
  .>h! VS-mode .>h! VU-mode
1012
1012
 
1013
1013
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1044,7 +1044,7 @@ fields:
1044
1044
 
1045
1045
  [separator="!",%autowidth]
1046
1046
  !===
1047
- .2+h! [.rotate]#`hcounteren.HPM27`# .2+h! [.rotate]#`mcounteren.HPM27`# .2+h! [.rotate]#`scounteren.HPM27`# 2+^.>! `cycle` access behavior
1047
+ .2+h! [.rotate]#`hcounteren.HPM27`# .2+h! [.rotate]#`mcounteren.HPM27`# .2+h! [.rotate]#`scounteren.HPM27`# 2+^.>! `hpmcounter27` access behavior
1048
1048
  .>h! VS-mode .>h! VU-mode
1049
1049
 
1050
1050
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1081,7 +1081,7 @@ fields:
1081
1081
 
1082
1082
  [separator="!",%autowidth]
1083
1083
  !===
1084
- .2+h! [.rotate]#`hcounteren.HPM28`# .2+h! [.rotate]#`mcounteren.HPM28`# .2+h! [.rotate]#`scounteren.HPM28`# 2+^.>! `cycle` access behavior
1084
+ .2+h! [.rotate]#`hcounteren.HPM28`# .2+h! [.rotate]#`mcounteren.HPM28`# .2+h! [.rotate]#`scounteren.HPM28`# 2+^.>! `hpmcounter28` access behavior
1085
1085
  .>h! VS-mode .>h! VU-mode
1086
1086
 
1087
1087
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1118,7 +1118,7 @@ fields:
1118
1118
 
1119
1119
  [separator="!",%autowidth]
1120
1120
  !===
1121
- .2+h! [.rotate]#`hcounteren.HPM29`# .2+h! [.rotate]#`mcounteren.HPM29`# .2+h! [.rotate]#`scounteren.HPM29`# 2+^.>! `cycle` access behavior
1121
+ .2+h! [.rotate]#`hcounteren.HPM29`# .2+h! [.rotate]#`mcounteren.HPM29`# .2+h! [.rotate]#`scounteren.HPM29`# 2+^.>! `hpmcounter29` access behavior
1122
1122
  .>h! VS-mode .>h! VU-mode
1123
1123
 
1124
1124
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1155,7 +1155,7 @@ fields:
1155
1155
 
1156
1156
  [separator="!",%autowidth]
1157
1157
  !===
1158
- .2+h! [.rotate]#`hcounteren.HPM30`# .2+h! [.rotate]#`mcounteren.HPM30`# .2+h! [.rotate]#`scounteren.HPM30`# 2+^.>! `cycle` access behavior
1158
+ .2+h! [.rotate]#`hcounteren.HPM30`# .2+h! [.rotate]#`mcounteren.HPM30`# .2+h! [.rotate]#`scounteren.HPM30`# 2+^.>! `hpmcounter30` access behavior
1159
1159
  .>h! VS-mode .>h! VU-mode
1160
1160
 
1161
1161
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1192,7 +1192,7 @@ fields:
1192
1192
 
1193
1193
  [separator="!",%autowidth]
1194
1194
  !===
1195
- .2+h! [.rotate]#`hcounteren.HPM31`# .2+h! [.rotate]#`mcounteren.HPM31`# .2+h! [.rotate]#`scounteren.HPM31`# 2+^.>! `cycle` access behavior
1195
+ .2+h! [.rotate]#`hcounteren.HPM31`# .2+h! [.rotate]#`mcounteren.HPM31`# .2+h! [.rotate]#`scounteren.HPM31`# 2+^.>! `hpmcounter31` access behavior
1196
1196
  .>h! VS-mode .>h! VU-mode
1197
1197
 
1198
1198
  ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
data/.data/spec/std/isa/csr/H/henvcfg.yaml CHANGED
@@ -258,7 +258,7 @@ fields:
258
258
  if (csr_value.CBIE == 0 || csr_value.CBIE == 1 || csr_value.CBIE == 3) {
259
259
  return csr_value.CBIE;
260
260
  } else {
261
- return CSR[menvcfg].CBIE;
261
+ return CSR[henvcfg].CBIE;
262
262
  }
263
263
  reset_value: UNDEFINED_LEGAL
264
264
  SSE:
data/.data/spec/std/isa/csr/H/htimedeltah.yaml CHANGED
@@ -29,4 +29,4 @@ fields:
29
29
  CSR[htimedelta].DELTA = {csr_value.DELTA, CSR[htimedelta].DELTA[31:0]};
30
30
  return csr_value.DELTA;
31
31
  sw_read(): |
32
- return CSR[htimedelta].DELTA[31:0];
32
+ return CSR[htimedelta].DELTA[63:32];