udb 0.1.14 → 0.1.16

data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout

@@ -82,14 +82,14 @@ fields:
         <%%- if ext?(:Sscofpmf) -%>
         * `mhpmevent<%= hpm_num %>.MINH` is set and the current privilege level is M
         <%%- if ext?(:S) -%>
-        * `mhpmevent<%= hpm_num %>.SINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>..SINH`<%%- end -%> is set and the current privilege level is (H)S
+        * `mhpmevent<%= hpm_num %>.SINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is (H)S
         <%%- end -%>
         <%%- if ext?(:U) -%>
-        * `mhpmevent<%= hpm_num %>.UINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is U
+        * `mhpmevent<%= hpm_num %>.UINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.UINH`<%%- end -%> is set and the current privilege level is U
         <%%- end -%>
         <%%- if ext?(:H) -%>
-        * `mhpmevent<%= hpm_num %>.VSINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is VS
-        * `mhpmevent<%= hpm_num %>.VUINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.SINH`<%%- end -%> is set and the current privilege level is VU
+        * `mhpmevent<%= hpm_num %>.VSINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.VSINH`<%%- end -%> is set and the current privilege level is VS
+        * `mhpmevent<%= hpm_num %>.VUINH` <%%- if ext?(:Ssccfg) -%>or its alias `hpmevent<%= hpm_num %>.VUINH`<%%- end -%> is set and the current privilege level is VU
         <%%- end -%>
         <%%- end -%>
       --

data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout

@@ -72,7 +72,7 @@ definedBy:
 fields:
   COUNT:
     location: 31-0
-    alias: mhpmcounter.COUNT<%= hpm_num %>[63:32]
+    alias: mhpmcounter<%= hpm_num %>.COUNT[63:32]
     description: |
       Upper bits of counter.
     type(): |

data/.data/spec/std/isa/csr/hstateen0h.yaml

@@ -156,4 +156,4 @@ fields:
       `mstateen0.CTR=0`.
     type: RW
     reset_value: 0
-sw_read(): return $bits(CSR[hstateen0])[63:32];
+sw_read(): return CSR[hstateen0].sw_read()[63:32];

data/.data/spec/std/isa/csr/hstateen1h.yaml

@@ -44,4 +44,4 @@ fields:
       The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR.
     type: RW
     reset_value: UNDEFINED_LEGAL
-sw_read(): return $bits(CSR[hstateen1])[63:32];
+sw_read(): return CSR[hstateen1].sw_read()[63:32];

data/.data/spec/std/isa/csr/hstateen2h.yaml

@@ -44,4 +44,4 @@ fields:
       The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR.
     type: RW
     reset_value: UNDEFINED_LEGAL
-sw_read(): return $bits(CSR[hstateen2])[63:32];
+sw_read(): return CSR[hstateen2].sw_read()[63:32];

data/.data/spec/std/isa/csr/hstateen3h.yaml

@@ -44,4 +44,4 @@ fields:
       The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR.
     type: RW
     reset_value: UNDEFINED_LEGAL
-sw_read(): return $bits(CSR[hstateen3])[63:32];
+sw_read(): return CSR[hstateen3].sw_read()[63:32];

data/.data/spec/std/isa/csr/hstatus.yaml

@@ -138,7 +138,7 @@ fields:
 
       Notably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap.
 
-      `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.TVTM`.
+      `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.VTVM`.
     type: RW
     reset_value: UNDEFINED_LEGAL
   VGEIN:

data/.data/spec/std/isa/csr/instreth.yaml

@@ -76,6 +76,4 @@ sw_read(): |
     }
   }
 
-  # since the counter may be shared among harts, reads must be handled
-  # as a builtin function
-  return read_mcycle();
+  return CSR[minstret].COUNT[63:32];

data/.data/spec/std/isa/csr/mcycle.yaml

@@ -32,7 +32,7 @@ fields:
       # since writes to this register may not be hart-local, it must be handled
       # as a special case
       if (xlen() == 32) {
-        return sw_write_mcycle({read_mcycle()[63:31], csr_value.COUNT[31:0]});
+        return sw_write_mcycle({read_mcycle()[63:32], csr_value.COUNT[31:0]});
       } else {
         return sw_write_mcycle(csr_value.COUNT);
       }
@@ -40,7 +40,7 @@ fields:
       Cycle counter.
 
       <%- if ext?(:Zicntr) -%>
-      Aliased as `cycle.CYCLE`.
+      Aliased as `cycle.COUNT`.
       <%- end -%>
 
       Increments every cycle unless:
@@ -49,14 +49,14 @@ fields:
         <%- if ext?(:Smcntrpmf) -%>
         * `mcyclecfg.MINH` is set and the current privilege level is M
         <%- if ext?(:S) -%>
-        * `mcyclecfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is (H)S
+        * `mcyclecfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.SINH`<%- end -%> is set and the current privilege level is (H)S
         <%- end -%>
         <%- if ext?(:U) -%>
-        * `mcyclecfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is U
+        * `mcyclecfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.UINH`<%- end -%> is set and the current privilege level is U
         <%- end -%>
         <%- if ext?(:H) -%>
-        * `mcyclecfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VS
-        * `mcyclecfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VU
+        * `mcyclecfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.VSINH`<%- end -%> is set and the current privilege level is VS
+        * `mcyclecfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `cyclecfg.VUINH`<%- end -%> is set and the current privilege level is VU
         <%- end -%>
         <%- end -%>
     reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/csr/minstret.yaml

@@ -37,11 +37,11 @@ fields:
         * `minstretcfg.SINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is (H)S
         <%- end -%>
         <%- if ext?(:U) -%>
-        * `minstretcfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is U
+        * `minstretcfg.UINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.UINH`<%- end -%> is set and the current privilege level is U
         <%- end -%>
         <%- if ext?(:H) -%>
-        * `minstretcfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VS
-        * `minstretcfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.SINH`<%- end -%> is set and the current privilege level is VU
+        * `minstretcfg.VSINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.VSINH`<%- end -%> is set and the current privilege level is VS
+        * `minstretcfg.VUINH` <%- if ext?(:Ssccfg) -%>or its alias `instretcfg.VUINH`<%- end -%> is set and the current privilege level is VU
         <%- end -%>
         <%- end -%>
 

data/.data/spec/std/isa/csr/minstreth.yaml

@@ -28,12 +28,12 @@ fields:
     reset_value: UNDEFINED_LEGAL
     affectedBy: [Zicntr, Smcntrpmf, Smcdeleg, Ssccfg]
     sw_write(csr_value): |
-      CSR[mcycle].COUNT = {csr_value.COUNT[31:0], CSR[minstret].COUNT[31:0]};
+      CSR[minstret].COUNT = {csr_value.COUNT[31:0], CSR[minstret].COUNT[31:0]};
       return csr_value.COUNT;
 definedBy:
   allOf:
     - xlen: 32
     - extension:
-        name: Zicntr
+        name: Sm
 sw_read(): |
   return CSR[minstret].COUNT[63:32];

data/.data/spec/std/isa/csr/mstatus.yaml

@@ -71,7 +71,7 @@ fields:
         - extension:
             name: Smdbltrp
     type: RW-H
-    reset_value: UNDEFINED_LEGAL
+    reset_value: 1
   MPELP:
     location: 41
     long_name: M-mode Previous Expected Landing Pad state
@@ -111,7 +111,11 @@ fields:
     long_name: Guest Virtual Address
     description: |
       When a trap is taken and a guest virtual address is written into mtval, GVA is set.
-      When a trap is taken and a guest virtual address is written into mtval, GVA is cleared.
+      GVA is written by the implementation whenever a trap is taken into
+      HS mode. For any trap (breakpoint, address misaligned, access fault,
+      page fault, or guest-page fault) that writes a guest virtual address to
+      `stval`, GVA is set to 1. For any other trap into HS-mode,
+      GVA is set to 0.
     type: RW-H
     reset_value: 0
     definedBy:
@@ -436,6 +440,10 @@ fields:
           - name: F
           - name: S
     reset_value(): |
+      if (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
+        # must be read-only-0
+        return 0;
+      }
       return $array_size(MSTATUS_FS_LEGAL_VALUES) == 1 ? MSTATUS_FS_LEGAL_VALUES[0] : UNDEFINED_LEGAL;
     sw_write(csr_value): |
       if (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
@@ -499,31 +507,17 @@ fields:
         return $array_size(MSTATUS_VS_LEGAL_VALUES) == 1 ? CsrFieldType::RO : CsrFieldType::RW;
       }
     reset_value(): |
-      if (CSR[misa].V == 1'b1){
-        return UNDEFINED_LEGAL;
-      } else if ((CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0)) {
+      if ((!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) || (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0))) {
         # must be read-only-0
         return 0;
-      } else {
-        # there will be no hardware update in this case because we know the V extension isn't implemented
-        if ($array_size(MSTATUS_VS_LEGAL_VALUES) == 0) {
-          return 0;
-        } else if ($array_size(MSTATUS_VS_LEGAL_VALUES) == 1) {
-          return MSTATUS_VS_LEGAL_VALUES[0];
-        } else {
-          return UNDEFINED_LEGAL;
-        }
       }
+      return $array_size(MSTATUS_VS_LEGAL_VALUES) == 1 ? MSTATUS_VS_LEGAL_VALUES[0] : UNDEFINED_LEGAL;
     sw_write(csr_value): |
-      if (implemented?(ExtensionName::V) && CSR[misa].V == 1'b1){
-        return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) {
+      if ((!implemented?(ExtensionName::S) && !implemented?(ExtensionName::V)) || (MISA_CSR_IMPLEMENTED && (CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0))) {
         # must be read-only-0
         return 0;
-      } else {
-        # there will be no hardware update in this case because we know the V extension isn't implemented
-        return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
       }
+      return $array_includes?(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
   SPP:
     location: 8
     long_name: S-mode Previous Privilege

data/.data/spec/std/isa/csr/mstatush.yaml

@@ -26,7 +26,7 @@ fields:
     description: |
       see `mstatus.MDT`
     type: RW-H
-    reset_value: UNDEFINED_LEGAL
+    reset_value: 1
     alias: mstatus.MDT
     definedBy:
       extension:

data/.data/spec/std/isa/csr/mtvec.yaml

@@ -30,37 +30,15 @@ fields:
       # implementations may put further constraints on BASE when MODE != Direct
       # If that is the case, stvec should have an override for the implementation
 
-      if (csr_value.MODE == 0) {
-        if ($array_includes?(MTVEC_MODES, 0)) {
-          return csr_value.BASE;
-        }
-        if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
-          return CSR[mtvec].BASE;
-        }
-        if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
-          return UNDEFINED_LEGAL_DETERMINISTIC;
-        }
-        unreachable();
-      } else if (csr_value.MODE == 1) {
-        if ($array_includes?(MTVEC_MODES, 1)) {
-          return csr_value.BASE;
-        }
-        if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
-          return CSR[mtvec].BASE;
-        }
-        if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
-          return UNDEFINED_LEGAL_DETERMINISTIC;
-        }
-        unreachable();
-      } else {
-        if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
-          return CSR[mtvec].BASE;
-        }
-        if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
-          return UNDEFINED_LEGAL_DETERMINISTIC;
-        }
-        unreachable();
+      if ($array_includes?(MTVEC_MODES, csr_value.MODE)) {
+        return csr_value.BASE;
       }
+      if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
+        return CSR[mtvec].BASE;
+      } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
+        return UNDEFINED_LEGAL_DETERMINISTIC;
+      }
+      unreachable();
     reset_value: 0
   MODE:
     location: 1-0
@@ -71,7 +49,7 @@ fields:
 
       When Direct, all synchronous exceptions and asynchronous interrupts jump to (`mtvec.BASE` << 2).
 
-      When Vectored, asynchronous interrupts jump to (`mtvec.BASE` << 2 + `mcause.CAUSE`*4) while synchronous exceptions continue to jump to (`mtvec.BASE` << 2).
+      When Vectored, asynchronous interrupts jump to (`mtvec.BASE` << 2 + `mcause.CODE`*4) while synchronous exceptions continue to jump to (`mtvec.BASE` << 2).
     type(): |
       if (MTVEC_ACCESS == "ro") {
         return CsrFieldType::RO;
@@ -79,32 +57,13 @@ fields:
 
       return ($array_size(MTVEC_MODES) == 1) ? CsrFieldType::RO : CsrFieldType::RWR;
     sw_write(csr_value): |
-      if (csr_value.MODE == 0) {
-        if ($array_includes?(MTVEC_MODES, 0)) {
-          return csr_value.MODE;
-        } else {
-          if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
-            return CSR[mtvec].MODE;
-          } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
-            return UNDEFINED_LEGAL_DETERMINISTIC;
-          }
-        }
-      } else if (csr_value.MODE == 1) {
-        if ($array_includes?(MTVEC_MODES, 1)) {
-          return csr_value.MODE;
-        } else {
-          if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
-            return CSR[mtvec].MODE;
-          } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
-            return UNDEFINED_LEGAL_DETERMINISTIC;
-          }
-        }
-      } else {
-        if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
-          return CSR[mtvec].MODE;
-        } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
-          return UNDEFINED_LEGAL_DETERMINISTIC;
-        }
+      if ($array_includes?(MTVEC_MODES, csr_value.MODE)) {
+        return csr_value.MODE;
+      }
+      if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "retain") {
+        return CSR[mtvec].MODE;
+      } else if (MTVEC_ILLEGAL_WRITE_BEHAVIOR == "custom") {
+        return UNDEFINED_LEGAL_DETERMINISTIC;
       }
       unreachable();
     reset_value(): |

data/.data/spec/std/isa/csr/senvcfg.yaml

@@ -12,7 +12,7 @@ long_name: Supervisor Environment Configuration
 description: |
   Contains fields that control certain characteristics of the U-mode execution environment.
 priv_mode: S
-length: 64
+length: SXLEN
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/csr/sepc.yaml

@@ -10,7 +10,7 @@ long_name: Supervisor Exception Program Counter
 address: 0x141
 writable: true
 priv_mode: S
-length: 64
+length: SXLEN
 description: |
   Written with the PC of an instruction on an exception or interrupt taken in (H)S-mode.
 
@@ -20,7 +20,8 @@ definedBy:
     name: S
 fields:
   PC:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: |
       When a trap is taken into S-mode, `sepc.PC` is written with the virtual address of the
       instruction that was interrupted or that encountered the exception.
@@ -38,7 +39,7 @@ fields:
       When `misa.C` is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
       may be visible on the next read with `misa.C` is set.
 
-      Holds bits 63:<%= ext?(:C) ? 2 : 1 %> of the virtual address associated with an exception.
+      Holds bits [SXLEN-1:<%= ext?(:C) ? 2 : 1 %>] of the virtual address associated with an exception.
     type: RW-RH
     sw_write(csr_value): |
       return csr_value.PC & ~64'b1;

data/.data/spec/std/isa/csr/sie.yaml

@@ -15,34 +15,60 @@ definedBy:
 length: SXLEN
 description: Supervisor interrupt-enable register.
 writable: true
+sw_read(): |
+  return $bits(CSR[mie]) & $bits(CSR[mideleg]);
 fields:
   SSIE:
     location: 1
     alias: mie.SSIE
     description: |
       Supervisor Software Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].SSI == 1'b1) {
+        CSR[mie].SSIE = csr_value.SSIE;
+        return csr_value.SSIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
   STIE:
     location: 5
     alias: mie.STIE
     description: |
       Supervisor Timer Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].STI == 1'b1) {
+        CSR[mie].STIE = csr_value.STIE;
+        return csr_value.STIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
   SEIE:
     location: 9
     alias: mie.SEIE
     description: |
       Supervisor External Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].SEI == 1'b1) {
+        CSR[mie].SEIE = csr_value.SEIE;
+        return csr_value.SEIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
   LCOFIE:
     location: 13
     alias: mie.LCOFIE
     description: |
       Local Counter Overflow Interrupt Enable
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].LCOFI == 1'b1) {
+        CSR[mie].LCOFIE = csr_value.LCOFIE;
+        return csr_value.LCOFIE;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
     definedBy:
       extension:

data/.data/spec/std/isa/csr/sip.yaml

@@ -15,10 +15,12 @@ description: |
 
   Hypervisor-related interrupts (VS-mode interrupts and Supervisor Guest interrupts) are not reflected
   in `sip` even though those interrupts can be taken in HS-mode. Instead, they are reported through `hip`.
-length: 64
+length: SXLEN
 definedBy:
   extension:
     name: S
+sw_read(): |
+  return $bits(CSR[mip]) & $bits(CSR[mideleg]);
 fields:
   SSIP:
     location: 1
@@ -59,7 +61,13 @@ fields:
       ! 0 ! read-only 0
       ! 1 ! writable alias of `mip.SSIP` <% if ext?(:Smaia) %>and `mvip.SSIP`<% end %>
       !===
-    type: RW
+    type: RW-R
+    sw_write(csr_value): |
+      if (CSR[mideleg].SSI == 1'b1) {
+        CSR[mip].SSIP = csr_value.SSIP;
+        return csr_value.SSIP;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
     definedBy:
       extension:
@@ -153,7 +161,13 @@ fields:
       ! 1
       a! writable alias of `mip.LCOFIP` (and `vsip.LCOFIP` when `hideleg.LCOFI` is set)
       !===
-    type: RW-H
+    type: RW-RH
+    sw_write(csr_value): |
+      if (CSR[mideleg].LCOFI == 1'b1) {
+        CSR[mip].LCOFIP = csr_value.LCOFIP;
+        return csr_value.LCOFIP;
+      }
+      return 1'b0;
     reset_value: UNDEFINED_LEGAL
     definedBy:
       extension:

data/.data/spec/std/isa/csr/sscratch.yaml

@@ -10,14 +10,15 @@ long_name: Supervisor Scratch Register
 address: 0x140
 writable: true
 priv_mode: S
-length: 64
+length: SXLEN
 description: Scratch register for software use. Bits are not interpreted by hardware.
 definedBy: # actually, defined by RV64, but must implement U-mode for this CSR to exist
   extension:
     name: S
 fields:
   SCRATCH:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: Scratch value
     type: RW
     reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/csr/stval.yaml

@@ -11,13 +11,14 @@ address: 0x143
 writable: true
 description: Holds trap-specific information
 priv_mode: S
-length: 64
+length: SXLEN
 definedBy:
   extension:
     name: S
 fields:
   VALUE:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: |
       Written with trap-specific information when a trap is taken into S-mode.
 

data/.data/spec/std/isa/csr/stvec.yaml

@@ -10,19 +10,20 @@ long_name: Supervisor Trap Vector
 address: 0x105
 writable: true
 priv_mode: S
-length: 64
+length: SXLEN
 description: Controls where traps jump.
 definedBy:
   extension:
     name: S
 fields:
   BASE:
-    location: 63-2
+    location_rv32: 31-2
+    location_rv64: 63-2
     description: |
-      <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 49 :39) -%>
-      Bit 63:0 of the virtual address of the exception vector for any trap taken into S-mode.
+      <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 48 : 39) -%>
+      Bits [SXLEN-1:2] of the virtual address of the exception vector for any trap taken into S-mode.
 
-      If the base address is written with a non-cannonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
+      If the base address is written with a non-canonical address (_i.e._, bits [SXLEN-1:<%= va_size %>] do not match bit <%= va_size-1 %>),
       the write should be ignored.
 
     type: RW-R
@@ -41,14 +42,13 @@ fields:
 
       When Direct, all synchronous exceptions and asynchronous interrupts jump to (`stvec.BASE` << 2).
 
-      When Vectored, asynchronous interrupts jump to (`stvec.BASE` << 2 + `scause.CAUSE`*4) while synchronous exceptions continue to jump to (`stvec.BASE` << 2).
-    type: RW-R
+      When Vectored, asynchronous interrupts jump to (`stvec.BASE` << 2 + `scause.CODE`*4) while synchronous exceptions continue to jump to (`stvec.BASE` << 2).
+    type(): |
+      return ($array_size(STVEC_MODES) == 1) ? CsrFieldType::RO : CsrFieldType::RWR;
     sw_write(csr_value): |
-      if (STVEC_MODE_DIRECT && csr_value.MODE == 0) {
-        return 0;
-      } else if (STVEC_MODE_VECTORED && csr_value.MODE == 1) {
-        return 1;
-      } else {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
+      if ($array_includes?(STVEC_MODES, csr_value.MODE)) {
+        return csr_value.MODE;
       }
-    reset_value: 0
+      return UNDEFINED_LEGAL_DETERMINISTIC;
+    reset_value(): |
+      return ($array_size(STVEC_MODES) == 1) ? STVEC_MODES[0] : UNDEFINED_LEGAL;

data/.data/spec/std/isa/csr/time.yaml

@@ -79,7 +79,7 @@ sw_read(): |
     }
   } else if (mode() == PrivilegeMode::VU) {
     # access in VU mode
-    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].IR == 1'b1)) {
+    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].TM == 1'b1)) {
       raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
     } else if (CSR[mcounteren].TM == 1'b0) {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/csr/timeh.yaml

@@ -80,7 +80,7 @@ sw_read(): |
     }
   } else if (mode() == PrivilegeMode::VU) {
     # access in VU mode
-    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].IR == 1'b1)) {
+    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].TM == 1'b1)) {
       raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
     } else if (CSR[mcounteren].TM == 1'b0) {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/csr/vsepc.yaml

@@ -11,7 +11,7 @@ address: 0x241
 writable: true
 virtual_address: 0x141
 priv_mode: VS
-length: 64
+length: VSXLEN
 description: |
   Written with the PC of an instruction on an exception or interrupt taken in VS-mode.
 
@@ -21,7 +21,8 @@ definedBy:
     name: H
 fields:
   PC:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: |
       When a trap is taken into VS-mode, `vsepc.PC` is written with the virtual address of the
       instruction that was interrupted or that encountered the exception.
@@ -39,14 +40,14 @@ fields:
       When `misa.C` is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
       may be visible on the next read with `misa.C` is set.
 
-      Holds bits 63:<%= ext?(:C) ? 2 : 1 %> of the virtual address associated with an exception.
+      Holds bits [VSXLEN-1:<%= ext?(:C) ? 2 : 1 %>] of the virtual address associated with an exception.
     type: RW-RH
     sw_write(csr_value): |
       return csr_value.PC & ~64'b1;
     reset_value: UNDEFINED_LEGAL
 sw_read(): |
   if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
-    return CSR[sepc].PC & ~64'b1;
+    return CSR[vsepc].PC & ~64'b1;
   } else {
-    return CSR[sepc].PC;
+    return CSR[vsepc].PC;
   }

data/.data/spec/std/isa/csr/vstval.yaml

@@ -11,7 +11,7 @@ address: 0x243
 writable: true
 virtual_address: 0x143
 description: Holds trap-specific information
-priv_mode: S
+priv_mode: VS
 length: VSXLEN
 definedBy:
   extension: