udb 0.1.14 → 0.1.16

data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsbu
+long_name: Load scaled indexed byte unsigned
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to XLEN.
+
+  The `lxbu` mnemonic is an assembler pseudoinstruction for `lxsbu`.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------100-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+pseudoinstructions:
+  - when: "true"
+    to: lxbu xd, (xs2), xs1
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(8, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsd.yaml

@@ -0,0 +1,38 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsd
+long_name: Load scaled indexed doubleword
+description: |
+  Load 64 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 3)`, where `xs2` is the base and `xs1` is the index.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------011-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 3);
+
+  X[xd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsh.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsh
+long_name: Load scaled indexed halfword
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 1)`, where `xs2` is the base and `xs1` is the index.
+  Sign extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------001-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 1);
+
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/std/isa/inst/Zilx/lxshu.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxshu
+long_name: Load scaled indexed halfword unsigned
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 1)`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------101-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 1);
+
+  X[xd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwb
+long_name: Load scaled indexed byte with unsigned word index
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + zext32(X[xs1])`, where `xs2` is the base and `xs1` is the index.
+  The index is zero-extended from `X[xs1][31:0]` before forming the address.
+  Sign extend the loaded byte to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------000-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1][31:0];
+
+  X[xd] = sext(read_memory(8, virtual_address, $encoding), 8);

data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwbu
+long_name: Load scaled indexed byte unsigned with unsigned word index
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + zext32(X[xs1])`, where `xs2` is the base and `xs1` is the index.
+  The index is zero-extended from `X[xs1][31:0]` before forming the address.
+  Zero extend the loaded byte to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------100-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1][31:0];
+
+  X[xd] = read_memory(8, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwd
+long_name: Load scaled indexed doubleword with unsigned word index
+description: |
+  Load 64 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 3)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------011-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 3);
+
+  X[xd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwh
+long_name: Load scaled indexed halfword with unsigned word index
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 1)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Sign extend the loaded halfword to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------001-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 1);
+
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwhu
+long_name: Load scaled indexed halfword unsigned with unsigned word index
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 1)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Zero extend the loaded halfword to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------101-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 1);
+
+  X[xd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuww
+long_name: Load scaled indexed word with unsigned word index
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 2)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Sign extend the loaded word to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------010-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 2);
+
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwwu
+long_name: Load scaled indexed word unsigned with unsigned word index
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 2)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Zero extend the loaded word to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------110-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 2);
+
+  X[xd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsw.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsw
+long_name: Load scaled indexed word
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 2)`, where `xs2` is the base and `xs1` is the index.
+  On RV64, the loaded word is sign-extended to 64 bits.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------010-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 2);
+
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/Zilx/lxswu.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxswu
+long_name: Load scaled indexed word unsigned
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 2)`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------110-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 2);
+
+  X[xd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxw.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxw
+long_name: Load indexed word
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  On RV64, the loaded word is sign-extended to 64 bits.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------010-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/Zilx/lxwu.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxwu
+long_name: Load indexed word unsigned
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------110-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zimop/mop.r.28.yaml

@@ -33,8 +33,7 @@ access:
   vu: always
 data_independent_timing: false
 hints:
-  - { $ref: inst/Zicfiss/sspopchk.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspopchk.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspopchk.yaml# }
   - { $ref: inst/Zicfiss/ssrdp.yaml# }
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/Zimop/mop.r.N.layout

@@ -50,8 +50,7 @@ access:
 data_independent_timing: false
 <% if n == 28 -%>
 hints:
-  - { $ref: inst/Zicfiss/sspopchk.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspopchk.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspopchk.yaml# }
   - { $ref: inst/Zicfiss/ssrdp.yaml# }
 <% end -%>
 operation(): |

data/.data/spec/std/isa/inst/Zimop/mop.rr.7.yaml

@@ -36,7 +36,6 @@ access:
   vu: always
 data_independent_timing: false
 hints:
-  - { $ref: inst/Zicfiss/sspush.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspush.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspush.yaml# }
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/Zimop/mop.rr.N.layout

@@ -51,8 +51,7 @@ access:
 data_independent_timing: false
 <% if n == 7 -%>
 hints:
-  - { $ref: inst/Zicfiss/sspush.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspush.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspush.yaml# }
 <% end -%>
 operation(): |
   X[xd] = 0;