udb 0.1.14 → 0.1.16

data/.data/spec/std/isa/inst/{Q → Zfa}/fltq.q.yaml

@@ -13,13 +13,12 @@ description: |
 
   `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid
   operation exception flag to be set.
-  This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:
       - name: Q
       - name: Zfa
-assembly: fd, fs1, fs2
+assembly: xd, fs1, fs2
 encoding:
   match: 1010011----------101-----1010011
   variables:
@@ -27,7 +26,7 @@ encoding:
       location: 24-20
     - name: fs1
       location: 19-15
-    - name: fd
+    - name: xd
       location: 11-7
 access:
   s: always

data/.data/spec/std/isa/inst/{F → Zfa}/fltq.s.yaml

@@ -28,7 +28,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/{Q → Zfa}/fmaxm.q.yaml

@@ -13,7 +13,6 @@ description: |
   If both inputs are _NaN_s, the result is the canonical _NaN_.
   If either input is _NaN_, the result is the canonical _NaN_.
   Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml

@@ -27,5 +27,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/{Q → Zfa}/fminm.q.yaml

@@ -13,7 +13,6 @@ description: |
   If both inputs are _NaN_s, the result is the canonical _NaN_.
   If either input is _NaN_, the result is the canonical _NaN_.
   Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml

@@ -27,5 +27,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/{Q → Zfa}/fmvp.q.x.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: fmvp.q.x
 long_name: Floating-Point Move Pair from Integer Registers to Quad-Precision Register
 description: |
-  The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into
+  The `fmvp.q.x` instruction moves a quad-precision number from a pair of integer registers into
   a floating-point register.
   Integer registers `xs1` and `xs2` supply bits 63:0 and 127:64, respectively; the result is written to
   floating-point register `fd`.

data/.data/spec/std/isa/inst/Zfa/fround.s.yaml

@@ -33,7 +33,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml

@@ -27,5 +27,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/Zfh/flh.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: flh
 long_name: Half-precision floating-point load
 description: |
-  The `flh` instruction loads a single-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _xd_.
+  The `flh` instruction loads a half-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _xd_.
 
   `flh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
 
@@ -16,13 +16,16 @@ description: |
 
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: fd, imm(xs1)
 encoding:
   match: "-----------------001-----0000111"
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fd

data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml

@@ -14,7 +14,9 @@ description: |
   the payloads of non-canonical NaNs are preserved.
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: fd, xs1
 encoding:
   match: 111101000000-----000-----1010011

data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml

@@ -9,7 +9,9 @@ name: fmv.x.h
 long_name: Move half-precision value from floating-point to integer register
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: xd, fs1
 description: |
   Moves the half-precision value in floating-point register fs1 represented in IEEE 754-2008

data/.data/spec/std/isa/inst/Zfh/fsh.yaml

@@ -19,13 +19,16 @@ description: |
 
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: fs2, imm(xs1)
 encoding:
   match: "-----------------001-----0100111"
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fs2

data/.data/spec/std/isa/inst/Zibi/beqi.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: beqi
+long_name: Branch if equal immediate
+description: |
+  Branch to PC + offset if the value in register xs1 is equal to the XLEN-bit
+  comparison constant decoded from cimm.
+
+  The cimm field is not sign-extended: cimm == 0 encodes the value -1, and
+  cimm values 1 through 31 encode the corresponding positive integer values.
+
+  Raise a `MisalignedAddress` exception if the branch is taken and PC + offset is
+  misaligned.
+definedBy:
+  extension:
+    name: Zibi
+assembly: xs1, cimm, offset
+encoding:
+  match: "-----------------010-----1100011"
+  variables:
+    - name: offset
+      location: 31|7|30-25|11-8
+      left_shift: 1
+      sign_extend: true
+    - name: cimm
+      location: 24-20
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg lhs = X[xs1];
+  XReg rhs = (cimm == 0) ? {MXLEN{1'b1}} : cimm;
+
+  if (lhs == rhs) {
+    jump_halfword($pc + $signed(offset));
+  }

data/.data/spec/std/isa/inst/Zibi/bnei.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: bnei
+long_name: Branch if not equal immediate
+description: |
+  Branch to PC + offset if the value in register xs1 is not equal to the XLEN-bit
+  comparison constant decoded from cimm.
+
+  The cimm field is not sign-extended: cimm == 0 encodes the value -1, and
+  cimm values 1 through 31 encode the corresponding positive integer values.
+
+  Raise a `MisalignedAddress` exception if the branch is taken and PC + offset is
+  misaligned.
+definedBy:
+  extension:
+    name: Zibi
+assembly: xs1, cimm, offset
+encoding:
+  match: "-----------------011-----1100011"
+  variables:
+    - name: offset
+      location: 31|7|30-25|11-8
+      left_shift: 1
+      sign_extend: true
+    - name: cimm
+      location: 24-20
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg lhs = X[xs1];
+  XReg rhs = (cimm == 0) ? {MXLEN{1'b1}} : cimm;
+
+  if (lhs != rhs) {
+    jump_halfword($pc + $signed(offset));
+  }

data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml

@@ -52,7 +52,7 @@ description: |
   `cbo.inval` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
   <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
-  Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
+  Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.inval` has UNSPECIFIED behavior.
   <%- end -%>
 
   Invalidate operations are treated as stores for page and access permissions. If permission checks fail,

data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: c.sspopchk
+long_name: Compressed Shadow Stack Pop and Check
+description: |
+  C.SSPOPCHK pops a value from the shadow stack and checks it against link
+  register `x5`.
+
+  This instruction uses the `c.mop.5` codepoint provided by Zcmop and expands
+  to `sspopchk x5`.
+definedBy:
+  extension:
+    allOf:
+      - name: Zicfiss
+      - name: Zcmop
+assembly: x5
+encoding:
+  match: "0110001010000001"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: c.sspush
+long_name: Compressed Shadow Stack Push
+description: |
+  C.SSPUSH pushes link register `x1` to the shadow stack.
+
+  This instruction uses the `c.mop.1` codepoint provided by Zcmop and expands
+  to `sspush x1`.
+definedBy:
+  extension:
+    allOf:
+      - name: Zicfiss
+      - name: Zcmop
+assembly: x1
+encoding:
+  match: "0110000010000001"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.d.yaml

@@ -12,7 +12,7 @@ description: |
 definedBy:
   extension:
     name: Zicfiss
-assembly: xd, xs2, xs1
+assembly: xd, xs2, (xs1)
 encoding:
   match: 01001------------011-----0101111
   variables:

data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.w.yaml

@@ -12,7 +12,7 @@ description: |
 definedBy:
   extension:
     name: Zicfiss
-assembly: xd, xs2, xs1
+assembly: xd, xs2, (xs1)
 encoding:
   match: 01001------------010-----0101111
   variables:

data/.data/spec/std/isa/inst/Zicfiss/sspopchk.yaml

@@ -0,0 +1,63 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspopchk
+long_name: Shadow Stack Pop and Check
+description: |
+  SSPOPCHK pops a value from the shadow stack and checks it against link
+  register `xs1`. The encoding restricts `xs1` to `x1` or `x5`.
+
+  This instruction uses the `mop.r.28` codepoint provided by Zimop.
+definedBy:
+  extension:
+    name: Zicfiss
+assembly: xs1
+encoding:
+  match: "110011011100-----100000001110011"
+  variables:
+    - name: xs1
+      location: 19-15
+      not:
+        [
+          0,
+          2,
+          3,
+          4,
+          6,
+          7,
+          8,
+          9,
+          10,
+          11,
+          12,
+          13,
+          14,
+          15,
+          16,
+          17,
+          18,
+          19,
+          20,
+          21,
+          22,
+          23,
+          24,
+          25,
+          26,
+          27,
+          28,
+          29,
+          30,
+          31,
+        ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicfiss/sspush.yaml

@@ -0,0 +1,63 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspush
+long_name: Shadow Stack Push
+description: |
+  SSPUSH pushes the value of link register `xs2` to the shadow stack.
+  The encoding restricts `xs2` to `x1` or `x5`.
+
+  This instruction uses the `mop.rr.7` codepoint provided by Zimop.
+definedBy:
+  extension:
+    name: Zicfiss
+assembly: xs2
+encoding:
+  match: "1100111-----00000100000001110011"
+  variables:
+    - name: xs2
+      location: 24-20
+      not:
+        [
+          0,
+          2,
+          3,
+          4,
+          6,
+          7,
+          8,
+          9,
+          10,
+          11,
+          12,
+          13,
+          14,
+          15,
+          16,
+          17,
+          18,
+          19,
+          20,
+          21,
+          22,
+          23,
+          24,
+          25,
+          26,
+          27,
+          28,
+          29,
+          30,
+          31,
+        ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml

@@ -30,6 +30,6 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   X[xd] = (X[xs2] == 0) ? 0 : X[xs1];

data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml

@@ -30,6 +30,6 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   X[xd] = (X[xs2] != 0) ? 0 : X[xs1];

data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml

@@ -34,6 +34,18 @@ access:
   vs: always
   vu: always
 pseudoinstructions:
+  - when: xd == 0 && csr == 0x001
+    to: fsflags xs1
+  - when: xd == 0 && csr == 0x002
+    to: fsrm xs1
+  - when: xd == 0 && csr == 0x003
+    to: fscsr xs1
+  - when: csr == 0x001
+    to: fsflags xd, xs1
+  - when: csr == 0x002
+    to: fsrm xd, xs1
+  - when: csr == 0x003
+    to: fscsr xd, xs1
   - when: xd == 0
     to: csrw csr, xs1
 operation(): |

data/.data/spec/std/isa/inst/Zilx/lxd.yaml

@@ -0,0 +1,38 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxd
+long_name: Load indexed doubleword
+description: |
+  Load 64 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------011-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxh.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxh
+long_name: Load indexed halfword
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Sign extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------001-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/std/isa/inst/Zilx/lxhu.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxhu
+long_name: Load indexed halfword unsigned
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------101-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsb.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsb
+long_name: Load scaled indexed byte
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Sign extend the result to XLEN.
+
+  The `lxb` mnemonic is an assembler pseudoinstruction for `lxsb`.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------000-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+pseudoinstructions:
+  - when: "true"
+    to: lxb xd, (xs2), xs1
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = sext(read_memory(8, virtual_address, $encoding), 8);