axi_tdl 0.1.1 → 0.1.3
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- checksums.yaml +4 -4
- data/Rakefile +7 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.sv +2 -2
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +46 -9
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
- data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
- data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -4
- data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
- data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
- data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
- data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +17 -47
- data/lib/tdl/elements/parameter.rb +5 -6
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
- data/lib/tdl/examples/8_top_module/dve.tcl +2 -155
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +2 -155
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +3 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_tttop.sv +1 -1
- data/lib/tdl/exlib/axis_verify.rb +4 -3
- data/lib/tdl/rebuild_ele/ele_base.rb +8 -8
- data/lib/tdl/sdlmodule/sdlmodule.rb +61 -51
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +5 -0
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +34 -3
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -63,7 +63,7 @@ module ClassHDL
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str.push op.instance(:always_ff).gsub(/^./){ |m| " #{m}"}
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else
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unless op.slaver
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rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
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rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff, belong_to_module))
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str.push " #{rel_str};"
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end
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end
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@@ -143,7 +143,7 @@ module ClassHDL
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str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
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else
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unless op.slaver
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
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str.push " #{rel_str};"
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end
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end
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@@ -8,14 +8,20 @@ module ClassHDL
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def initialize(belong_to_module)
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@opertor_chains = []
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@belong_to_module = belong_to_module
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unless @belong_to_module
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raise TdlError.new("HDLAssignBlock must have belong_to_module")
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end
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end
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def instance
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unless @belong_to_module.is_a?(SdlModule)
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raise TdlError.new("HDLAssignBlock must have belong_to_module")
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end
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str = []
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opertor_chains.each do |op|
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unless op.slaver
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sub_str = op.instance(:assign)
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sub_str = op.instance(:assign,belong_to_module)
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# if sub_str =~ /^(?<head>[\w\.\[\]\:]+\s*)(?<eq><?=\s*)\((?<body>.+)\)$/
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# rel_str = $~[:head] + $~[:eq] + $~[:body]
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# else
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@@ -11,7 +11,7 @@ module ClassHDL
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def instance(as_type= :cond)
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if cond.is_a? ClassHDL::OpertorChain
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head_str = "if(#{cond.instance(:cond)})begin"
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head_str = "if(#{cond.instance(:cond, belong_to_module)})begin"
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else
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head_str = "if(#{cond.to_s})begin"
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end
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opertor_chains.each do |oc|
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unless oc.is_a? BlockIF
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unless oc.slaver
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rel_str = ClassHDL.compact_op_ch(oc.instance(as_type))
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rel_str = ClassHDL.compact_op_ch(oc.instance(as_type, belong_to_module))
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sub_str.push " #{rel_str};"
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end
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else
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class BlockELSIF < BlockIF
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def instance(as_type= :cond)
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if cond.is_a? ClassHDL::OpertorChain
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head_str = "else if(#{cond.instance(:cond)})begin"
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head_str = "else if(#{cond.instance(:cond, belong_to_module)})begin"
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else
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head_str = "else if(#{cond.to_s})begin"
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end
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opertor_chains.each do |oc|
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unless oc.is_a? BlockIF
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unless oc.slaver
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sub_str.push " #{oc.instance(as_type)};"
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sub_str.push " #{oc.instance(as_type, belong_to_module)};"
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end
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else
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sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
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opertor_chains.each do |oc|
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unless oc.is_a? BlockIF
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unless oc.slaver
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sub_str.push " #{oc.instance(as_type)};"
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sub_str.push " #{oc.instance(as_type, belong_to_module)};"
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end
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else
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sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
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opertor_chains.each do |oc|
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unless oc.is_a? BlockIF
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unless oc.slaver
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sub_str.push " #{oc.instance(as_type)};"
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sub_str.push " #{oc.instance(as_type, belong_to_module)};"
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end
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else
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sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
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unless oc.is_a? BlockIF
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sub_str.push " #{oc.instance(as_type)};"
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sub_str.push " #{oc.instance(as_type, belong_to_module)};"
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end
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else
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sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
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opertor_chains.each do |oc|
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unless oc.is_a? BlockIF
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unless oc.slaver
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sub_str.push " #{oc.instance(as_type)};"
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sub_str.push " #{oc.instance(as_type, belong_to_module)};"
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end
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else
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sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
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opertor_chains.each do |oc|
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unless oc.is_a? BlockIF
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unless oc.slaver
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sub_str.push " #{oc.instance(as_type)};"
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sub_str.push " #{oc.instance(as_type,belong_to_module)};"
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end
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else
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sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
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@@ -13,7 +13,7 @@ module ClassHDL
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if @func_inst.return_type.is_a? StructMeta
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@func_inst.return_type.struct_slots.each do |e|
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self.define_singleton_method(e.name) do
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TdlSpace::ArrayChain.
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TdlSpace::ArrayChain.create(obj: "#{@func_inst.name}.#{e.name}".to_nq, belong_to_module: @func_inst.belong_to_module )
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end
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end
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end
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@@ -90,7 +90,7 @@ module ClassHDL
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str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
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else
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unless op.slaver
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
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str.push " #{rel_str};"
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end
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end
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@@ -193,7 +193,7 @@ module ClassHDL
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# pin,iostd = parse_pin_prop(pin_prop) if pin_prop
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# RedefOpertor.with_normal_operators do
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ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
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tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self)
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# add_to_new_module("@port_logics",tmp)
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# add_method_to_itgt(name,tmp)
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tmp
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@@ -205,7 +205,7 @@ module ClassHDL
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# pin,iostd = parse_pin_prop(pin_prop) if pin_prop
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# RedefOpertor.with_normal_operators do
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ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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tmp = Logic.new(name:name,dsize:dsize,port:"output logic",dimension:dimension)
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tmp = Logic.new(name:name,dsize:dsize,port:"output logic",dimension:dimension, belong_to_module: self)
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# add_to_new_module("@port_logics",tmp)
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if block_given?
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@@ -20,6 +20,9 @@ module ClassHDL
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def initialize(belong_to_module)
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@belong_to_module = belong_to_module
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super("genblk#{globle_random_name_flag()}")
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unless @belong_to_module
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raise TdlError.new("GenerateBlock must have belong_to_module")
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end
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end
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@@ -41,7 +44,7 @@ module ClassHDL
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def IF(cond,&block)
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if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? HDLAssignGenerateBlock
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if cond.respond_to?(:instance)
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-
head_str = "\nif(#{cond.instance(:cond)})begin\n"
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head_str = "\nif(#{cond.instance(:cond, @belong_to_module)})begin\n"
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else
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head_str = "\nif(#{cond})begin\n"
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end
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@@ -7,6 +7,9 @@ module ClassHDL
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def initialize(belong_to_module)
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@opertor_chains = []
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@belong_to_module = belong_to_module
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unless @belong_to_module
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raise TdlError.new("HDLInitialBlock must have belong_to_module")
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end
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end
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def instance(block_name=nil)
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@@ -17,7 +20,26 @@ module ClassHDL
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str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
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else
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unless op.slaver
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
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str.push " #{rel_str};"
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end
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end
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end
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str.push "end\n"
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str.join("\n")
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end
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def instance_inspect()
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str = []
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block_name=nil
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str.push "initial begin#{block_name ? ':'.concat(block_name.to_s) : ''}"
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opertor_chains.each do |op|
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unless op.is_a? OpertorChain
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str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
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else
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unless op.slaver
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
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str.push " #{rel_str};"
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end
|
23
45
|
end
|
@@ -41,7 +63,7 @@ module ClassHDL
|
|
41
63
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class BlocAssertIF < BlockIF
|
42
64
|
def instance(as_type= :cond)
|
43
65
|
if cond.is_a? ClassHDL::OpertorChain
|
44
|
-
head_str = "assert(#{cond.instance(:cond)})else begin"
|
66
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+
head_str = "assert(#{cond.instance(:cond, belong_to_module)})else begin"
|
45
67
|
else
|
46
68
|
head_str = "assert(#{cond.to_s})else begin"
|
47
69
|
end
|
@@ -50,7 +72,7 @@ module ClassHDL
|
|
50
72
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opertor_chains.each do |oc|
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51
73
|
unless oc.is_a? BlockIF
|
52
74
|
unless oc.slaver
|
53
|
-
sub_str.push " #{oc.instance(as_type)};"
|
75
|
+
sub_str.push " #{oc.instance(as_type,belong_to_module)};"
|
54
76
|
end
|
55
77
|
else
|
56
78
|
sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
|
@@ -170,6 +170,9 @@ module ClassHDL
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def initialize(sdlm,args={})
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@chain = []
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@sdlm = sdlm
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+
unless @sdlm
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+
raise TdlError.new("ImplicitPortBase<#{args.to_s}> dont have belong_to_module")
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+
end
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|
@up_args = args
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|
end
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175
178
|
|
@@ -298,7 +301,7 @@ module ClassHDL
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if sub_type.is_a? StructMeta
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@sub_type.struct_slots.each do |e|
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obj.define_singleton_method(e.name) do
|
301
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-
TdlSpace::ArrayChain.
|
304
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+
TdlSpace::ArrayChain.create(obj: "#{obj.name}.#{e.name}".to_nq, belong_to_module: obj.belong_to_module)
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|
end
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end
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end
|
@@ -380,27 +383,27 @@ class SdlModule
|
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380
383
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|
381
384
|
def >>(*args)
|
382
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|
str = "{>>{#{args.map{|e| e.to_s }.join(',')}}}"
|
383
|
-
TdlSpace::ArrayChain.
|
386
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
384
387
|
end
|
385
388
|
|
386
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|
def <<(*args)
|
387
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|
str = "{<<{#{args.map{|e| e.to_s }.join(',')}}}"
|
388
|
-
TdlSpace::ArrayChain.
|
391
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
389
392
|
end
|
390
393
|
|
391
394
|
def logic_bind_(*args)
|
392
395
|
str = "{#{args.map{|e| e.to_s }.join(',')}}"
|
393
|
-
TdlSpace::ArrayChain.
|
396
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
394
397
|
end
|
395
398
|
|
396
399
|
def clog2(arg)
|
397
400
|
str = "$clog2(#{arg.to_s})"
|
398
|
-
TdlSpace::ArrayChain.
|
401
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
399
402
|
end
|
400
403
|
|
401
404
|
def bits(arg)
|
402
405
|
str = "$bits(#{arg.to_s})"
|
403
|
-
TdlSpace::ArrayChain.
|
406
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
404
407
|
end
|
405
408
|
|
406
409
|
end
|
@@ -90,6 +90,51 @@ module ClassHDL
|
|
90
90
|
return str
|
91
91
|
end
|
92
92
|
|
93
|
+
def build_module_verb(ex_param: "",ex_port: "",ex_up_code: "",ex_down_code: "")
|
94
|
+
# Tdl.Puts pagination(module_name)
|
95
|
+
Tdl.Build_SdlModule_Puts(module_name)
|
96
|
+
|
97
|
+
ex_param = ex_param.to_s unless ex_param
|
98
|
+
ex_port = ex_port.to_s unless ex_port
|
99
|
+
ex_up_code = ex_up_code.to_s unless ex_up_code
|
100
|
+
ex_down_code = ex_down_code.to_s unless ex_down_code
|
101
|
+
|
102
|
+
# gen_auto_method # auto generate class method for interface
|
103
|
+
# draw = Tdl.inst + Tdl.draw
|
104
|
+
|
105
|
+
instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst
|
106
|
+
vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec
|
107
|
+
|
108
|
+
post_str = post_inst_stack_call()
|
109
|
+
|
110
|
+
unless post_str.strip.empty?
|
111
|
+
post_str = pagination("ROOT REF") + post_str
|
112
|
+
end
|
113
|
+
|
114
|
+
draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
|
115
|
+
|
116
|
+
unless ex_up_code.empty?
|
117
|
+
ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
|
118
|
+
end
|
119
|
+
|
120
|
+
unless ex_down_code.empty?
|
121
|
+
ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
|
122
|
+
end
|
123
|
+
|
124
|
+
|
125
|
+
module_name_str = @module_name
|
126
|
+
|
127
|
+
|
128
|
+
# str = module_head+"package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
|
129
|
+
str = "package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
|
130
|
+
|
131
|
+
create_vivado_tcl if @create_tcl
|
132
|
+
create_constraints_file if @create_sdc
|
133
|
+
|
134
|
+
return [module_head_verb,str]
|
135
|
+
end
|
136
|
+
|
137
|
+
|
93
138
|
end
|
94
139
|
|
95
140
|
# class ReqPakcgeLine
|
@@ -47,6 +47,20 @@ module ClassHDL
|
|
47
47
|
@tree << arg
|
48
48
|
end
|
49
49
|
@belong_to_module = belong_to_module
|
50
|
+
unless @belong_to_module
|
51
|
+
raise TdlError.new("OpertorChain must have belong_to_module")
|
52
|
+
end
|
53
|
+
end
|
54
|
+
|
55
|
+
def instance_inspect
|
56
|
+
str = ["self belong_to_module:#{belong_to_module.module_name}"]
|
57
|
+
index = 0
|
58
|
+
@tree.each do |node|
|
59
|
+
bl = "#{node[0].respond_to?(:belong_to_module) ? "belong_to_module:#{node[0].belong_to_module.module_name }" : '' }"
|
60
|
+
str << "{{ tree[#{index}][1]node[1]SYMB{#{node[1].to_s}} tree[#{index}][0]node[0]#{node[0].to_s} #{node[0].class} #{bl}}}"
|
61
|
+
index += 1
|
62
|
+
end
|
63
|
+
str.join(" ")
|
50
64
|
end
|
51
65
|
|
52
66
|
ClassHDL::OP_SYMBOLS.each do |os|
|
@@ -103,17 +117,20 @@ module ClassHDL
|
|
103
117
|
# self.nege = true
|
104
118
|
# return self
|
105
119
|
self.slaver = true
|
106
|
-
|
120
|
+
bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
121
|
+
new_op = OpertorChain.new(["~(#{self.instance(:assign, bel)})".to_nq])
|
107
122
|
end
|
108
123
|
|
109
124
|
def brackets
|
110
125
|
self.slaver = true
|
111
|
-
|
126
|
+
bel = ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
127
|
+
new_op = OpertorChain.new(["(#{self.instance(:assign, belong_to_module || bel)})".to_nq], belong_to_module)
|
112
128
|
end
|
113
129
|
|
114
130
|
def clog2
|
115
131
|
self.slaver = true
|
116
|
-
|
132
|
+
bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
133
|
+
new_op = OpertorChain.new(["$clog2(#{self.instance(:aasign, bel)})".to_nq],belong_to_module)
|
117
134
|
end
|
118
135
|
|
119
136
|
def self.define_op_flag(ruby_op,hdl_op)
|
@@ -143,10 +160,13 @@ module ClassHDL
|
|
143
160
|
|
144
161
|
|
145
162
|
def to_s
|
146
|
-
instance(type=:cond)
|
163
|
+
instance(type=:cond,belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module ) )
|
147
164
|
end
|
148
165
|
|
149
|
-
def instance(type=:assign)
|
166
|
+
def instance(type=:assign,block_belong_to_module=nil,show=nil)
|
167
|
+
unless block_belong_to_module
|
168
|
+
raise TdlError.new("OpertorChain must has block_belong_to_module")
|
169
|
+
end
|
150
170
|
AssignDefOpertor.with_rollback_opertors(:old) do
|
151
171
|
str = ''
|
152
172
|
# both_symb_used = false
|
@@ -160,39 +180,75 @@ module ClassHDL
|
|
160
180
|
sb = " = "
|
161
181
|
end
|
162
182
|
else
|
163
|
-
|
164
|
-
|
165
|
-
# else
|
166
|
-
sb = "#{node[1].to_s}"
|
167
|
-
# end
|
183
|
+
|
184
|
+
sb = "#{node[1].to_s}"
|
168
185
|
end
|
169
186
|
else
|
170
|
-
|
171
|
-
|
172
|
-
|
173
|
-
|
174
|
-
#
|
187
|
+
sb = "#{node[1].to_s}"
|
188
|
+
end
|
189
|
+
|
190
|
+
if cnt==1 && show
|
191
|
+
puts "tree[1][1]<#{node[1]}> 使用 #{sb}"
|
175
192
|
end
|
176
193
|
|
177
194
|
unless node[0].is_a? OpertorChain
|
178
195
|
## 判断是不是属于 Var <= "String" 形式
|
179
196
|
if (@tree.length == 2) && node[0].instance_of?(String) && !@slaver
|
180
197
|
str += (sb + '"' + node[0].to_s + '"')
|
198
|
+
if show
|
199
|
+
puts "tree 长度等于2; tree[#{cnt}][0] is string; op is not slaver"
|
200
|
+
end
|
181
201
|
elsif node[0].instance_of?(String)
|
182
202
|
# "如果是字符串 则原始输出"
|
183
203
|
str += (sb + '"' + node[0].to_s + '"')
|
204
|
+
if show
|
205
|
+
puts "tree[#{cnt}][0] is string"
|
206
|
+
end
|
184
207
|
else
|
185
208
|
# str += (sb + node[0].to_s)
|
186
|
-
if
|
209
|
+
if block_belong_to_module
|
210
|
+
if (node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != block_belong_to_module) && node[0].belong_to_module.top_tb_ref? )
|
211
|
+
|
212
|
+
str += (sb + node[0].root_ref)
|
213
|
+
|
214
|
+
if show
|
215
|
+
puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != block_belong_to_module<#{block_belong_to_module.module_name}>"
|
216
|
+
end
|
217
|
+
## 反向添加到 TestUnitModule
|
218
|
+
if block_belong_to_module.is_a?(TestUnitModule)
|
219
|
+
block_belong_to_module.add_root_ref_ele(node[0])
|
220
|
+
if show
|
221
|
+
puts "block_belong_to_module<#{block_belong_to_module.module_name}> is TestUnitModule"
|
222
|
+
end
|
223
|
+
end
|
224
|
+
else
|
225
|
+
str += (sb + node[0].to_s)
|
226
|
+
if show
|
227
|
+
mmm = node[0].respond_to?(:belong_to_module) && node[0].belong_to_module.module_name
|
228
|
+
puts "tree[#{cnt}][0]<#{node[0].class}>: ref_root<#{node[0].respond_to?(:root_ref).to_s}> belong_to_module<#{mmm}> block_belong_to_module<#{block_belong_to_module.module_name}> ...."
|
229
|
+
end
|
230
|
+
end
|
231
|
+
elsif(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
|
187
232
|
# sb = "#{node[1].root_ref.to_s}"
|
188
233
|
str += (sb + node[0].root_ref)
|
234
|
+
|
235
|
+
if show
|
236
|
+
puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != op.belong_to_module<#{belong_to_module.module_name}>"
|
237
|
+
end
|
238
|
+
|
189
239
|
## 反向添加到 TestUnitModule
|
190
240
|
if belong_to_module.is_a?(TestUnitModule)
|
191
241
|
belong_to_module.add_root_ref_ele(node[0])
|
242
|
+
if show
|
243
|
+
puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> is TestUnitModule"
|
244
|
+
end
|
192
245
|
end
|
193
246
|
else
|
194
247
|
# sb = "#{node[1].to_s}"
|
195
248
|
str += (sb + node[0].to_s)
|
249
|
+
if show
|
250
|
+
puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> ..."
|
251
|
+
end
|
196
252
|
end
|
197
253
|
end
|
198
254
|
else
|
@@ -203,13 +259,17 @@ module ClassHDL
|
|
203
259
|
# if node[0].tree.length>2 && ["&","|","<",">"].include?(node[0].tree[1][1])
|
204
260
|
|
205
261
|
# else
|
262
|
+
|
206
263
|
if sb =~/(\||&){2,2}/
|
207
|
-
str += " #{sb}#{node[0].instance(:slaver).to_s}"
|
264
|
+
str += " #{sb}#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s}"
|
208
265
|
else
|
209
|
-
str += "#{sb}(#{node[0].instance(:slaver).to_s})"
|
266
|
+
str += "#{sb}(#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s})"
|
210
267
|
end
|
211
|
-
|
212
|
-
|
268
|
+
|
269
|
+
if show
|
270
|
+
puts "tree[#{cnt}][0] is op, block_belong_to_module<#{block_belong_to_module.to_s}> op.belong_to_module<#{belong_to_module.to_s}>"
|
271
|
+
end
|
272
|
+
|
213
273
|
end
|
214
274
|
cnt += 1
|
215
275
|
end
|
@@ -235,8 +295,10 @@ module ClassHDL
|
|
235
295
|
|
236
296
|
module AssignDefOpertor
|
237
297
|
@@included_class = []
|
238
|
-
@@curr_assign_block = HDLAssignBlock.new(
|
239
|
-
@@
|
298
|
+
@@curr_assign_block = HDLAssignBlock.new(true) ##HDLAssignBlock ##HDLAlwaysCombBlock
|
299
|
+
# @@curr_assign_block = nil
|
300
|
+
@@curr_assign_block_stack = [HDLAssignBlock.new(true) ]
|
301
|
+
# @@curr_assign_block_stack = []
|
240
302
|
@@curr_opertor_stack = [:old]
|
241
303
|
|
242
304
|
def self.curr_opertor_stack
|
@@ -296,7 +358,18 @@ module ClassHDL
|
|
296
358
|
b.slaver = true
|
297
359
|
end
|
298
360
|
## 当 进行 X < Y 等运算时OpertorChain 需要获取 assign block的 belong_to_module
|
299
|
-
|
361
|
+
if @@curr_assign_block
|
362
|
+
bblm = @@curr_assign_block.belong_to_module
|
363
|
+
elsif self.respond_to?(:belong_to_module)
|
364
|
+
bblm = self.belong_to_module
|
365
|
+
elsif b.respond_to?(:belong_to_module)
|
366
|
+
bblm = b.belong_to_module
|
367
|
+
|
368
|
+
else
|
369
|
+
bblm = nil
|
370
|
+
end
|
371
|
+
|
372
|
+
new_op = OpertorChain.new(nil, bblm)
|
300
373
|
new_op.tree.push([self])
|
301
374
|
new_op.tree.push([b,symb])
|
302
375
|
if @@curr_assign_block
|
@@ -511,7 +584,7 @@ class BaseElm
|
|
511
584
|
|
512
585
|
@_array_chain_hash_[name.to_s] = rel
|
513
586
|
end
|
514
|
-
TdlSpace::ArrayChain.
|
587
|
+
TdlSpace::ArrayChain.create(obj: @_array_chain_hash_[name.to_s], lchain:[], belong_to_module: self.belong_to_module)
|
515
588
|
end
|
516
589
|
end
|
517
590
|
end
|
@@ -576,9 +649,8 @@ module TdlSpace
|
|
576
649
|
end
|
577
650
|
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
578
651
|
unless b
|
579
|
-
ArrayChain.
|
652
|
+
ArrayChain.create(obj: obj,lchain: chain+[a],belong_to_module: belong_to_module)
|
580
653
|
else
|
581
|
-
# ArrayChain.new(&obj,chain,[a,b])
|
582
654
|
@end_slice = [a,b]
|
583
655
|
self
|
584
656
|
end
|
@@ -610,7 +682,7 @@ module TdlSpace
|
|
610
682
|
end
|
611
683
|
|
612
684
|
def ~
|
613
|
-
ArrayChain.
|
685
|
+
ArrayChain.create(obj: "~#{self.to_s}", belong_to_module: belong_to_module)
|
614
686
|
end
|
615
687
|
end
|
616
688
|
end
|