axi_tdl 0.1.1 → 0.1.3

data/lib/tdl/examples/8_top_module/test_top.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-03-21 23:51:36 +0800
+created: 2021-04-03 13:14:45 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/9_itegration/dve.tcl

@@ -12,128 +12,6 @@ gui_set_time_units 1ps
 ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
 ## ==== [add_signal] ===== ##
 
-## -------------- sub_md0_logic -------------------------
-set _wave_session_group_sub_md0_logic sub_md0_logic
-# set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
-    set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
-}
-set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt}  }
-## ============== sub_md0_logic =========================
-        
-
-## -------------- sub_md0_interface -------------------------
-set _wave_session_group_sub_md0_interface sub_md0_interface
-# set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
-    set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
-}
-set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in}  }
-## ============== sub_md0_interface =========================
-        
-
-## -------------- sub_md0_default -------------------------
-set _wave_session_group_sub_md0_default sub_md0_default
-# set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
-    set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
-}
-set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" {  }
-## ============== sub_md0_default =========================
-        
-
-## -------------- sub_md0_default.inter_tf -------------------------
-## set _wave_session_group_sub_md0_default_inter_tf Group1
-## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
-
-set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
-append _wave_session_group_sub_md0_default_inter_tf inter_tf
-set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
-
-# set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" {  {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf}  }  
-## ============== sub_md0_default.inter_tf =========================
-        
-
-## -------------- sub_md1_default -------------------------
-set _wave_session_group_sub_md1_default sub_md1_default
-# set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
-    set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
-}
-set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" {  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt}  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out}  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable}  }
-## ============== sub_md1_default =========================
-        
-
-## -------------- sub_md1_inner -------------------------
-set _wave_session_group_sub_md1_inner sub_md1_inner
-# set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
-if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
-    set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
-}
-set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" {  }
-## ============== sub_md1_inner =========================
-        
-
-## -------------- sub_md1_inner.inter_tf -------------------------
-## set _wave_session_group_sub_md1_inner_inter_tf Group1
-## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
-
-set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
-append _wave_session_group_sub_md1_inner_inter_tf inter_tf
-set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
-
-# set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" {  {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf}  }  
-## ============== sub_md1_inner.inter_tf =========================
-        
-
-## -------------- exp_test_unit_default -------------------------
-set _wave_session_group_exp_test_unit_default exp_test_unit_default
-# set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
-if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
-    set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
-}
-set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" {  }
-## ============== exp_test_unit_default =========================
-        
-
-## -------------- exp_test_unit_default.axis_data_inf -------------------------
-## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
-## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
-
-set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
-append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
-set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
-
-# set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
-
-## 添加信号到 group
-gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" {  {Sim:tb_exp_test_unit.rtl_top.axis_data_inf}  }  
-## ============== exp_test_unit_default.axis_data_inf =========================
-        
 
 ## 创建波形窗口
 if {![info exists useOldWindow]} { 
@@ -162,33 +40,7 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
 ## gui_list_add_group -id ${Wave.3}  -after ${Group2} [list ${Group2|tx_inf}]
 ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
 ## === [add_signal_wave] === ##
-## -------------- Group2_sub_md0_logic -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
-## ============== Group2_sub_md0_logic =========================
-## -------------- Group2_sub_md0_interface -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
-## ============== Group2_sub_md0_interface =========================
-## -------------- Group2_sub_md0_default -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
-## ============== Group2_sub_md0_default =========================
-## -------------- sub_md0_default|inter_tf -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
-## ============== sub_md0_default|inter_tf =========================
-## -------------- Group2_sub_md1_default -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
-## ============== Group2_sub_md1_default =========================
-## -------------- Group2_sub_md1_inner -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
-## ============== Group2_sub_md1_inner =========================
-## -------------- sub_md1_inner|inter_tf -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
-## ============== sub_md1_inner|inter_tf =========================
-## -------------- Group2_exp_test_unit_default -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
-## ============== Group2_exp_test_unit_default =========================
-## -------------- exp_test_unit_default|axis_data_inf -------------------------
-gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
-## ============== exp_test_unit_default|axis_data_inf =========================
+
 
 gui_seek_criteria -id ${Wave.3} {Any Edge}
 
@@ -205,12 +57,7 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
 gui_list_set_filter -id ${Wave.3} -text {*}
 ##gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2}  -position in
 ## === [add_bar] === ##
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_logic}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_interface}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md0_default}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md1_default}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_sub_md1_inner}  -position in
-gui_list_set_insertion_bar  -id ${Wave.3} -group ${Group2_exp_test_unit_default}  -position in
+
 
 gui_marker_move -id ${Wave.3} {C1} 560248001
 gui_view_scroll -id ${Wave.3} -vertical -set 35

data/lib/tdl/examples/9_itegration/tb_test_tttop.sv

@@ -5,10 +5,12 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-03-21 23:54:11 +0800
+created: 2021-04-03 13:14:45 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
+`timescale 1ns/1ps
+`timescale 1ns/1ps
 
 module tb_test_tttop();
 //==========================================================================

data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-03-21 23:51:36 +0800
+created: 2021-04-03 12:39:31 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/9_itegration/test_tttop.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: 2021-03-21 23:54:11 +0800
+created: 2021-04-03 13:14:45 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/exlib/axis_verify.rb

@@ -128,9 +128,9 @@ end
 
 class AxiStream
 
-    def to_simple_sim_master_coe(length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
+    def to_simple_sim_master_coe(enable: 1.b1, length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
         # raise TdlError.new "file cant be empty"  unless file
-        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
+        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{globle_random_name_flag}.coe")
         _sps = nil
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
             require_sdl 'axis_sim_master_model.rb'
@@ -144,11 +144,12 @@ class AxiStream
             _sps 
         end
 
-        @belong_to_module.instance_exec(self,file,loop_coe) do |_self,file,loop_coe| 
+        @belong_to_module.instance_exec(self,file,loop_coe,enable) do |_self,file,loop_coe,_enable| 
 
             Instance(:axis_sim_master_model,"sim_model_inst_#{_self.name}") do |h| 
                 h.param.LOOP                (loop_coe ? "TRUE" : "FALSE")
                 h.param.RAM_DEPTH           File.open(File.expand_path(file)).readlines.size
+                h.input.enable              _enable
                 h.input.load_trigger        1.b0
                 h.input[32].total_length    h.param.RAM_DEPTH
                 h.input[512*8].mem_file     File.expand_path(file) # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -128,7 +128,7 @@ module TdlSpace
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     unless rel 
-                        "#{inst_name}.#{hdl_key}".to_nq
+                        TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
                     else 
                         rel 
                     end
@@ -152,9 +152,9 @@ module TdlSpace
                 define_method('clock') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     if !dimension || dimension.empty?
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                     else  
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}[0].#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
                     end
                 end
 
@@ -171,7 +171,7 @@ module TdlSpace
              self.class_exec(tdl_key) do |tdl_key|
                 define_method('reset') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("reset=") do |arg|
@@ -200,7 +200,7 @@ module TdlSpace
             self.class_exec(tdl_key) do |tdl_key|
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_") || default_value
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("#{tdl_key}=") do |arg|
@@ -215,7 +215,7 @@ module TdlSpace
                 _io_map(e,e,nil,'sdata',nil)
                 self.class_exec(e) do |e|
                     define_method(e) do 
-                        TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                        TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                     end
                 end
             end
@@ -225,7 +225,7 @@ module TdlSpace
             _io_map(name,name,nil,'pdata',dimension)
             self.class_exec(name) do |e|
                 define_method(e) do 
-                    TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                    TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                 end
             end
         end
@@ -374,7 +374,7 @@ module TdlSpace
                     e.slaver = true
                 end 
             end
-            TdlSpace::ArrayChain.new(self,a)
+            TdlSpace::ArrayChain.create(obj: self,lchain: a, belong_to_module: belong_to_module)
         end
 
         def instance(exp_len: nil)

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -74,7 +74,7 @@ class SdlModule
             if e.is_a? String 
                 next 
             end
-            tmp = e.new(name:"#{head}_NC")
+            tmp = e.new(name:"#{head}_NC",belong_to_module: self)
             tmp.belong_to_module = self
             tmp.ghost = true
             instance_variable_set("@#{head}_NC",tmp)
@@ -127,16 +127,6 @@ class SdlModule
         @@allmodule << self
         @module_name = name
         @real_sv_path = File.join(@out_sv_path,"#{@module_name}.sv") if @out_sv_path
-        # @port_clocks = []
-        # @port_resets = []
-        # @port_params = []
-        # @port_logics = []
-        # @port_datainfs = []
-        # @port_datainf_c_s = []
-        # @port_videoinfs = []
-        # @port_axisinfs = []
-        # @port_axi4infs = []
-        # @port_axilinfs = []
 
         @port_clocks        = Hash.new
         @port_resets        = Hash.new
@@ -164,52 +154,16 @@ class SdlModule
             # self.instance_variable_set("#{head_str}_NC",tmp)
         end
         create_ghost
-        # @super_modules = []
-        # @Logic_collect = []
-        # @Logic_inst = []
-        # @Logic_draw = []
-        #
-        # @Clock_collect = []
-        # @Clock_inst = []
-        # @Clock_draw = []
-        #
-        # @Reset_collect = []
-        # @Reset_inst = []
-        # @Reset_draw = []
-        #
-        # @Parameter_collect = []
-        # @Parameter_inst = []
-        # @Parameter_draw = []
-        #
-        # @DataInf_collect = []
-        # @DataInf_inst = []
-        # @DataInf_draw = []
-        #
-        # @DataInf_C_collect = []
-        # @DataInf_C_inst = []
-        # @DataInf_C_draw = []
-        #
-        # @AxiStream_collect = []
-        # @AxiStream_inst = []
-        # @AxiStream_draw = []
-        #
-        # @AxiLite_collect = []
-        # @AxiLite_inst = []
-        # @AxiLite_draw = []
-        #
-        # @VideoInf_collect = []
-        # @VideoInf_inst = []
-        # @VideoInf_draw = []
-        #
-        # @Axi4_collect = []
-        # @Axi4_inst = []
-        # @Axi4_draw = []
+
         if block_given?
             yield(self)
         end
 
         @instanced_and_parent_module ||= Hash.new
         @instance_and_children_module ||= Hash.new
+
+        ## 记录当前模块被例化的 具体对象
+        @instances =[]
     end
 
     public
@@ -473,3 +427,59 @@ class SdlModule
         end
     end
 end
+
+class SdlModule 
+
+    ## 获取信号的绝对路径
+    def path_refs(&block)
+        collects = []
+        if self != TopModule.current.techbench
+            @instances.each do |it|
+                it.origin.parents_inst_tree do |tree|
+                    ll = ["$root"]
+                    rt = tree.reverse
+                    rt.each_index do |index|
+                        if rt[index].respond_to? :module_name
+                            ll << rt[index].module_name 
+                        else 
+                            ll << rt[index].inst_name
+                        end
+                    end
+                    # ll << it.inst_name
+                    new_name = ll.join('.').to_nq
+                    if block_given?
+                        if yield(new_name)
+                            collects << new_name
+                        end 
+                    else
+                        collects << new_name
+                    end
+                end
+            end
+        else
+            collects = ["$root.#{self.module_name}".to_nq]
+        end
+        collects
+    end
+
+    ## 定义获取 信号的绝对路径
+    def root_ref(&block)
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+            rels = path_refs(&block)
+            if block_given?
+                sst = "block given"
+            else
+                sst = "no block"
+            end
+
+            if rels.size == 1
+                rels[0]
+            elsif rels.size == 0
+                raise TdlError.new "#{module_name} Cant find root ref {#{sst}}"
+            else
+                raise TdlError.new "#{module_name} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
+            end
+        end
+    end
+
+end