axi_tdl 0.1.1 → 0.1.3

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Files changed (111) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.sv +2 -2
  6. data/lib/axi/AXI4/axis_to_axi4_wr.sv +8 -8
  7. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  8. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
  9. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  10. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +8 -8
  11. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  12. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  13. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  14. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  15. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  16. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  17. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  18. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  19. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  20. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  21. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
  22. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  23. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  24. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +1 -1
  25. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  26. data/lib/axi_tdl/version.rb +1 -1
  27. data/lib/public_atom_module/CheckPClock.sv +53 -0
  28. data/lib/public_atom_module/LICENSE.md +674 -0
  29. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  30. data/lib/public_atom_module/bits_decode.sv +71 -0
  31. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  32. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  33. data/lib/public_atom_module/broaden.v +43 -0
  34. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  35. data/lib/public_atom_module/ceiling.v +39 -0
  36. data/lib/public_atom_module/ceiling_A1.v +42 -0
  37. data/lib/public_atom_module/clock_rst.sv +64 -0
  38. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  39. data/lib/public_atom_module/edge_generator.v +50 -0
  40. data/lib/public_atom_module/flooring.v +36 -0
  41. data/lib/public_atom_module/latch_data.v +30 -0
  42. data/lib/public_atom_module/latency.v +48 -0
  43. data/lib/public_atom_module/latency_dynamic.v +83 -0
  44. data/lib/public_atom_module/latency_long.v +84 -0
  45. data/lib/public_atom_module/latency_verb.v +52 -0
  46. data/lib/public_atom_module/once_event.sv +65 -0
  47. data/lib/public_atom_module/pipe_reg.v +93 -0
  48. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  49. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  50. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  51. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  52. data/lib/tdl/Logic/logic_edge.rb +1 -1
  53. data/lib/tdl/axi4/axi4_interconnect_verb.rb +46 -9
  54. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  55. data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
  56. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  57. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  58. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  59. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  60. data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
  61. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  62. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  63. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  64. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  65. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  66. data/lib/tdl/elements/Reset.rb +5 -9
  67. data/lib/tdl/elements/clock.rb +5 -9
  68. data/lib/tdl/elements/data_inf.rb +0 -17
  69. data/lib/tdl/elements/logic.rb +9 -31
  70. data/lib/tdl/elements/mail_box.rb +6 -1
  71. data/lib/tdl/elements/originclass.rb +17 -47
  72. data/lib/tdl/elements/parameter.rb +5 -6
  73. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  74. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
  75. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +1 -1
  76. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
  77. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +1 -2
  78. data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
  79. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  80. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  81. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  82. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  83. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
  84. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
  85. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  86. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  87. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
  88. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  89. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
  90. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  91. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  92. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  93. data/lib/tdl/examples/8_top_module/dve.tcl +2 -155
  94. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  95. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +1 -1
  96. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  97. data/lib/tdl/examples/9_itegration/dve.tcl +2 -155
  98. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +3 -1
  99. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
  100. data/lib/tdl/examples/9_itegration/test_tttop.sv +1 -1
  101. data/lib/tdl/exlib/axis_verify.rb +4 -3
  102. data/lib/tdl/rebuild_ele/ele_base.rb +8 -8
  103. data/lib/tdl/sdlmodule/sdlmodule.rb +61 -51
  104. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  105. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  106. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  107. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  108. data/lib/tdl/sdlmodule/test_unit_module.rb +5 -0
  109. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  110. metadata +34 -3
  111. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-21 23:54:11 +0800
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+ created: 2021-04-03 13:14:45 +0800
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  Version: VERA.0.0
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- created: 2021-03-20 12:08:00 +0800
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+ created: 2021-04-03 13:14:02 +0800
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- created: 2021-03-21 23:54:11 +0800
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+ created: 2021-04-03 13:14:45 +0800
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  `timescale 1ns/1ps
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- `timescale 1ns/1ps
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- `timescale 1ns/1ps
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  module tb_exp_test_unit();
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  //==========================================================================
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- created: 2021-03-21 23:51:36 +0800
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  `timescale 1ns/1ps
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  `timescale 1ns/1ps
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- `timescale 1ns/1ps
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  module tb_exp_test_unit_sim();
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- created: 2021-03-21 23:51:42 +0800
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- created: xxxx.xx.xx
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+ created: 2021-03-29 17:23:25 +0800
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  descript:
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  author : Cook.Darwin
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- created: 2021-03-21 23:54:11 +0800
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+ created: 2021-04-03 13:14:45 +0800
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- created: 2021-03-21 23:54:11 +0800
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+ created: 2021-04-03 13:14:45 +0800
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  //==========================================================================
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  //-------- define ----------------------------------------------------------
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  logic [axi_wr_inf.ASIZE-1:0] addr ;
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- logic [axi_wr_inf.IDSIZE-4-1:0] id ;
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+ logic [(axi_wr_inf.IDSIZE - 4)-1:0] id ;
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  logic [24-1:0] length ;
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- axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE(axi_wr_inf.IDSIZE-4),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
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+ axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE((axi_wr_inf.IDSIZE - 4)),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
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  //==========================================================================
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  //-------- instance --------------------------------------------------------
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  axi_stream_cache_35bit cache_inst(
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  author : Cook.Darwin
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- module test_packageparameter NUM = 6;();
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+ package test_package;
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+ parameter NUM = 6;
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  //-------- expression ------------------------------------------------------
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  assign zing_v0.op[9] = 0;
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  ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
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- ## -------------- sub_md0_logic -------------------------
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- set _wave_session_group_sub_md0_logic sub_md0_logic
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- # set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
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- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
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- set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
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- }
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- set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
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- ## 添加信号到 group
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- gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt} }
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- ## ============== sub_md0_logic =========================
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-
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- ## -------------- sub_md0_interface -------------------------
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- set _wave_session_group_sub_md0_interface sub_md0_interface
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- # set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
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- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
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- set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
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- }
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- set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
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- ## 添加信号到 group
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- gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in} }
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- ## ============== sub_md0_interface =========================
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- ## -------------- sub_md0_default -------------------------
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- set _wave_session_group_sub_md0_default sub_md0_default
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- # set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
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- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
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- set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
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- }
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- set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
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- ## 添加信号到 group
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- gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
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- ## ============== sub_md0_default =========================
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- ## -------------- sub_md0_default.inter_tf -------------------------
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- ## set _wave_session_group_sub_md0_default_inter_tf Group1
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- ## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
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- set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
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- append _wave_session_group_sub_md0_default_inter_tf inter_tf
60
- set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
61
-
62
- # set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
63
-
64
- ## 添加信号到 group
65
- gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf} }
66
- ## ============== sub_md0_default.inter_tf =========================
67
-
68
-
69
- ## -------------- sub_md1_default -------------------------
70
- set _wave_session_group_sub_md1_default sub_md1_default
71
- # set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
72
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
73
- set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
74
- }
75
- set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
76
-
77
- ## 添加信号到 group
78
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable} }
79
- ## ============== sub_md1_default =========================
80
-
81
-
82
- ## -------------- sub_md1_inner -------------------------
83
- set _wave_session_group_sub_md1_inner sub_md1_inner
84
- # set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
85
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
86
- set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
87
- }
88
- set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
89
-
90
- ## 添加信号到 group
91
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
92
- ## ============== sub_md1_inner =========================
93
-
94
-
95
- ## -------------- sub_md1_inner.inter_tf -------------------------
96
- ## set _wave_session_group_sub_md1_inner_inter_tf Group1
97
- ## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
98
-
99
- set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
100
- append _wave_session_group_sub_md1_inner_inter_tf inter_tf
101
- set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
102
-
103
- # set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
104
-
105
- ## 添加信号到 group
106
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf} }
107
- ## ============== sub_md1_inner.inter_tf =========================
108
-
109
-
110
- ## -------------- exp_test_unit_default -------------------------
111
- set _wave_session_group_exp_test_unit_default exp_test_unit_default
112
- # set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
113
- if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
114
- set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
115
- }
116
- set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
117
-
118
- ## 添加信号到 group
119
- gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" { }
120
- ## ============== exp_test_unit_default =========================
121
-
122
-
123
- ## -------------- exp_test_unit_default.axis_data_inf -------------------------
124
- ## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
125
- ## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
126
-
127
- set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
128
- append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
129
- set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
130
-
131
- # set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
132
-
133
- ## 添加信号到 group
134
- gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" { {Sim:tb_exp_test_unit.rtl_top.axis_data_inf} }
135
- ## ============== exp_test_unit_default.axis_data_inf =========================
136
-
137
15
 
138
16
  ## 创建波形窗口
139
17
  if {![info exists useOldWindow]} {
@@ -162,33 +40,7 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
162
40
  ## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
163
41
  ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
164
42
  ## === [add_signal_wave] === ##
165
- ## -------------- Group2_sub_md0_logic -------------------------
166
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
167
- ## ============== Group2_sub_md0_logic =========================
168
- ## -------------- Group2_sub_md0_interface -------------------------
169
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
170
- ## ============== Group2_sub_md0_interface =========================
171
- ## -------------- Group2_sub_md0_default -------------------------
172
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
173
- ## ============== Group2_sub_md0_default =========================
174
- ## -------------- sub_md0_default|inter_tf -------------------------
175
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
176
- ## ============== sub_md0_default|inter_tf =========================
177
- ## -------------- Group2_sub_md1_default -------------------------
178
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
179
- ## ============== Group2_sub_md1_default =========================
180
- ## -------------- Group2_sub_md1_inner -------------------------
181
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
182
- ## ============== Group2_sub_md1_inner =========================
183
- ## -------------- sub_md1_inner|inter_tf -------------------------
184
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
185
- ## ============== sub_md1_inner|inter_tf =========================
186
- ## -------------- Group2_exp_test_unit_default -------------------------
187
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
188
- ## ============== Group2_exp_test_unit_default =========================
189
- ## -------------- exp_test_unit_default|axis_data_inf -------------------------
190
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
191
- ## ============== exp_test_unit_default|axis_data_inf =========================
43
+
192
44
 
193
45
  gui_seek_criteria -id ${Wave.3} {Any Edge}
194
46
 
@@ -205,12 +57,7 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
205
57
  gui_list_set_filter -id ${Wave.3} -text {*}
206
58
  ##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
207
59
  ## === [add_bar] === ##
208
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
209
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
210
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
211
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
212
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
213
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_default} -position in
60
+
214
61
 
215
62
  gui_marker_move -id ${Wave.3} {C1} 560248001
216
63
  gui_view_scroll -id ${Wave.3} -vertical -set 35
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-21 23:54:11 +0800
8
+ created: 2021-04-03 13:14:45 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-21 23:50:09 +0800
8
+ created: 2021-04-03 13:14:08 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps