axi_tdl 0.1.1 → 0.1.3
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/Rakefile +7 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.sv +2 -2
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +46 -9
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
- data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
- data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -4
- data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
- data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
- data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
- data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +17 -47
- data/lib/tdl/elements/parameter.rb +5 -6
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
- data/lib/tdl/examples/8_top_module/dve.tcl +2 -155
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +2 -155
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +3 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_tttop.sv +1 -1
- data/lib/tdl/exlib/axis_verify.rb +4 -3
- data/lib/tdl/rebuild_ele/ele_base.rb +8 -8
- data/lib/tdl/sdlmodule/sdlmodule.rb +61 -51
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +5 -0
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +34 -3
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -0,0 +1,93 @@
|
|
1
|
+
/**********************************************
|
2
|
+
______________ ______________
|
3
|
+
______________ \ /\ /|\ /| ______________
|
4
|
+
______________ \/ \/ | \/ | ______________
|
5
|
+
descript:
|
6
|
+
author : Young
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded: 2015/7/9 9:20:55
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
module pipe_reg #(
|
13
|
+
parameter DSIZE = 8
|
14
|
+
)(
|
15
|
+
input clock ,
|
16
|
+
input rst_n ,
|
17
|
+
input wr_en ,
|
18
|
+
input [DSIZE-1:0] indata ,
|
19
|
+
input low_empty ,
|
20
|
+
output valid ,
|
21
|
+
output curr_empty ,
|
22
|
+
output sum_empty ,
|
23
|
+
output[DSIZE-1:0] outdata ,
|
24
|
+
output high_reload
|
25
|
+
);
|
26
|
+
|
27
|
+
/*
|
28
|
+
table
|
29
|
+
higher_vld(wr_en) curr_valid low_empty : next_valid next_data curr_empty sum_empty
|
30
|
+
1 1 1 : 1 U 0 curr_empty | low_empty
|
31
|
+
1 1 0 : 1 K 0 curr_empty | low_empty
|
32
|
+
1 0 1 : 1 U 0 curr_empty | low_empty
|
33
|
+
1 0 0 : 1 U 0 curr_empty | low_empty
|
34
|
+
0 1 1 : 0 C 1 curr_empty | low_empty
|
35
|
+
0 1 0 : 1 K 0 curr_empty | low_empty
|
36
|
+
0 0 1 : 0 C 1 curr_empty | low_empty
|
37
|
+
0 0 0 : 0 C 1 curr_empty | low_empty
|
38
|
+
*/
|
39
|
+
|
40
|
+
reg data_vld;
|
41
|
+
reg[DSIZE-1:0] data_reg;
|
42
|
+
reg reload_reg;
|
43
|
+
|
44
|
+
always@(posedge clock/*,negedge rst_n*/)
|
45
|
+
if(~rst_n) data_vld <= 1'b0;
|
46
|
+
else
|
47
|
+
case({wr_en,data_vld,low_empty})
|
48
|
+
3'b111,
|
49
|
+
3'b110,
|
50
|
+
3'b101,
|
51
|
+
3'b100,
|
52
|
+
3'b010: data_vld <= 1'b1;
|
53
|
+
default:data_vld <= 1'b0;
|
54
|
+
endcase
|
55
|
+
|
56
|
+
always@(posedge clock/*,negedge rst_n*/)
|
57
|
+
if(~rst_n) reload_reg <= 1'b0;
|
58
|
+
else
|
59
|
+
case({wr_en,data_vld,low_empty})
|
60
|
+
3'b111: reload_reg <= 1'b1;
|
61
|
+
3'b110: reload_reg <= 1'b0;
|
62
|
+
3'b101: reload_reg <= 1'b1;
|
63
|
+
3'b100: reload_reg <= 1'b1;
|
64
|
+
3'b011: reload_reg <= 1'b1;
|
65
|
+
3'b010: reload_reg <= 1'b0;
|
66
|
+
3'b001: reload_reg <= 1'b1;
|
67
|
+
3'b000: reload_reg <= 1'b1;
|
68
|
+
default:reload_reg <= 1'b0;
|
69
|
+
endcase
|
70
|
+
|
71
|
+
always@(posedge clock/*,negedge rst_n*/)
|
72
|
+
if(~rst_n) data_reg <= {DSIZE{1'b0}};
|
73
|
+
else
|
74
|
+
case({wr_en,data_vld,low_empty})
|
75
|
+
3'b111: data_reg <= indata;
|
76
|
+
3'b110: data_reg <= data_reg;
|
77
|
+
3'b101: data_reg <= indata;
|
78
|
+
3'b100: data_reg <= indata;
|
79
|
+
3'b011: data_reg <= {DSIZE{1'b0}};
|
80
|
+
3'b010: data_reg <= data_reg;
|
81
|
+
3'b001: data_reg <= {DSIZE{1'b0}};
|
82
|
+
3'b000: data_reg <= {DSIZE{1'b0}};
|
83
|
+
default:data_reg <= {DSIZE{1'b0}};
|
84
|
+
endcase
|
85
|
+
|
86
|
+
assign curr_empty = !data_vld;
|
87
|
+
assign outdata = data_reg;
|
88
|
+
assign valid = data_vld;
|
89
|
+
assign sum_empty = curr_empty | low_empty;
|
90
|
+
assign high_reload = reload_reg;
|
91
|
+
|
92
|
+
endmodule
|
93
|
+
|
@@ -0,0 +1,84 @@
|
|
1
|
+
/**********************************************
|
2
|
+
______________ ______________
|
3
|
+
______________ \ /\ /|\ /| ______________
|
4
|
+
______________ \/ \/ | \/ | ______________
|
5
|
+
descript:
|
6
|
+
author : Young
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded: 2015/7/9 9:20:55
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
module pipe_reg_2write_port #(
|
13
|
+
parameter DSIZE = 8
|
14
|
+
)(
|
15
|
+
input clock ,
|
16
|
+
input rst_n ,
|
17
|
+
input wr_en0 ,
|
18
|
+
input [DSIZE-1:0] indata0 ,
|
19
|
+
input wr_en1 ,
|
20
|
+
input [DSIZE-1:0] indata1 ,
|
21
|
+
input low_empty ,
|
22
|
+
output valid ,
|
23
|
+
output curr_empty ,
|
24
|
+
output sum_empty ,
|
25
|
+
output[DSIZE-1:0] outdata
|
26
|
+
);
|
27
|
+
|
28
|
+
wire[DSIZE-1:0] indata;
|
29
|
+
wire wr_en;
|
30
|
+
|
31
|
+
assign indata = wr_en0? indata0 : (wr_en1? indata0 :{DSIZE{1'b0}});
|
32
|
+
assign wr_en = wr_en0 | wr_en1;
|
33
|
+
|
34
|
+
/*
|
35
|
+
table
|
36
|
+
higher_vld(wr_en) curr_valid low_empty : next_valid next_data curr_empty sum_empty
|
37
|
+
1 1 1 : 1 U 0 curr_empty | low_empty
|
38
|
+
1 1 0 : 1 K 0 curr_empty | low_empty
|
39
|
+
1 0 1 : 1 U 0 curr_empty | low_empty
|
40
|
+
1 0 0 : 1 U 0 curr_empty | low_empty
|
41
|
+
0 1 1 : 0 C 1 curr_empty | low_empty
|
42
|
+
0 1 0 : 1 K 0 curr_empty | low_empty
|
43
|
+
0 0 1 : 0 C 1 curr_empty | low_empty
|
44
|
+
0 0 0 : 0 C 1 curr_empty | low_empty
|
45
|
+
*/
|
46
|
+
|
47
|
+
reg data_vld;
|
48
|
+
reg[DSIZE-1:0] data_reg;
|
49
|
+
|
50
|
+
always@(posedge clock/*,negedge rst_n*/)
|
51
|
+
if(~rst_n) data_vld <= 1'b0;
|
52
|
+
else
|
53
|
+
case({wr_en,data_vld,low_empty})
|
54
|
+
3'b111,
|
55
|
+
3'b110,
|
56
|
+
3'b101,
|
57
|
+
3'b100,
|
58
|
+
3'b010: data_vld <= 1'b1;
|
59
|
+
default:data_vld <= 1'b0;
|
60
|
+
endcase
|
61
|
+
|
62
|
+
always@(posedge clock/*,negedge rst_n*/)
|
63
|
+
if(~rst_n) data_reg <= {DSIZE{1'b0}};
|
64
|
+
else
|
65
|
+
case({wr_en,data_vld,low_empty})
|
66
|
+
3'b111: data_reg <= indata;
|
67
|
+
3'b110: data_reg <= data_reg;
|
68
|
+
3'b101: data_reg <= indata;
|
69
|
+
3'b100: data_reg <= indata;
|
70
|
+
3'b011: data_reg <= {DSIZE{1'b0}};
|
71
|
+
3'b010: data_reg <= data_reg;
|
72
|
+
3'b001: data_reg <= {DSIZE{1'b0}};
|
73
|
+
3'b000: data_reg <= {DSIZE{1'b0}};
|
74
|
+
default:data_reg <= {DSIZE{1'b0}};
|
75
|
+
endcase
|
76
|
+
|
77
|
+
|
78
|
+
assign curr_empty = !data_vld;
|
79
|
+
assign outdata = data_reg;
|
80
|
+
assign valid = data_vld;
|
81
|
+
assign sum_empty = curr_empty | low_empty;
|
82
|
+
|
83
|
+
endmodule
|
84
|
+
|
@@ -0,0 +1,54 @@
|
|
1
|
+
/**********************************************
|
2
|
+
______________________________________________
|
3
|
+
_______ ___ ___ ___ __ _ _
|
4
|
+
_______ | | | |\ /| |___ | \ | /_\
|
5
|
+
_______ |___ |___| | \/ | |___ |__/ | / \
|
6
|
+
_______________________________________________
|
7
|
+
descript:
|
8
|
+
author : Young
|
9
|
+
Version: VERB.0.0
|
10
|
+
create a module for it
|
11
|
+
creaded: 2015/10/16 10:50:52
|
12
|
+
madified:
|
13
|
+
***********************************************/
|
14
|
+
`timescale 1ns/1ps
|
15
|
+
(* data_inf = "true" *)
|
16
|
+
module clock_rst_verb #(
|
17
|
+
parameter bit ACTIVE = 1,
|
18
|
+
parameter longint PERIOD_CNT = 0,
|
19
|
+
parameter RST_HOLD = 5,
|
20
|
+
parameter real FreqM = 100
|
21
|
+
)(
|
22
|
+
output clock,
|
23
|
+
output rst_x
|
24
|
+
);
|
25
|
+
|
26
|
+
bit clk_pause = 1;
|
27
|
+
bit clock_reg;
|
28
|
+
bit rst_reg;
|
29
|
+
|
30
|
+
longint ccnt = 0;
|
31
|
+
|
32
|
+
initial begin
|
33
|
+
clk_pause = 1;
|
34
|
+
clock_reg = 0;
|
35
|
+
rst_reg = ACTIVE;
|
36
|
+
#(1000/FreqM*2);
|
37
|
+
clk_pause = 0;
|
38
|
+
repeat(RST_HOLD)
|
39
|
+
@(posedge clock_reg);
|
40
|
+
rst_reg = ~rst_reg;
|
41
|
+
end
|
42
|
+
|
43
|
+
always #(1000/FreqM/2) begin
|
44
|
+
if(clk_pause == 0 && (PERIOD_CNT==0 || ccnt < PERIOD_CNT))
|
45
|
+
clock_reg = ~clock_reg;
|
46
|
+
end
|
47
|
+
|
48
|
+
always@(posedge clock)
|
49
|
+
ccnt <= ccnt + 1;
|
50
|
+
|
51
|
+
assign clock = clock_reg;
|
52
|
+
assign rst_x = rst_reg;
|
53
|
+
|
54
|
+
endmodule
|
@@ -0,0 +1,49 @@
|
|
1
|
+
/**********************************************
|
2
|
+
______________ ______________
|
3
|
+
______________ \ /\ /|\ /| ______________
|
4
|
+
______________ \/ \/ | \/ | ______________
|
5
|
+
descript:
|
6
|
+
author : Young
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded: 2015/12/1 14:28:31
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
module latency_long_tb;
|
13
|
+
|
14
|
+
bit clock = 0;
|
15
|
+
bit rst_n = 0;
|
16
|
+
|
17
|
+
always #5 clock = ~clock;
|
18
|
+
|
19
|
+
initial begin
|
20
|
+
repeat(10) @(posedge clock);
|
21
|
+
rst_n = 1;
|
22
|
+
end
|
23
|
+
|
24
|
+
bit d;
|
25
|
+
|
26
|
+
initial begin
|
27
|
+
d = 0 ;
|
28
|
+
wait(rst_n);
|
29
|
+
repeat(20) @(posedge clock);
|
30
|
+
d = 1;
|
31
|
+
repeat(1) @(posedge clock);
|
32
|
+
d = 0;
|
33
|
+
end
|
34
|
+
|
35
|
+
latency_long #(
|
36
|
+
.LAT (5 )
|
37
|
+
)latency_long_inst(
|
38
|
+
.clock (clock ),
|
39
|
+
.rst_n (rst_n ),
|
40
|
+
.d (d ),
|
41
|
+
.q ( )
|
42
|
+
);
|
43
|
+
|
44
|
+
|
45
|
+
endmodule
|
46
|
+
|
47
|
+
|
48
|
+
|
49
|
+
|
@@ -0,0 +1,49 @@
|
|
1
|
+
/**********************************************
|
2
|
+
______________ ______________
|
3
|
+
______________ \ /\ /|\ /| ______________
|
4
|
+
______________ \/ \/ | \/ | ______________
|
5
|
+
descript:
|
6
|
+
author : Young
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded: 2015/12/1 14:28:31
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
module latency_long_tb;
|
13
|
+
|
14
|
+
bit clock = 0;
|
15
|
+
bit rst_n = 0;
|
16
|
+
|
17
|
+
always #5 clock = ~clock;
|
18
|
+
|
19
|
+
initial begin
|
20
|
+
repeat(10) @(posedge clock);
|
21
|
+
rst_n = 1;
|
22
|
+
end
|
23
|
+
|
24
|
+
bit d;
|
25
|
+
|
26
|
+
initial begin
|
27
|
+
d = 0 ;
|
28
|
+
wait(rst_n);
|
29
|
+
repeat(20) @(posedge clock);
|
30
|
+
d = 1;
|
31
|
+
repeat(10) @(posedge clock);
|
32
|
+
d = 0;
|
33
|
+
end
|
34
|
+
|
35
|
+
latency_long #(
|
36
|
+
.LAT (5 )
|
37
|
+
)latency_long_inst(
|
38
|
+
.clock (clock ),
|
39
|
+
.rst_n (rst_n ),
|
40
|
+
.d (d ),
|
41
|
+
.q ( )
|
42
|
+
);
|
43
|
+
|
44
|
+
|
45
|
+
endmodule
|
46
|
+
|
47
|
+
|
48
|
+
|
49
|
+
|
data/lib/tdl/Logic/logic_edge.rb
CHANGED
@@ -66,7 +66,34 @@ class Axi4
|
|
66
66
|
# next unless e.is_a? Axi4
|
67
67
|
if e.is_a? Axi4
|
68
68
|
e.band_params_from(self)
|
69
|
-
|
69
|
+
|
70
|
+
## e is a Vector
|
71
|
+
if e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
|
72
|
+
# require_hdl 'axi4_direct_B1.sv'
|
73
|
+
require_hdl 'axi4_direct_verc.sv'
|
74
|
+
|
75
|
+
e.dimension[0].times do |xi|
|
76
|
+
_ne = e.copy(name: "#{e.inst_name}_toM_#{xi}")
|
77
|
+
# _ne << e[xi]
|
78
|
+
# belong_to_module.Instance('axi4_direct_B1',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
|
79
|
+
# # h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
80
|
+
# h.slaver_inf e[xi]
|
81
|
+
# h.master_inf _ne
|
82
|
+
# end
|
83
|
+
|
84
|
+
belong_to_module.Instance('axi4_direct_verc',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
|
85
|
+
h.param.MODE "#{_ne.mode}_to_#{_ne.mode}" # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
86
|
+
h.param.SLAVER_MODE _ne.mode # //
|
87
|
+
h.param.MASTER_MODE _ne.mode # //
|
88
|
+
h.slaver_inf e[xi]
|
89
|
+
h.master_inf _ne
|
90
|
+
end
|
91
|
+
|
92
|
+
@interconnect_up_streams << _ne
|
93
|
+
end
|
94
|
+
else
|
95
|
+
@interconnect_up_streams << e
|
96
|
+
end
|
70
97
|
else
|
71
98
|
raise TdlError.new("When use `<<` for axi4's M2S ,argvs must be axi4 too.\nOtherwise use `naxi4_mix_interconnect_M2S` directly")
|
72
99
|
end
|
@@ -218,10 +245,19 @@ class Axi4
|
|
218
245
|
else
|
219
246
|
mode_str = "ONLY_READ_to_BOTH"
|
220
247
|
end
|
221
|
-
require_hdl 'axi4_direct_B1.sv'
|
222
|
-
# Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
|
223
|
-
belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
|
224
|
-
|
248
|
+
# require_hdl 'axi4_direct_B1.sv'
|
249
|
+
# # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
|
250
|
+
# belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
|
251
|
+
# # h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
252
|
+
# h.slaver_inf lo
|
253
|
+
# h.master_inf "#{sub_name}[#{index}]".to_nq
|
254
|
+
# end
|
255
|
+
|
256
|
+
require_hdl 'axi4_direct_verc.sv'
|
257
|
+
belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
|
258
|
+
h.param.MODE mode_str # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
259
|
+
h.param.SLAVER_MODE (wr_lg ? "ONLY_WRITE" : "ONLY_READ") # //
|
260
|
+
h.param.MASTER_MODE "BOTH" # //
|
225
261
|
h.slaver_inf lo
|
226
262
|
h.master_inf "#{sub_name}[#{index}]".to_nq
|
227
263
|
end
|
@@ -252,10 +288,11 @@ class Axi4
|
|
252
288
|
@_long_slim_to_wide.each do |e|
|
253
289
|
mode_str = e.mode + "_to_BOTH"
|
254
290
|
# Axi4.axi4_direct_a1(mode:mode_str,slaver:e,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
|
291
|
+
require_hdl 'axi4_direct_B1.sv'
|
255
292
|
belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_inst_long_to_wide_#{sub_name}") do |h|
|
256
293
|
# h.param.MODE mode_str #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
257
|
-
h.
|
258
|
-
h.
|
294
|
+
h.slaver_inf e
|
295
|
+
h.master_inf "#{sub_name}[#{index}]".to_nq
|
259
296
|
end
|
260
297
|
index = index + 1
|
261
298
|
end
|
@@ -311,8 +348,8 @@ class Axi4
|
|
311
348
|
"\naxi4_direct_B1 /* #(
|
312
349
|
.MODE (\"#{_str}\") //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
|
313
350
|
)*/ iterconnect_direct_A1_#{name}_instMM(
|
314
|
-
/* axi_inf.slaver */ .
|
315
|
-
/* axi_inf.master */ .
|
351
|
+
/* axi_inf.slaver */ .slaver_inf (sub_axi_#{name}_inf[0]),
|
352
|
+
/* axi_inf.master */ .master_inf (#{name})
|
316
353
|
);\n"
|
317
354
|
end
|
318
355
|
|
@@ -7,6 +7,9 @@ module ClassHDL
|
|
7
7
|
def initialize(belong_to_module)
|
8
8
|
@opertor_chains = []
|
9
9
|
@belong_to_module = belong_to_module
|
10
|
+
unless @belong_to_module
|
11
|
+
raise TdlError.new("HDLAlwaysCombBlock must have belong_to_module")
|
12
|
+
end
|
10
13
|
end
|
11
14
|
|
12
15
|
def instance
|
@@ -17,7 +20,7 @@ module ClassHDL
|
|
17
20
|
str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
|
18
21
|
else
|
19
22
|
unless op.slaver
|
20
|
-
rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
|
23
|
+
rel_str = ClassHDL.compact_op_ch(op.instance(:assign, @belong_to_module))
|
21
24
|
str.push " #{rel_str};"
|
22
25
|
end
|
23
26
|
end
|