axi_tdl 0.1.1 → 0.1.3

data/lib/axi/AXI_stream/axis_sim_master_model.rb

@@ -3,6 +3,7 @@ require_hdl 'data_c_sim_master_model.sv'
 TdlBuild.axis_sim_master_model(__dir__) do 
     parameter.LOOP       "TRUE"
     parameter.RAM_DEPTH  10000
+    input               - 'enable'
     input               - 'load_trigger'
     input[32]           - 'total_length'
     input[512*8]        - 'mem_file' # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}
@@ -13,6 +14,7 @@ TdlBuild.axis_sim_master_model(__dir__) do
     data_c_sim_master_model.data_c_sim_master_model_inst do |h| #(
         h.param.LOOP        param.LOOP
         h.param.RAM_DEPTH   param.RAM_DEPTH
+        h.input.enable              enable
         h.input.load_trigger        load_trigger
         h.input[32].total_length    total_length
         h.input[512*8].mem_file     mem_file

data/lib/axi/AXI_stream/axis_sim_master_model.sv

@@ -0,0 +1,46 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2021-04-03 12:04:15 +0800
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axis_sim_master_model #(
+    parameter  LOOP      = "TRUE",
+    parameter  RAM_DEPTH = 10000
+)(
+    input                   enable,
+    input                   load_trigger,
+    input [31:0]            total_length,
+    input [4095:0]          mem_file,
+    axi_stream_inf.master   out_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+data_inf_c #(.DSIZE(out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1)) out_inf_dc (.clock(out_inf.aclk),.rst_n(out_inf.aresetn)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+data_c_sim_master_model #(
+    .LOOP      (LOOP      ),
+    .RAM_DEPTH (RAM_DEPTH )
+)data_c_sim_master_model_inst(
+/* input             */.enable       (enable       ),
+/* input             */.load_trigger (load_trigger ),
+/* input             */.total_length (total_length ),
+/* input             */.mem_file     (mem_file     ),
+/* data_inf_c.master */.out_inf      (out_inf_dc   )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign out_inf.axis_tvalid = out_inf_dc.valid;
+assign out_inf_dc.ready = out_inf.axis_tready;
+assign {>>{out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata}} = out_inf_dc.data;
+
+endmodule

data/lib/axi/AXI_stream/axis_split_channel_verb.sv

@@ -0,0 +1,62 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: XXXX.XX.XX
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module axis_split_channel_verb (
+    input [15:0]            split_len,
+    axi_stream_inf.slaver   origin_inf,
+    axi_stream_inf.master   first_inf,
+    axi_stream_inf.master   end_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock;
+logic  rst_n;
+logic [16-1:0]  insert_seed ;
+logic [16-1:0]  next_split_len ;
+axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+axis_insert_copy axis_insert_copy_inst(
+/* input                 */.insert_seed (insert_seed       ),
+/* input                 */.insert_len  (8'd1              ),
+/* axi_stream_inf.slaver */.in_inf      (origin_inf        ),
+/* axi_stream_inf.master */.out_inf     (origin_inf_insert )
+);
+common_fifo #(
+    .DEPTH (4  ),
+    .DSIZE (16 )
+)common_fifo_head_bytesx_inst(
+/* input  */.clock (clock                                                                                          ),
+/* input  */.rst_n (rst_n                                                                                          ),
+/* input  */.wdata (split_len                                                                                      ),
+/* input  */.wr_en ((origin_inf.axis_tcnt == '0) && origin_inf.axis_tvalid && origin_inf.axis_tready               ),
+/* output */.rdata (next_split_len                                                                                 ),
+/* input  */.rd_en (origin_inf_insert.axis_tvalid && origin_inf_insert.axis_tready && origin_inf_insert.axis_tlast ),
+/* output */.count (/*unused */                                                                                    ),
+/* output */.empty (/*unused */                                                                                    ),
+/* output */.full  (/*unused */                                                                                    )
+);
+axi_stream_split_channel axi_stream_split_channel_inst(
+/* input                 */.split_len  (next_split_len    ),
+/* axi_stream_inf.slaver */.origin_inf (origin_inf_insert ),
+/* axi_stream_inf.master */.first_inf  (first_inf         ),
+/* axi_stream_inf.master */.end_inf    (end_inf           )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign clock = origin_inf.aclk;
+assign rst_n = origin_inf.aresetn;
+
+assign insert_seed = split_len-1'b1;
+
+endmodule

data/lib/axi/common/common_ram_sim_wrapper.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/axi/common/common_ram_wrapper.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
 endgenerate
 //-------- CLOCKs Total 2 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_7,cc_same_7;
-integer cc_afreq_7,cc_bfreq_7;
-ClockSameDomain CheckPClock_inst_7(
+logic cc_done_9,cc_same_9;
+integer cc_afreq_9,cc_bfreq_9;
+ClockSameDomain CheckPClock_inst_9(
 /*  input         */      .aclk     (in_inf.clock           ),
 /*  input         */      .bclk     (out_inf.clock          ),
-/*  output logic  */      .done     (cc_done_7),
-/*  output logic  */      .same     (cc_same_7),
-/*  output integer */     .aFreqK   (cc_afreq_7),
-/*  output integer */     .bFreqK   (cc_bfreq_7)
+/*  output logic  */      .done     (cc_done_9),
+/*  output logic  */      .same     (cc_same_9),
+/*  output integer */     .aFreqK   (cc_afreq_9),
+/*  output integer */     .bFreqK   (cc_bfreq_9)
 );
 
 initial begin
-    wait(cc_done_7);
-    assert(cc_same_7)
+    wait(cc_done_9);
+    assert(cc_same_9)
     else begin
-        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
+        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
         repeat(10)begin 
             @(posedge in_inf.clock);
         end

data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv

@@ -13,6 +13,7 @@ module data_c_sim_master_model #(
     parameter   LOOP        = "TRUE",
     parameter   RAM_DEPTH   = 10000
 )(
+    input               enable,
     input               load_trigger,
     input [31:0]        total_length,
     input[512*8-1:0]    mem_file,
@@ -46,24 +47,26 @@ end
 always@(posedge out_inf.clock) begin 
     if(~out_inf.rst_n) index     <= 0;
     else begin 
-        if(out_inf.ready) begin 
-            if(index >= total_length_lock-1)begin 
-                if(LOOP == "TRUE" || LOOP == "ON")begin 
-                    index <= 0;
+        if(enable)begin 
+            if(out_inf.ready) begin 
+                if(index >= total_length_lock-1)begin 
+                    if(LOOP == "TRUE" || LOOP == "ON")begin 
+                        index <= 0;
+                    end else begin 
+                        index   <= total_length_lock-1;
+                        disable_coe <= 1'b1;
+                    end 
                 end else begin 
-                    index   <= total_length_lock-1;
-                    disable_coe <= 1'b1;
+                    index <= index + 1;
                 end 
             end else begin 
-                index <= index + 1;
+                index <= index;
             end 
-        end else begin 
-            index <= index;
-        end 
+        end
     end 
 end 
 
 assign out_inf.data     = BRAM[index][out_inf.DSIZE-1:0];
-assign out_inf.valid    = BRAM[index][out_inf.DSIZE] && ~disable_coe; 
+assign out_inf.valid    = BRAM[index][out_inf.DSIZE] && ~disable_coe && enable; 
 
 endmodule

data/lib/axi/platform_ip/fifo_36kb_long.sv

@@ -53,7 +53,7 @@ localparam DIV =    ((DSIZE>=37) && (DSIZE<=72)) ? 512 :
                     ((DSIZE>=5 ) && (DSIZE<=9 )) ? 4096 :
                     ((DSIZE>=1 ) && (DSIZE<=4 )) ? 8192 : 8192;
 
-localparam KNUM = DEPTH/DIV;
+localparam KNUM = DEPTH/DIV + (DEPTH/DIV == 0);
 
 // FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
 //                       Artix-7

data/lib/axi/techbench/tb_axi_stream_split_channel.rb

@@ -1,4 +1,4 @@
-require 'axi_tdl'
+require_relative '../../axi_tdl.rb'
 require_sdl 'axi_stream_split_channel.rb'
 
 TdlBuild.tb_axi_stream_split_channel(__dir__) do 

data/lib/axi/techbench/tb_axi_stream_split_channel.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-04-03 12:04:15 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -36,113 +36,114 @@ logic_sim_model #(
     .DSIZE     (16     ),
     .RAM_DEPTH (8      )
 )split_len_sim_model_inst(
-/* input  */.next_at_negedge_of (origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast             ),
-/* input  */.next_at_posedge_of (1'b0                                                                                  ),
-/* input  */.load_trigger       (1'b0                                                                                  ),
-/* input  */.total_length       (8                                                                                     ),
-/* input  */.mem_file           ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/split_len_R1712.coe" ),
-/* output */.data               (split_len                                                                             )
+/* input  */.next_at_negedge_of (origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast  ),
+/* input  */.next_at_posedge_of (1'b0                                                                       ),
+/* input  */.load_trigger       (1'b0                                                                       ),
+/* input  */.total_length       (8                                                                          ),
+/* input  */.mem_file           ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/split_len_R674.coe" ),
+/* output */.data               (split_len                                                                  )
 );
 axis_sim_master_model #(
     .LOOP      ("TRUE" ),
     .RAM_DEPTH (246    )
 )sim_model_inst_origin_inf(
-/* input                 */.load_trigger (1'b0                                                                                  ),
-/* input                 */.total_length (246                                                                                   ),
-/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/origin_inf_R560.coe" ),
-/* axi_stream_inf.master */.out_inf      (origin_inf                                                                            )
+/* input                 */.enable       (/*unused */                                                                  ),
+/* input                 */.load_trigger (1'b0                                                                         ),
+/* input                 */.total_length (246                                                                          ),
+/* input                 */.mem_file     ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/origin_inf_R1699.coe" ),
+/* axi_stream_inf.master */.out_inf      (origin_inf                                                                   )
 );
 axis_sim_verify_by_coe #(
     .RAM_DEPTH   (21    ),
     .VERIFY_KEEP ("OFF" ),
     .VERIFY_USER ("OFF" )
 )axis_sim_verify_by_coe_inst_first_inf(
-/* input                 */.load_trigger (1'b0                                                                                  ),
-/* input                 */.total_length (21                                                                                    ),
-/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/first_inf_R1297.coe" ),
-/* axi_stream_inf.mirror */.mirror_inf   (first_inf                                                                             )
+/* input                 */.load_trigger (1'b0                                                                        ),
+/* input                 */.total_length (21                                                                          ),
+/* input                 */.mem_file     ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/first_inf_R1282.coe" ),
+/* axi_stream_inf.mirror */.mirror_inf   (first_inf                                                                   )
 );
 axis_sim_verify_by_coe #(
     .RAM_DEPTH   (113   ),
     .VERIFY_KEEP ("OFF" ),
     .VERIFY_USER ("OFF" )
 )axis_sim_verify_by_coe_inst_end_inf(
-/* input                 */.load_trigger (1'b0                                                                                ),
-/* input                 */.total_length (113                                                                                 ),
-/* input                 */.mem_file     ("/var/lib/gems/2.5.0/gems/axi_tdl-0.0.10/lib/tdl/auto_script/tmp/end_inf_R1464.coe" ),
-/* axi_stream_inf.mirror */.mirror_inf   (end_inf                                                                             )
+/* input                 */.load_trigger (1'b0                                                                      ),
+/* input                 */.total_length (113                                                                       ),
+/* input                 */.mem_file     ("/home/wmy367/work/gem/axi_tdl/lib/tdl/auto_script/tmp/end_inf_R1315.coe" ),
+/* axi_stream_inf.mirror */.mirror_inf   (end_inf                                                                   )
 );
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-     clock = 1'b0;
-     #(100ns);
-     forever begin #(5.0ns);clock = ~clock;end;
+    clock = 1'b0;
+    #(100ns);
+    forever begin #(5.0ns);clock = ~clock;end;
 end
 
 initial begin
-     rst_n = 1'b0;
-     #(200ns);
-     rst_n = ~rst_n;
+    rst_n = 1'b0;
+    #(200ns);
+    rst_n = ~rst_n;
 end
 
 initial begin
-     first_inf_rdy_percetage_index = 0;
-     first_inf_rdy_percetage[0] = 50;
-     first_inf_rdy_percetage[1] = 100;
-     first_inf_rdy_percetage[2] = 30;
+    first_inf_rdy_percetage_index = 0;
+    first_inf_rdy_percetage[0] = 50;
+    first_inf_rdy_percetage[1] = 100;
+    first_inf_rdy_percetage[2] = 30;
 end
 
 always@(posedge clock) begin 
     if(first_inf.axis_tvalid && first_inf.axis_tready && first_inf.axis_tlast)begin
-        if( first_inf_rdy_percetage_index>=( 3-1))begin
-             first_inf_rdy_percetage_index <= 0;
+        if(first_inf_rdy_percetage_index>=(3-1))begin
+            first_inf_rdy_percetage_index <= 0;
         end
         else begin
-             first_inf_rdy_percetage_index <= ( first_inf_rdy_percetage_index+1'b1);
+            first_inf_rdy_percetage_index <= (first_inf_rdy_percetage_index+1'b1);
         end
     end
     else begin
-         first_inf_rdy_percetage_index <= first_inf_rdy_percetage_index;
+        first_inf_rdy_percetage_index <= first_inf_rdy_percetage_index;
     end
 end
 
 always@(posedge clock) begin 
     if(~rst_n)begin
-         first_inf.axis_tready <= 1'b0;
+        first_inf.axis_tready <= 1'b0;
     end
     else begin
-         first_inf.axis_tready <= ($urandom_range(0,99) <= first_inf_rdy_percetage[first_inf_rdy_percetage_index]);
+        first_inf.axis_tready <= ($urandom_range(0,99) <= first_inf_rdy_percetage[first_inf_rdy_percetage_index]);
     end
 end
 
 initial begin
-     end_inf_rdy_percetage_index = 0;
-     end_inf_rdy_percetage[0] = 100;
-     end_inf_rdy_percetage[1] = 50;
-     end_inf_rdy_percetage[2] = 100;
+    end_inf_rdy_percetage_index = 0;
+    end_inf_rdy_percetage[0] = 100;
+    end_inf_rdy_percetage[1] = 50;
+    end_inf_rdy_percetage[2] = 100;
 end
 
 always@(posedge clock) begin 
     if(end_inf.axis_tvalid && end_inf.axis_tready && end_inf.axis_tlast)begin
-        if( end_inf_rdy_percetage_index>=( 3-1))begin
-             end_inf_rdy_percetage_index <= 0;
+        if(end_inf_rdy_percetage_index>=(3-1))begin
+            end_inf_rdy_percetage_index <= 0;
         end
         else begin
-             end_inf_rdy_percetage_index <= ( end_inf_rdy_percetage_index+1'b1);
+            end_inf_rdy_percetage_index <= (end_inf_rdy_percetage_index+1'b1);
         end
     end
     else begin
-         end_inf_rdy_percetage_index <= end_inf_rdy_percetage_index;
+        end_inf_rdy_percetage_index <= end_inf_rdy_percetage_index;
     end
 end
 
 always@(posedge clock) begin 
     if(~rst_n)begin
-         end_inf.axis_tready <= 1'b0;
+        end_inf.axis_tready <= 1'b0;
     end
     else begin
-         end_inf.axis_tready <= ($urandom_range(0,99) <= end_inf_rdy_percetage[end_inf_rdy_percetage_index]);
+        end_inf.axis_tready <= ($urandom_range(0,99) <= end_inf_rdy_percetage[end_inf_rdy_percetage_index]);
     end
 end
 

data/lib/axi_tdl/version.rb

@@ -1,3 +1,3 @@
 module AxiTdl
-  VERSION = "0.1.1"
+  VERSION = "0.1.3"
 end

data/lib/public_atom_module/CheckPClock.sv

@@ -0,0 +1,53 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version:
+creaded: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module CheckPClock (
+    input               aclk,
+    input               bclk,
+    output logic        done,
+    output logic        same
+);
+
+
+realtime     a2b;
+realtime     b2a;
+
+
+initial begin
+    done = 0;
+    same = 1;
+    repeat(100)begin
+        @(posedge aclk);
+        @(posedge bclk);
+    end
+    @(posedge aclk);
+    a2b = $realtime;
+    @(posedge bclk);
+    a2b = $realtime - a2b;
+
+    @(posedge bclk);
+    b2a = $realtime;
+    @(posedge aclk);
+    b2a = $realtime - b2a;
+    @(posedge aclk);
+    if(a2b < (b2a + 0.001) || a2b > (b2a - 0.001))
+            same = 1;
+    else    same = 0;
+
+    repeat(10)begin
+        @(posedge aclk);
+        @(posedge bclk);
+    end
+
+    done = 1;
+end
+
+endmodule