axi_tdl 0.1.1 → 0.1.3
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- checksums.yaml +4 -4
- data/Rakefile +7 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.sv +2 -2
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +8 -8
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +11 -11
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +46 -9
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
- data/lib/tdl/class_hdl/hdl_always_ff.rb +2 -2
- data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -4
- data/lib/tdl/class_hdl/hdl_generate.rb +4 -1
- data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
- data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
- data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +17 -47
- data/lib/tdl/elements/parameter.rb +5 -6
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -3
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tu0.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
- data/lib/tdl/examples/8_top_module/dve.tcl +2 -155
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +2 -155
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +3 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_tttop.sv +1 -1
- data/lib/tdl/exlib/axis_verify.rb +4 -3
- data/lib/tdl/rebuild_ele/ele_base.rb +8 -8
- data/lib/tdl/sdlmodule/sdlmodule.rb +61 -51
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +5 -0
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +34 -3
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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+
metadata.gz: 99f610d018d1748b203a9585758257032c2a0e546efe8f01b93e357eddb9ddf7
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data.tar.gz: 80ec9d6701044c372b3ae6a7ab924eb314616d0c1ab1e9db9478dc22ca04d513
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SHA512:
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metadata.gz:
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data.tar.gz:
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+
metadata.gz: 99e0ded0d9f5b6c5f8e053a0a7fa32d3c13330c0746844bb18e29757105b8bf6c0f4c6755edfdbf730e290c1f6fb4f52cb87a8afc1fd39a731325f76ae51ef29
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+
data.tar.gz: 1c42c7ff45587b03dc9c859eb9c80d7274cf6ff73f006e5bc68ed578a0235a064bb480d7685bf8421432eecdba07d820147d2145037b6a55862e298865356138
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data/Rakefile
CHANGED
@@ -12,3 +12,10 @@ Rake::TestTask.new(:test) do |t|
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# t.ruby_opts = ["-c"]
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# t.verbose = true
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end
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+
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desc "编译TB"
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task :tb do
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+
require_relative "./lib/axi_tdl.rb"
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puts AxiTdl::VERSION
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require_relative "./lib/axi/techbench/tb_axi_stream_split_channel.rb"
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end
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@@ -53,7 +53,7 @@ initial begin
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case(MODE)
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"BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
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assert(slaver.MODE =="BOTH")
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-
else $error("SLAVER AXIS MODE<%
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+
else $error("SLAVER AXIS MODE<%0s> != BOTH",slaver.MODE);
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"ONLY_READ_to_BOTH":
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assert(slaver.MODE == "ONLY_READ")
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else $error("SLAVER AXIS MODE != ONLY_READ");
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@@ -25,9 +25,9 @@ module axi4_direct_verc #(
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`parameter_string IGNORE_LSIZE = "FALSE" //(* show = "false" *)
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)(
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(* axi4_up = "true" *)
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-
axi_inf.slaver
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+
axi_inf.slaver slaver_inf,
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(* axi4_down = "true" *)
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-
axi_inf.master
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+
axi_inf.master master_inf
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);
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@@ -36,60 +36,60 @@ import SystemPkg::*;
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initial begin
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#(1us);
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if(IGNORE_IDSIZE == "FALSE")begin
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assert(
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assert(slaver_inf.IDSIZE <= master_inf.IDSIZE) //idsize of slaver_inf can be smaller thane master_inf's
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else begin
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$error("SLAVER AXIS IDSIZE != MASTER AXIS IDSIZE");
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$finish;
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end
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end
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if(IGNORE_DSIZE == "FALSE")begin
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-
assert(
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assert(slaver_inf.DSIZE == master_inf.DSIZE)
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else $error("SLAVER AXIS DSIZE != MASTER AXIS DSIZE");
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end
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if(IGNORE_ASIZE == "FALSE")begin
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-
assert(
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assert(slaver_inf.ASIZE == master_inf.ASIZE)
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else $error("SLAVER AXIS ASIZE != MASTER AXIS ASIZE");
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end
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if(IGNORE_LSIZE == "FALSE")begin
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-
assert(
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assert(slaver_inf.LSIZE == master_inf.LSIZE)
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else $error("SLAVER AXIS LSIZE != MASTER AXIS LSIZE");
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end
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case(MODE)
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"BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
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assert(
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-
else $error("SLAVER AXIS MODE<%s> != BOTH",
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assert(slaver_inf.MODE =="BOTH" && SLAVER_MODE=="BOTH")
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else $error("SLAVER AXIS MODE<%s> != BOTH",slaver_inf.MODE);
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"ONLY_READ_to_BOTH":
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assert(
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assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
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else $error("SLAVER AXIS MODE != ONLY_READ");
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"ONLY_WRITE_to_BOTH","ONLY_WRITE_to_ONLY_WRITE":
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assert(
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assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
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else begin
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$error("SLAVER AXIS MODE != ONLY_WRITE");
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$finish;
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end
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"ONLY_READ_to_ONLY_READ":
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-
assert(
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assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
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else $error("SLAVER AXIS MODE != ONLY_READ");
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default:
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-
assert(
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+
assert(slaver_inf.MODE == "_____")
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else $error("SLAVER AXIS MODE ERROR") ;
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endcase
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case(MODE)
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"ONLY_WRITE_to_BOTH","ONLY_READ_to_BOTH","BOTH_to_BOTH":
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assert(
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assert(master_inf.MODE == "BOTH" && MASTER_MODE=="BOTH")
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else $error("MASTER AXIS MODE != BOTH");
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"BOTH_to_ONLY_READ":
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-
assert(
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+
assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
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else $error("MASTER AXIS MODE != ONLY_READ");
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"BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
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-
assert(
|
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+
assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
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else $error("MASTER AXIS MODE != ONLY_WRITE");
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"ONLY_READ_to_ONLY_READ":
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-
assert(
|
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+
assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
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else $error("MASTER AXIS MODE != ONLY_READ");
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default:
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-
assert(
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+
assert(master_inf.MODE == "_____")
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else $error("MASTER AXIS MODE ERROR");
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endcase
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@@ -97,49 +97,49 @@ end
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generate
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if(MASTER_MODE!="ONLY_READ")begin
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-
assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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-
assign
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-
assign
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-
assign
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+
assign master_inf.axi_awid = slaver_inf.axi_awid ;
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+
assign master_inf.axi_awaddr = slaver_inf.axi_awaddr ;
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+
assign master_inf.axi_awlen = slaver_inf.axi_awlen ;
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+
assign master_inf.axi_awsize = slaver_inf.axi_awsize ;
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104
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+
assign master_inf.axi_awburst = slaver_inf.axi_awburst;
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105
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+
assign master_inf.axi_awlock = slaver_inf.axi_awlock ;
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+
assign master_inf.axi_awcache = slaver_inf.axi_awcache;
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107
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+
assign master_inf.axi_awprot = slaver_inf.axi_awprot ;
|
108
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+
assign master_inf.axi_awqos = slaver_inf.axi_awqos ;
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109
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+
assign master_inf.axi_awvalid = slaver_inf.axi_awvalid;
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110
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+
assign slaver_inf.axi_awready = master_inf.axi_awready;
|
111
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+
assign master_inf.axi_wdata = slaver_inf.axi_wdata ;
|
112
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+
assign master_inf.axi_wstrb = slaver_inf.axi_wstrb ;
|
113
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+
assign master_inf.axi_wlast = slaver_inf.axi_wlast ;
|
114
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+
assign master_inf.axi_wvalid = slaver_inf.axi_wvalid ;
|
115
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+
assign slaver_inf.axi_wready = master_inf.axi_wready ;
|
116
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+
assign master_inf.axi_bready = slaver_inf.axi_bready ;
|
117
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+
assign slaver_inf.axi_bid = master_inf.axi_bid ;
|
118
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+
assign slaver_inf.axi_bresp = master_inf.axi_bresp ;
|
119
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+
assign slaver_inf.axi_bvalid = master_inf.axi_bvalid ;
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120
120
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end
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121
121
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endgenerate
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122
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generate
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if(MASTER_MODE!="ONLY_WRITE")begin
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-
assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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assign
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-
assign
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-
assign
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-
assign
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-
assign
|
126
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+
assign master_inf.axi_arid = slaver_inf.axi_arid ;
|
127
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+
assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
|
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+
assign master_inf.axi_arlen = slaver_inf.axi_arlen ;
|
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+
assign master_inf.axi_arsize = slaver_inf.axi_arsize ;
|
130
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+
assign master_inf.axi_arburst = slaver_inf.axi_arburst;
|
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+
assign master_inf.axi_arlock = slaver_inf.axi_arlock ;
|
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+
assign master_inf.axi_arcache = slaver_inf.axi_arcache;
|
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+
assign master_inf.axi_arprot = slaver_inf.axi_arprot ;
|
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+
assign master_inf.axi_arqos = slaver_inf.axi_arqos ;
|
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+
assign master_inf.axi_arvalid = slaver_inf.axi_arvalid;
|
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+
assign slaver_inf.axi_arready = master_inf.axi_arready;
|
137
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+
assign master_inf.axi_rready = slaver_inf.axi_rready ;
|
138
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+
assign slaver_inf.axi_rid = master_inf.axi_rid ;
|
139
|
+
assign slaver_inf.axi_rdata = master_inf.axi_rdata ;
|
140
|
+
assign slaver_inf.axi_rresp = master_inf.axi_rresp ;
|
141
|
+
assign slaver_inf.axi_rlast = master_inf.axi_rlast ;
|
142
|
+
assign slaver_inf.axi_rvalid = master_inf.axi_rvalid ;
|
143
143
|
end
|
144
144
|
endgenerate
|
145
145
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|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
|
descript:
|
6
6
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author : Cook.Darwin
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Version: VERA.0.0
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-
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creaded: XXXX.XX.XX
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madified:
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***********************************************/
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`timescale 1ns/1ps
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@@ -20,7 +20,7 @@ module axi4_dpram_cache #(
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//==========================================================================
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//-------- define ----------------------------------------------------------
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-
cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE(a_inf.DSIZE/8)) xram_inf();
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+
cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE((a_inf.DSIZE / 8))) xram_inf();
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axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(a_inf.DSIZE),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
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data_inf_c #(.DSIZE(a_inf.ASIZE+1)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
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@@ -5,7 +5,7 @@ _______________________________________
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descript:
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author : Cook.Darwin
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7
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Version: VERA.0.0
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-
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8
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+
creaded: XXXX.XX.XX
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9
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madified:
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***********************************************/
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`timescale 1ns/1ps
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@@ -56,7 +56,7 @@ logic stream_en;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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59
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-
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP))
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+
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R186 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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@@ -92,16 +92,16 @@ independent_clock_fifo #(
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/* output */.full (fifo_full )
|
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);
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axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
95
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-
/* output */.stream_en (stream_en
|
96
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-
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in
|
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-
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
|
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+
/* output */.stream_en (stream_en ),
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+
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
|
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+
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R186 )
|
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);
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vcs_axi4_comptable #(
|
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.ORIGIN ("master_wr_aux_no_resp" ),
|
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.TO ("master_wr" )
|
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-
)
|
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-
/* input */.origin (
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-
/* output */.to (axi_wr
|
102
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+
)vcs_axi4_comptable_axi_wr_aux_R282_axi_wr_inst(
|
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+
/* input */.origin (axi_wr_vcs_cp_R186 ),
|
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+
/* output */.to (axi_wr )
|
105
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);
|
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axis_valve_with_pipe #(
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.MODE ("BOTH" )
|
@@ -26,6 +26,13 @@ module odata_pool_axi4_A3 #(
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`include "define_macro.sv"
|
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+
initial begin
|
30
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+
assert (addr_size_inf.DSIZE == 64)
|
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+
else begin
|
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|
+
$display("addr_size_inf.DSIZE<%0d> != 64",addr_size_inf.DSIZE);
|
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+
end
|
34
|
+
end
|
35
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+
|
29
36
|
logic fifo_empty;
|
30
37
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logic fifo_full;
|
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38
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logic [31:0] fifo_addr;
|
@@ -5,7 +5,7 @@ _______________________________________
|
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5
5
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descript:
|
6
6
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author : Cook.Darwin
|
7
7
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Version: VERA.0.0
|
8
|
-
|
8
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+
creaded: XXXX.XX.XX
|
9
9
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madified:
|
10
10
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***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -31,7 +31,7 @@ logic one_long_stream;
|
|
31
31
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logic fifo_wr;
|
32
32
|
logic [IDSIZE+4-1:0] curr_id ;
|
33
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logic [LSIZE-1:0] curr_length ;
|
34
|
-
logic [(data_in.DSIZE-IDSIZE)-LSIZE-1:0] curr_addr ;
|
34
|
+
logic [(data_in.DSIZE - IDSIZE)-LSIZE-1:0] curr_addr ;
|
35
35
|
logic [LSIZE-1:0] wr_length ;
|
36
36
|
(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
|
37
37
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(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
|
@@ -5,7 +5,7 @@ _______________________________________
|
|
5
5
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descript:
|
6
6
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author : Cook.Darwin
|
7
7
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Version: VERA.0.0
|
8
|
-
|
8
|
+
creaded: XXXX.XX.XX
|
9
9
|
madified:
|
10
10
|
***********************************************/
|
11
11
|
`timescale 1ns/1ps
|
@@ -56,7 +56,7 @@ logic stream_en;
|
|
56
56
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
|
57
57
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
58
58
|
axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
59
|
-
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP))
|
59
|
+
axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1342 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
|
60
60
|
axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
|
61
61
|
//==========================================================================
|
62
62
|
//-------- instance --------------------------------------------------------
|
@@ -91,16 +91,16 @@ independent_clock_fifo #(
|
|
91
91
|
/* output */.full (fifo_full )
|
92
92
|
);
|
93
93
|
axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
|
94
|
-
/* output */.stream_en (stream_en
|
95
|
-
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in
|
96
|
-
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
|
94
|
+
/* output */.stream_en (stream_en ),
|
95
|
+
/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
|
96
|
+
/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1342 )
|
97
97
|
);
|
98
98
|
vcs_axi4_comptable #(
|
99
99
|
.ORIGIN ("master_wr_aux_no_resp" ),
|
100
100
|
.TO ("master_wr" )
|
101
|
-
)
|
102
|
-
/* input */.origin (
|
103
|
-
/* output */.to (axi_wr
|
101
|
+
)vcs_axi4_comptable_axi_wr_aux_R700_axi_wr_inst(
|
102
|
+
/* input */.origin (axi_wr_vcs_cp_R1342 ),
|
103
|
+
/* output */.to (axi_wr )
|
104
104
|
);
|
105
105
|
axis_valve_with_pipe #(
|
106
106
|
.MODE ("OUT" )
|
@@ -0,0 +1,154 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: 2021-04-03 12:04:15 +0800
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module axi_stream_split_channel (
|
14
|
+
input [15:0] split_len,
|
15
|
+
axi_stream_inf.slaver origin_inf,
|
16
|
+
axi_stream_inf.master first_inf,
|
17
|
+
axi_stream_inf.master end_inf
|
18
|
+
);
|
19
|
+
|
20
|
+
//==========================================================================
|
21
|
+
//-------- define ----------------------------------------------------------
|
22
|
+
logic clock;
|
23
|
+
logic rst_n;
|
24
|
+
logic addr;
|
25
|
+
logic new_last;
|
26
|
+
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
27
|
+
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
28
|
+
//==========================================================================
|
29
|
+
//-------- instance --------------------------------------------------------
|
30
|
+
axi_stream_interconnect_S2M #(
|
31
|
+
.NUM (2 )
|
32
|
+
)axi_stream_interconnect_S2M_inst(
|
33
|
+
/* input */.addr (addr ),
|
34
|
+
/* axi_stream_inf.slaver */.s00 (origin_inf_add_last ),
|
35
|
+
/* axi_stream_inf.master */.m00 (sub_origin_inf )
|
36
|
+
);
|
37
|
+
//==========================================================================
|
38
|
+
//-------- expression ------------------------------------------------------
|
39
|
+
|
40
|
+
axi_stream_inf #(.DSIZE(first_inf.DSIZE)) sub_first_inf[1-1:0](.aclk(first_inf.aclk),.aresetn(first_inf.aresetn),.aclken(1'b1));
|
41
|
+
|
42
|
+
|
43
|
+
axis_direct axis_direct_first_inf_inst0 (
|
44
|
+
/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
|
45
|
+
/* axi_stream_inf.master*/ .master (sub_first_inf[0])
|
46
|
+
);
|
47
|
+
|
48
|
+
|
49
|
+
axi_stream_inf #(.DSIZE(end_inf.DSIZE)) sub_end_inf[1-1:0](.aclk(end_inf.aclk),.aresetn(end_inf.aresetn),.aclken(1'b1));
|
50
|
+
|
51
|
+
|
52
|
+
axis_direct axis_direct_end_inf_inst0 (
|
53
|
+
/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[1]),
|
54
|
+
/* axi_stream_inf.master*/ .master (sub_end_inf[0])
|
55
|
+
);
|
56
|
+
//-------- CLOCKs Total 3 ----------------------
|
57
|
+
//--->> CheckClock <<----------------
|
58
|
+
logic cc_done_0,cc_same_0;
|
59
|
+
integer cc_afreq_0,cc_bfreq_0;
|
60
|
+
ClockSameDomain CheckPClock_inst_0(
|
61
|
+
/* input */ .aclk (origin_inf.aclk),
|
62
|
+
/* input */ .bclk (first_inf.aclk),
|
63
|
+
/* output logic */ .done (cc_done_0),
|
64
|
+
/* output logic */ .same (cc_same_0),
|
65
|
+
/* output integer */ .aFreqK (cc_afreq_0),
|
66
|
+
/* output integer */ .bFreqK (cc_bfreq_0)
|
67
|
+
);
|
68
|
+
|
69
|
+
initial begin
|
70
|
+
wait(cc_done_0);
|
71
|
+
assert(cc_same_0)
|
72
|
+
else begin
|
73
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_0, 1000000.0/cc_bfreq_0);
|
74
|
+
repeat(10)begin
|
75
|
+
@(posedge origin_inf.aclk);
|
76
|
+
end
|
77
|
+
$stop;
|
78
|
+
end
|
79
|
+
end
|
80
|
+
//---<< CheckClock >>----------------
|
81
|
+
|
82
|
+
//--->> CheckClock <<----------------
|
83
|
+
logic cc_done_1,cc_same_1;
|
84
|
+
integer cc_afreq_1,cc_bfreq_1;
|
85
|
+
ClockSameDomain CheckPClock_inst_1(
|
86
|
+
/* input */ .aclk (origin_inf.aclk),
|
87
|
+
/* input */ .bclk (end_inf.aclk),
|
88
|
+
/* output logic */ .done (cc_done_1),
|
89
|
+
/* output logic */ .same (cc_same_1),
|
90
|
+
/* output integer */ .aFreqK (cc_afreq_1),
|
91
|
+
/* output integer */ .bFreqK (cc_bfreq_1)
|
92
|
+
);
|
93
|
+
|
94
|
+
initial begin
|
95
|
+
wait(cc_done_1);
|
96
|
+
assert(cc_same_1)
|
97
|
+
else begin
|
98
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_1, 1000000.0/cc_bfreq_1);
|
99
|
+
repeat(10)begin
|
100
|
+
@(posedge origin_inf.aclk);
|
101
|
+
end
|
102
|
+
$stop;
|
103
|
+
end
|
104
|
+
end
|
105
|
+
//---<< CheckClock >>----------------
|
106
|
+
|
107
|
+
//======== CLOCKs Total 3 ======================
|
108
|
+
assign clock = origin_inf.aclk;
|
109
|
+
assign rst_n = origin_inf.aresetn;
|
110
|
+
|
111
|
+
always_ff@(posedge clock,negedge rst_n) begin
|
112
|
+
if(~rst_n)begin
|
113
|
+
addr <= 1'b0;
|
114
|
+
new_last <= 1'b0;
|
115
|
+
end
|
116
|
+
else begin
|
117
|
+
if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
|
118
|
+
new_last <= origin_inf.axis_tcnt==(split_len-2);
|
119
|
+
end
|
120
|
+
else begin
|
121
|
+
new_last <= new_last;
|
122
|
+
end
|
123
|
+
if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
|
124
|
+
addr <= 1'b0;
|
125
|
+
end
|
126
|
+
else if(origin_inf.axis_tcnt==(split_len-1)&&origin_inf.axis_tvalid && origin_inf.axis_tready)begin
|
127
|
+
addr <= 1'b1;
|
128
|
+
end
|
129
|
+
else begin
|
130
|
+
addr <= addr;
|
131
|
+
end
|
132
|
+
end
|
133
|
+
end
|
134
|
+
|
135
|
+
assign origin_inf_add_last.axis_tdata = origin_inf.axis_tdata;
|
136
|
+
assign origin_inf_add_last.axis_tvalid = origin_inf.axis_tvalid;
|
137
|
+
assign origin_inf_add_last.axis_tuser = origin_inf.axis_tuser;
|
138
|
+
assign origin_inf_add_last.axis_tkeep = origin_inf.axis_tkeep;
|
139
|
+
assign origin_inf_add_last.axis_tlast = origin_inf.axis_tlast|new_last;
|
140
|
+
assign origin_inf.axis_tready = origin_inf_add_last.axis_tready;
|
141
|
+
|
142
|
+
|
143
|
+
axis_direct axis_direct_first_inf_instMM (
|
144
|
+
/* axi_stream_inf.slaver*/ .slaver (sub_first_inf[0]),
|
145
|
+
/* axi_stream_inf.master*/ .master (first_inf)
|
146
|
+
);
|
147
|
+
|
148
|
+
|
149
|
+
axis_direct axis_direct_end_inf_instMM (
|
150
|
+
/* axi_stream_inf.slaver*/ .slaver (sub_end_inf[0]),
|
151
|
+
/* axi_stream_inf.master*/ .master (end_inf)
|
152
|
+
);
|
153
|
+
|
154
|
+
endmodule
|