axi_tdl 0.1.1 → 0.1.3

data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb

@@ -88,7 +88,7 @@ module TdlSpace
                 dimension = []
             end
             name = to_inp(name)
-            belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
+            rel = belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
         end
 
         def wire 

data/lib/tdl/sdlmodule/sdlmodule_instance.rb

@@ -448,6 +448,9 @@ class SdlModule
         # @ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs)
         @instance_cnt ||= 0
         inst_p = SdlInst.new(origin:self,name:name)
+     
+        @instances ||= []
+        @instances << inst_p
 
         @port_params.each do |k,v|
             inst_p.inst_param_hash[k.to_s] = nil

data/lib/tdl/sdlmodule/sdlmodule_port_define.rb

@@ -65,7 +65,7 @@ class SdlModule
         if value.is_a? Float
             type = :real
         end
-        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show)
+        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show, belong_to_module: self)
         add_to_new_module("@port_params",tmp)
         add_method_to_itgt(name,tmp)
         tmp
@@ -87,7 +87,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
-            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
+            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
             add_method_to_itgt(name,tmp)
             tmp
@@ -109,7 +109,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic')
+            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic', belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -136,7 +136,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' )
+            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' , belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -150,7 +150,7 @@ class SdlModule
     def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize)
+        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_clocks",a)
 
         if block_given?
@@ -164,7 +164,7 @@ class SdlModule
     def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize)
+        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_resets",a)
         # define_method(name){ a }
         add_method_to_itgt(name,a)

data/lib/tdl/sdlmodule/sdlmodule_varible.rb

@@ -13,25 +13,25 @@ class DefXp
     end
 
     def logic(name:"tmp",dsize:1,port:false,default:nil,msb_high:true,dimension:[],type:"logic",&block)
-        lg = Logic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type)
+        lg = Logic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type, belong_to_module: @sdlmodule)
         var_common(lg,&block)
         add_method_to_itgt(name,lg)
     end
 
     def clock(name:"",freqM:100,dsize:1,&block)
-        a = Clock.new(name:name,freqM:freqM,dsize:dsize)
+        a = Clock.new(name:name,freqM:freqM,dsize:dsize, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
 
     def reset(name:"",active:"low",dsize:1,&block)
-        a = Reset.new(name:name,active:active,dsize:dsize)
+        a = Reset.new(name:name,active:active,dsize:dsize, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
 
     def parameter(name:"P",value:100,local:false,type:nil,&block)
-        a = Parameter.new(name:name,value:value,local:local,port:false,show:true,type:type)
+        a = Parameter.new(name:name,value:value,local:local,port:false,show:true,type:type, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
@@ -77,12 +77,12 @@ class DefXp
     # end
 
     def mailbox(name:'mbox',depth:100,&block)
-        a = MailBox.new(name:name,depth:depth)
+        a = MailBox.new(name:name,depth:depth, belong_to_module: @sdlmodule)
         var_common(a,&block)
     end
 
     def debuglogic(name:"tmp",dsize:1,port:false,default:nil,msb_high:true,dimension:[],type:"logic",&block)
-        lg = DebugLogic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type)
+        lg = DebugLogic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type, belong_to_module: @sdlmodule)
         var_common(lg,&block)
         add_method_to_itgt(name,lg)
     end

data/lib/tdl/sdlmodule/test_unit_module.rb

@@ -43,6 +43,8 @@ class SdlModule
     end
 
     def gen_dev_wave_tcl ## 返回一个[]
+        return ['','',''] unless TopModule.sim
+
         dve_tcl_hash = {}
         track_signals_hash.each do |flag, base_ele_bhash|
             base_elms = []
@@ -50,6 +52,7 @@ class SdlModule
             intf_elms_name = []
             base_ele_bhash.each do |ele, sub_filter_block|
                 _ref_paths = ele.path_refs(&@__track_filter_block__)
+                _ref_paths.uniq!
 
                 if sub_filter_block
                     _ref_paths = _ref_paths.select do |e| 
@@ -143,6 +146,8 @@ class SdlModule
 
                 sub_hash.each do |ele, sub_filter_block|
                     _root_refs = ele.path_refs(&filter_block)
+                    _root_refs.uniq!
+                    
                     if sub_filter_block 
                         _root_refs.select! do |e| sub_filter_block.call(e) end
                     end    

data/lib/tdl/tdlerror/tdlerror.rb

@@ -4,6 +4,6 @@ class TdlError < ScriptError
         head_str0 = String.new("\n+_____________________________________________+\n")
         head_str1 = "\n|----------------TDL ERROR--------------------|\n"
         end_str0  = "\n+================TDL ERROR====================+\n"
-        super(head_str0.concat(head_str1).concat(arge.to_s[0,255]+end_str0))
+        super(head_str0.concat(head_str1).concat(arge.to_s[0,255]).concat(end_str0))
     end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: axi_tdl
 version: !ruby/object:Gem::Version
-  version: 0.1.1
+  version: 0.1.3
 platform: ruby
 authors:
 - Cook.Darwin
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2021-03-21 00:00:00.000000000 Z
+date: 2021-04-03 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rake
@@ -208,6 +208,7 @@ files:
 - lib/axi/AXI_stream/axi_stream_partition_A1.sv
 - lib/axi/AXI_stream/axi_stream_planer.sv
 - lib/axi/AXI_stream/axi_stream_split_channel.rb
+- lib/axi/AXI_stream/axi_stream_split_channel.sv
 - lib/axi/AXI_stream/axi_streams_combin.sv
 - lib/axi/AXI_stream/axi_streams_combin_A1.sv
 - lib/axi/AXI_stream/axi_streams_scaler.sv
@@ -229,8 +230,10 @@ files:
 - lib/axi/AXI_stream/axis_head_cut.sv
 - lib/axi/AXI_stream/axis_head_cut_verb.sv
 - lib/axi/AXI_stream/axis_head_cut_verc.rb
+- lib/axi/AXI_stream/axis_head_cut_verc.sv
 - lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv
 - lib/axi/AXI_stream/axis_insert_copy.rb
+- lib/axi/AXI_stream/axis_insert_copy.sv
 - lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv
@@ -239,18 +242,20 @@ files:
 - lib/axi/AXI_stream/axis_length_split.sv
 - lib/axi/AXI_stream/axis_length_split_with_addr.sv
 - lib/axi/AXI_stream/axis_length_split_with_user.sv
-- lib/axi/AXI_stream/axis_length_split_writh_user.sv
 - lib/axi/AXI_stream/axis_link_trigger.sv
 - lib/axi/AXI_stream/axis_master_empty.sv
 - lib/axi/AXI_stream/axis_mirror_to_master.sv
 - lib/axi/AXI_stream/axis_mirrors.sv
 - lib/axi/AXI_stream/axis_orthogonal.sv
 - lib/axi/AXI_stream/axis_pipe_sync_seam.rb
+- lib/axi/AXI_stream/axis_pipe_sync_seam.sv
 - lib/axi/AXI_stream/axis_ram_buffer.sv
 - lib/axi/AXI_stream/axis_rom_contect.rb
 - lib/axi/AXI_stream/axis_rom_contect.sv
 - lib/axi/AXI_stream/axis_rom_contect_sim.rb
+- lib/axi/AXI_stream/axis_rom_contect_sim.sv
 - lib/axi/AXI_stream/axis_sim_master_model.rb
+- lib/axi/AXI_stream/axis_sim_master_model.sv
 - lib/axi/AXI_stream/axis_sim_slaver_model.rb
 - lib/axi/AXI_stream/axis_sim_verify_by_coe.sv
 - lib/axi/AXI_stream/axis_slaver_empty.sv
@@ -258,6 +263,7 @@ files:
 - lib/axi/AXI_stream/axis_slaver_pipe_A1.sv
 - lib/axi/AXI_stream/axis_slaver_vector_empty.sv
 - lib/axi/AXI_stream/axis_split_channel_verb.rb
+- lib/axi/AXI_stream/axis_split_channel_verb.sv
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.rb
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.sv
 - lib/axi/AXI_stream/axis_to_data_inf.sv
@@ -546,6 +552,31 @@ files:
 - lib/axi/video_interface/video_interface.sv
 - lib/axi_tdl.rb
 - lib/axi_tdl/version.rb
+- lib/public_atom_module/CheckPClock.sv
+- lib/public_atom_module/LICENSE.md
+- lib/public_atom_module/altera_xilinx_always_block_sw.rb
+- lib/public_atom_module/bits_decode.sv
+- lib/public_atom_module/bits_decode_verb.sv
+- lib/public_atom_module/bits_decode_verb_sdl.rb
+- lib/public_atom_module/broaden.v
+- lib/public_atom_module/broaden_and_cross_clk.v
+- lib/public_atom_module/ceiling.v
+- lib/public_atom_module/ceiling_A1.v
+- lib/public_atom_module/clock_rst.sv
+- lib/public_atom_module/cross_clk_sync.v
+- lib/public_atom_module/edge_generator.v
+- lib/public_atom_module/flooring.v
+- lib/public_atom_module/latch_data.v
+- lib/public_atom_module/latency.v
+- lib/public_atom_module/latency_dynamic.v
+- lib/public_atom_module/latency_long.v
+- lib/public_atom_module/latency_verb.v
+- lib/public_atom_module/once_event.sv
+- lib/public_atom_module/pipe_reg.v
+- lib/public_atom_module/pipe_reg_2write_ports.v
+- lib/public_atom_module/sim/clock_rst_verb.sv
+- lib/public_atom_module/sim/latency_long_tb.sv
+- lib/public_atom_module/sim/latency_long_tb.sv.bak
 - lib/spec/spec_helper.rb
 - lib/tdl/LICENSE
 - lib/tdl/Logic/Logic.tar.gz

data/lib/axi/AXI_stream/axis_length_split_writh_user.sv

@@ -1,87 +0,0 @@
-/**********************************************
-______________   ______________
-______________ X ______________
-______________  ______________
-
-descript:
-author : Cook.Darwin
-Version: VERA.0.X 2018/1/25 
-    use axis_user to detect last
-creaded: 2017/5/19 
-madified:
-***********************************************/
-`timescale 1ns/1ps
-(* axi_stream = "true" *)
-module axis_length_split_with_user (
-    input [31:0]           length,      ////[0] mean 0 len
-    (* up_stream = "true" *)
-    axi_stream_inf.slaver  axis_in,
-    (* down_stream = "true" *)
-    axi_stream_inf.master  axis_out
-);
-
-wire    clock,rst_n,clken;
-
-assign  clock   = axis_in.aclk;
-assign  rst_n   = axis_in.aresetn;
-assign  clken   = axis_in.aclken;
-
-axi_stream_inf #(.DSIZE(axis_in.DSIZE)) axis_pre (.aclk(clock),.aresetn(rst_n),.aclken(clken));
-
-
-logic [31:0]        cnt;
-
-always@(posedge clock,negedge rst_n)
-    if(~rst_n)  cnt     <= '0;
-    else begin
-        if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
-                cnt     <= '0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready && (cnt >= (length-1)))
-                cnt     <= '0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready)
-                cnt     <= cnt + 1'b1;
-        else    cnt     <= cnt;
-    end
-
-logic   new_last;
-
-always@(posedge clock,negedge rst_n)
-    if(~rst_n)  new_last    <= 1'b0;
-    else begin
-        if(axis_in.axis_tvalid  && axis_in.axis_tready && (new_last||axis_in.axis_tlast))
-                new_last    <= 1'b0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready && cnt==(length-2))
-                new_last    <= 1'b1;
-        else    new_last    <= new_last;
-    end
-
-// logic   mark_tail;
-//
-// always@(posedge clock,negedge rst_n)
-//     if(~rst_n)  mark_tail   <= 1'b0;
-//     else begin
-//         if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
-//                 mark_tail   <= 1'b0;
-//         else if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tcnt==(length-1))
-//                 mark_tail   <= 1'b1;
-//         else    mark_tail   <= mark_tail;
-//     end
-
-assign axis_pre.axis_tvalid = axis_in.axis_tvalid;
-assign axis_pre.axis_tdata  = axis_in.axis_tdata;
-assign axis_pre.axis_tlast  = new_last || axis_in.axis_tlast;
-assign axis_pre.axis_tkeep  = axis_in.axis_tkeep;
-// assign axis_pre.axis_tuser  = axis_in.axis_tuser;
-assign axis_pre.axis_tuser  = axis_in.axis_tlast;
-assign axis_in.axis_tready  = axis_pre.axis_tready;
-
-axis_connect_pipe axis_connect_pipe_inst(
-/*  axi_stream_inf.slaver  */  .axis_in     (axis_pre   ),
-/*  axi_stream_inf.master  */  .axis_out    (axis_out   )
-);
-
-int out_cnt;
-
-assign out_cnt = axis_out.axis_tcnt;
-
-endmodule