HDLRuby 3.1.0 → 3.3.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/HDLRuby.gemspec +1 -0
- data/README.html +2330 -2670
- data/README.md +400 -100
- data/ext/hruby_sim/hruby_rcsim_build.c +402 -3
- data/ext/hruby_sim/hruby_sim.h +2 -1
- data/ext/hruby_sim/hruby_sim_calc.c +34 -7
- data/ext/hruby_sim/hruby_sim_core.c +15 -5
- data/ext/hruby_sim/hruby_sim_tree_calc.c +112 -23
- data/lib/HDLRuby/hdr_samples/c_program/echo.c +33 -0
- data/lib/HDLRuby/hdr_samples/comparison_bench.rb +2 -2
- data/lib/HDLRuby/hdr_samples/counter_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +8 -7
- data/lib/HDLRuby/hdr_samples/dff_properties.rb +2 -0
- data/lib/HDLRuby/hdr_samples/enum_as_param.rb +52 -0
- data/lib/HDLRuby/hdr_samples/linear_test.rb +2 -0
- data/lib/HDLRuby/hdr_samples/logic_bench.rb +6 -0
- data/lib/HDLRuby/hdr_samples/mei8.rb +6 -6
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +6 -6
- data/lib/HDLRuby/hdr_samples/memory_test.rb +2 -0
- data/lib/HDLRuby/hdr_samples/named_sub.rb +9 -5
- data/lib/HDLRuby/hdr_samples/ram.rb +7 -6
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +2 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/echo.rb +9 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/stdrw.rb +6 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_cpu_terminal.rb +614 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb +32 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb +33 -0
- data/lib/HDLRuby/hdr_samples/struct.rb +15 -3
- data/lib/HDLRuby/hdr_samples/with_board.rb +63 -0
- data/lib/HDLRuby/hdr_samples/with_bram.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_channel.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_channel_other.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_class.rb +3 -1
- data/lib/HDLRuby/hdr_samples/with_clocks.rb +42 -0
- data/lib/HDLRuby/hdr_samples/with_connector.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +6 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint_adv.rb +73 -0
- data/lib/HDLRuby/hdr_samples/with_leftright.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_of.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_program_c.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb +234 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb +23 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb +58 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb +56 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +17 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_channel.rb +58 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +10 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +18 -4
- data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +2 -4
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +2 -1
- data/lib/HDLRuby/hdrcc.rb +72 -21
- data/lib/HDLRuby/hruby_error.rb +13 -0
- data/lib/HDLRuby/hruby_high.rb +125 -26
- data/lib/HDLRuby/hruby_low.rb +171 -3
- data/lib/HDLRuby/hruby_low2programs.rb +47 -0
- data/lib/HDLRuby/hruby_low_resolve.rb +3 -2
- data/lib/HDLRuby/hruby_low_without_namespace.rb +133 -5
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +1 -1
- data/lib/HDLRuby/hruby_rcsim.rb +113 -6
- data/lib/HDLRuby/hruby_serializer.rb +2 -1
- data/lib/HDLRuby/hruby_verilog.rb +94 -20
- data/lib/HDLRuby/hruby_verilog_name.rb +3 -17
- data/lib/HDLRuby/std/clocks.rb +118 -50
- data/lib/HDLRuby/std/fixpoint.rb +2 -2
- data/lib/HDLRuby/std/function_generator.rb +1 -1
- data/lib/HDLRuby/std/linear.rb +7 -7
- data/lib/HDLRuby/std/sequencer.rb +263 -13
- data/lib/HDLRuby/std/sequencer_channel.rb +90 -0
- data/lib/HDLRuby/std/sequencer_func.rb +28 -15
- data/lib/HDLRuby/std/std.rb +6 -0
- data/lib/HDLRuby/ui/hruby_board.rb +1079 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/lib/c/Rakefile +8 -0
- data/lib/c/cHDL.h +12 -0
- data/lib/c/extconf.rb +7 -0
- data/lib/rubyHDL.rb +33 -0
- data/tuto/gui_accum.png +0 -0
- data/tuto/gui_board.png +0 -0
- data/tuto/tutorial_sw.html +2263 -1890
- data/tuto/tutorial_sw.md +957 -62
- metadata +43 -5
- data/README.pdf +0 -0
- data/tuto/tutorial_sw.pdf +0 -0
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# A benchmark for testing the use of Ruby software code.
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system :with_ruby_thread do
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inner :clk, :rst, :req, :ack
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[8].inner :count
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program(:ruby,:boot) do
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actport rst.negedge
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inport din: count
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outport ack: ack
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code "ruby_program/sw_log.rb"
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end
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program(:ruby,:log) do
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actport req.posedge
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code "ruby_program/sw_log.rb"
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end
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par(ack.posedge) { count <= count + 1 }
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timed do
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clk <= 0
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rst <= 0
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count <= 0
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req <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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repeat(100) do
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clk <= 1
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req <= 1
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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req <= 0
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!10.ns
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clk <= 0
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!10.ns
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end
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end
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end
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@@ -16,6 +16,7 @@ include HDLRuby::High::Std
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# - One sequencer puts the sum of two arrays in a third one.
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# - One sequencer iterates over two arrays.
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# - One sequencer iterates downward.
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# - One sequencer checks sub iterators (HDLRuby special).
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system :my_seqencer do
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inner :clk,:rst
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# hprint(")2 res6=",res6,"\n")
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end
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[8].inner :res7,:res8
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sequencer(clk.posedge,rst) do
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res7 <= 0
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res8 <= 0
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ar0.seach_range(0..3) do |elem|
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res7 <= elem
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end
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ar0.seach_range(4..9) do |elem|
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res7 <= elem
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end
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(_h00.._h07).seach_range(1..4) do |elem|
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res8 <= elem
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end
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end
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timed do
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clk <= 0
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require 'std/sequencer.rb'
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include HDLRuby::High::Std
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# Checking the usage of sequencers' channels.
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system :my_seqencer do
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inner :clk,:rst,filled: 0
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bit[16][-16].inner :mem
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[16].inner :res0, :res1, :res2, :res3
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ch_read = schannel(bit[16],16) do |i|
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mem[i]
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end
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ch_write = schannel(bit[16],16) do |i,val|
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mem[i] <= val
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end
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sequencer(clk.posedge,rst) do
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16.stimes { |i| ch_write.snext!(i) }
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filled <= 1
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16.stimes do |i|
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res0 <= ch_read.snext
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res1 <= ch_read[15-i]
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end
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end
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sequencer(clk.posedge,rst) do
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swhile(~filled);
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16.stimes do |i|
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res2 <= ch_read.snext
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res3 <= ch_read[15-i]
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end
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end
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timed do
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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repeat(100) do
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!10.ns
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clk <= ~clk
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end
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end
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end
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# - The twenty nineth sequencer checks stake and stake_while
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# - The thirtieth sequencer checks suniq
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# - The thirty first sequencer checks szip
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# - The thirty second sequnecer checks seach_nexts (HDLRuby special)
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#
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# __WARNING__: All the operations on enumerators generate their own result
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# signal. Therefore, in a real circuit, there is no need to
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# hprint("}1 res52=",res52," res53=",res53,"\n")
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end
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[8].inner :res54,:res55
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sequencer(clk.posedge,rst) do
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res54 <= 0
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res55 <= 0
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vals.seach_nexts(6) { |i| res54 <= i }
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res55 <= vals.seach_nexts(4).ssum
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end
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timed do
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data <= mem[addr]
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mem_enum = senumerator(bit[8],8) do |i|
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mem_enum = senumerator(bit[8],8) do |i,val|
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if val then
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# Write
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mem[i] <= val
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step
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val
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else
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# Read
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addr <= i
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step
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data
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end
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end
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sequencer(clk.posedge,rst) do
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# hprint("~0\n")
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res6 <= 0
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res6 <= mem_enum.ssum
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mem_enum.srewind
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mem_enum.snext!(_hAA)
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mem_enum.snext!(_hBB)
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mem_enum.srewind
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res6 <= mem_enum.snext
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res6 <= mem_enum.snext
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# hprint("~1 res6=",res6,"\n")
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end
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require 'std/sequencer_func.rb'
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include HDLRuby::High::Std
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# A factorial with default stack depth.
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sdef(:fact) do |n|
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5.stimes do |i|
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val <= i
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res <= fact(val)
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hprint("res=",res,"\n")
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end
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hprint("Going to overflow...\n")
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4.stimes do |i|
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val <= i
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res <= fact_over(val)
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hprint("res=",res,"\n")
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end
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hprint("stack_overflow_error=",stack_overflow_error,"\n")
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end
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data/lib/HDLRuby/hdrcc.rb
CHANGED
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begin
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rescue LoadError
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# begin
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# # We can check the memory.
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# require 'get_process_mem'
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# $memory_check = GetProcessMem.new
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# def show_mem
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# " | "+$memory_check.bytes.to_s+"B"
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# end
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# rescue LoadError
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# # We cannot check the memory.
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def show_mem
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""
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end
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# end
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require 'fileutils'
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require 'HDLRuby/version.rb'
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# Global flags
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$sim = false # Tells if hdrcc is in simulation mode
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$gen = false # Tells if hdrcc is in hardware generation mode
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##
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# HDLRuby compiler interface program
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opts.on("-r", "--hdr","Output in HDLRuby format") do |v|
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$options[:hdr] = v
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end
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opts.on("-C", "--clang","Output in C format (simulator)") do |v|
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end
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|
370
|
-
opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
|
|
371
|
-
|
|
372
|
-
end
|
|
370
|
+
# opts.on("-C", "--clang","Output in C format (simulator, deprecated)") do |v|
|
|
371
|
+
# $options[:clang] = v
|
|
372
|
+
# $options[:multiple] = v
|
|
373
|
+
# end
|
|
374
|
+
# opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
|
|
375
|
+
# $options[:allocate] = v
|
|
376
|
+
# end
|
|
373
377
|
opts.on("-S","--sim","Default simulator (hybrid C-Ruby)") do |v|
|
|
374
378
|
$options[:rcsim] = v
|
|
375
379
|
$options[:multiple] = v
|
|
380
|
+
$sim = true
|
|
376
381
|
end
|
|
377
|
-
opts.on("--csim","Standalone C-based simulator") do |v|
|
|
382
|
+
opts.on("--csim","Standalone C-based simulator (deprecated)") do |v|
|
|
378
383
|
$options[:clang] = v
|
|
379
384
|
$options[:multiple] = v
|
|
380
385
|
$options[:csim] = v
|
|
386
|
+
$sim = true
|
|
381
387
|
end
|
|
382
|
-
opts.on("--rsim","Ruby-based simulator") do |v|
|
|
388
|
+
opts.on("--rsim","Ruby-based simulator (deprecated)") do |v|
|
|
383
389
|
$options[:rsim] = v
|
|
384
390
|
$options[:multiple] = v
|
|
391
|
+
$sim = true
|
|
385
392
|
end
|
|
386
393
|
opts.on("--rcsim","Hybrid C-Ruby-based simulator") do |v|
|
|
387
394
|
$options[:rcsim] = v
|
|
388
395
|
$options[:multiple] = v
|
|
396
|
+
$sim = true
|
|
389
397
|
end
|
|
390
398
|
opts.on("--mute", "The simulator will not generate any output") do |v|
|
|
391
399
|
$options[:mute] = v
|
|
@@ -393,15 +401,44 @@ $optparse = OptionParser.new do |opts|
|
|
|
393
401
|
opts.on("--vcd", "The simulator will generate a vcd file") do |v|
|
|
394
402
|
$options[:vcd] = v
|
|
395
403
|
end
|
|
404
|
+
opts.on("--ch dir", "Generates the files for compiling a software extension") do |dir|
|
|
405
|
+
# Check the target directory.
|
|
406
|
+
if !dir or dir.empty? then
|
|
407
|
+
raise "Need a program name for generating the compiling files."
|
|
408
|
+
end
|
|
409
|
+
# Create the source path.
|
|
410
|
+
src_path = File.dirname(__FILE__) + "/../c/"
|
|
411
|
+
# Create the target directory.
|
|
412
|
+
Dir.mkdir(dir) unless File.exist?(dir)
|
|
413
|
+
# Copy the header files.
|
|
414
|
+
## FileUtils.copy(src_path + "cHDL.h",dir)
|
|
415
|
+
# And update it with any empty initialization function
|
|
416
|
+
# (not used but required for compiling for windows).
|
|
417
|
+
lines = nil
|
|
418
|
+
File.open(src_path + "cHDL.h","r") {|f| lines = f.readlines }
|
|
419
|
+
lines = ["void Init_#{dir}() {}\n\n"] + lines
|
|
420
|
+
File.open(dir + "/" + "cHDL.h", "w") {|f| lines.each {|l| f.write(l) } }
|
|
421
|
+
# Copy and modify the files for rake.
|
|
422
|
+
["extconf.rb", "Rakefile"].each do |fname|
|
|
423
|
+
lines = nil
|
|
424
|
+
File.open(src_path + fname,"r") {|f| lines = f.readlines }
|
|
425
|
+
# puts "Checking dir: #{File.dirname(__FILE__)+"/../hruby_sim/"}"
|
|
426
|
+
lines = ["C_PROGRAM = '#{dir}'\nRCSIM_DIR = '#{File.dirname(__FILE__)+"/../hruby_sim/"}'\n"] + lines
|
|
427
|
+
File.open(dir + "/" + fname, "w") {|f| lines.each {|l| f.write(l) } }
|
|
428
|
+
end
|
|
429
|
+
exit
|
|
430
|
+
end
|
|
396
431
|
opts.on("-v", "--verilog","Output in Verlog HDL format") do |v|
|
|
397
432
|
$options[:verilog] = v
|
|
398
433
|
$options[:multiple] = v
|
|
434
|
+
$gen = true
|
|
399
435
|
end
|
|
400
436
|
opts.on("-V", "--vhdl","Output in VHDL format") do |v|
|
|
401
437
|
HDLRuby::Low::Low2VHDL.vhdl08 = false
|
|
402
438
|
$options[:vhdl] = v
|
|
403
439
|
$options[:multiple] = v
|
|
404
440
|
$options[:vhdl08] = false
|
|
441
|
+
$gen = true
|
|
405
442
|
end
|
|
406
443
|
opts.on("-A", "--alliance","Output in Alliance-compatible VHDL format") do |v|
|
|
407
444
|
HDLRuby::Low::Low2VHDL.vhdl08 = false
|
|
@@ -410,12 +447,14 @@ $optparse = OptionParser.new do |opts|
|
|
|
410
447
|
$options[:alliance] = v
|
|
411
448
|
$options[:multiple] = v
|
|
412
449
|
$options[:vhdl08] = false
|
|
450
|
+
$gen = true
|
|
413
451
|
end
|
|
414
452
|
opts.on("-U", "--vhdl08","Output in VHDL'08 format") do |v|
|
|
415
453
|
HDLRuby::Low::Low2VHDL.vhdl08 = true
|
|
416
454
|
$options[:vhdl] = v
|
|
417
455
|
$options[:multiple] = v
|
|
418
456
|
$options[:vhdl08] = true
|
|
457
|
+
$gen = true
|
|
419
458
|
end
|
|
420
459
|
opts.on("-s", "--syntax","Output the Ruby syntax tree") do |s|
|
|
421
460
|
$options[:syntax] = s
|
|
@@ -454,14 +493,26 @@ $optparse = OptionParser.new do |opts|
|
|
|
454
493
|
$options[:dump] = v
|
|
455
494
|
$options[:multiple] = v
|
|
456
495
|
end
|
|
457
|
-
opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one,
|
|
496
|
+
opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one, then exit") do
|
|
458
497
|
FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples","./hdr_samples")
|
|
498
|
+
FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/c_program","./hdr_samples/c_program")
|
|
499
|
+
FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/ruby_program","./hdr_samples/ruby_program")
|
|
500
|
+
exit
|
|
501
|
+
end
|
|
502
|
+
opts.on("--get-tuto", "Copy the tutorial directory (tuto) to current one, then exit") do
|
|
503
|
+
FileUtils.copy_entry(File.dirname(__FILE__) + "../../tuto","./tuto")
|
|
459
504
|
exit
|
|
460
505
|
end
|
|
461
506
|
opts.on("--version", "Show the version of HDLRuby, then exit") do |v|
|
|
462
507
|
puts VERSION
|
|
463
508
|
exit
|
|
464
509
|
end
|
|
510
|
+
opts.on("--path","Shows the path where HDLRuby is install.") do |v|
|
|
511
|
+
require 'pathname'
|
|
512
|
+
path = Pathname.new(__FILE__ + "../../../../").cleanpath
|
|
513
|
+
puts path.to_s
|
|
514
|
+
exit
|
|
515
|
+
end
|
|
465
516
|
# opts.on_tail("-h", "--help", "Show this message") do
|
|
466
517
|
opts.on("-h", "--help", "Show this message") do
|
|
467
518
|
puts opts
|
|
@@ -571,7 +622,7 @@ if $options[:syntax] then
|
|
|
571
622
|
$output << $loader.show_all
|
|
572
623
|
exit
|
|
573
624
|
end
|
|
574
|
-
HDLRuby.show "#{Time.now}#{show_mem}"
|
|
625
|
+
# HDLRuby.show "#{Time.now}#{show_mem}"
|
|
575
626
|
HDLRuby.show "##### Starting parser #####"
|
|
576
627
|
|
|
577
628
|
if $options[:debug] then
|
data/lib/HDLRuby/hruby_error.rb
CHANGED
|
@@ -5,6 +5,10 @@ module HDLRuby
|
|
|
5
5
|
class AnyError < ::StandardError
|
|
6
6
|
end
|
|
7
7
|
|
|
8
|
+
## The HDLRuby UI error class.
|
|
9
|
+
class UIError < ::StandardError
|
|
10
|
+
end
|
|
11
|
+
|
|
8
12
|
module High
|
|
9
13
|
## The HDLRuby::High error class.
|
|
10
14
|
class AnyError < HDLRuby::AnyError
|
|
@@ -13,12 +17,21 @@ module HDLRuby
|
|
|
13
17
|
## The HDLRuby error class replacing the standard Ruby NoMethodError
|
|
14
18
|
class NotDefinedError < AnyError
|
|
15
19
|
end
|
|
20
|
+
|
|
21
|
+
## The HDLRuby::High UI error class.
|
|
22
|
+
class UIError < HDLRuby::UIError
|
|
23
|
+
end
|
|
16
24
|
end
|
|
17
25
|
|
|
26
|
+
|
|
18
27
|
module Low
|
|
19
28
|
## The HDLRuby::Low error class.
|
|
20
29
|
class AnyError < HDLRuby::AnyError
|
|
21
30
|
end
|
|
31
|
+
|
|
32
|
+
## The HDLRuby::Low UI error class.
|
|
33
|
+
class UIError < HDLRuby::UIError
|
|
34
|
+
end
|
|
22
35
|
end
|
|
23
36
|
|
|
24
37
|
## Execution context for processing error messages in +code+.
|