HDLRuby 3.1.0 → 3.3.0

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Files changed (88) hide show
  1. checksums.yaml +4 -4
  2. data/HDLRuby.gemspec +1 -0
  3. data/README.html +2330 -2670
  4. data/README.md +400 -100
  5. data/ext/hruby_sim/hruby_rcsim_build.c +402 -3
  6. data/ext/hruby_sim/hruby_sim.h +2 -1
  7. data/ext/hruby_sim/hruby_sim_calc.c +34 -7
  8. data/ext/hruby_sim/hruby_sim_core.c +15 -5
  9. data/ext/hruby_sim/hruby_sim_tree_calc.c +112 -23
  10. data/lib/HDLRuby/hdr_samples/c_program/echo.c +33 -0
  11. data/lib/HDLRuby/hdr_samples/comparison_bench.rb +2 -2
  12. data/lib/HDLRuby/hdr_samples/counter_bench.rb +1 -1
  13. data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +8 -7
  14. data/lib/HDLRuby/hdr_samples/dff_properties.rb +2 -0
  15. data/lib/HDLRuby/hdr_samples/enum_as_param.rb +52 -0
  16. data/lib/HDLRuby/hdr_samples/linear_test.rb +2 -0
  17. data/lib/HDLRuby/hdr_samples/logic_bench.rb +6 -0
  18. data/lib/HDLRuby/hdr_samples/mei8.rb +6 -6
  19. data/lib/HDLRuby/hdr_samples/mei8_bench.rb +6 -6
  20. data/lib/HDLRuby/hdr_samples/memory_test.rb +2 -0
  21. data/lib/HDLRuby/hdr_samples/named_sub.rb +9 -5
  22. data/lib/HDLRuby/hdr_samples/ram.rb +7 -6
  23. data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +2 -0
  24. data/lib/HDLRuby/hdr_samples/ruby_program/echo.rb +9 -0
  25. data/lib/HDLRuby/hdr_samples/ruby_program/stdrw.rb +6 -0
  26. data/lib/HDLRuby/hdr_samples/ruby_program/sw_cpu_terminal.rb +614 -0
  27. data/lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb +32 -0
  28. data/lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb +33 -0
  29. data/lib/HDLRuby/hdr_samples/struct.rb +15 -3
  30. data/lib/HDLRuby/hdr_samples/with_board.rb +63 -0
  31. data/lib/HDLRuby/hdr_samples/with_bram.rb +1 -1
  32. data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +1 -1
  33. data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +1 -1
  34. data/lib/HDLRuby/hdr_samples/with_channel.rb +2 -0
  35. data/lib/HDLRuby/hdr_samples/with_channel_other.rb +2 -0
  36. data/lib/HDLRuby/hdr_samples/with_class.rb +3 -1
  37. data/lib/HDLRuby/hdr_samples/with_clocks.rb +42 -0
  38. data/lib/HDLRuby/hdr_samples/with_connector.rb +2 -0
  39. data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -0
  40. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +6 -0
  41. data/lib/HDLRuby/hdr_samples/with_fixpoint_adv.rb +73 -0
  42. data/lib/HDLRuby/hdr_samples/with_leftright.rb +1 -1
  43. data/lib/HDLRuby/hdr_samples/with_of.rb +1 -1
  44. data/lib/HDLRuby/hdr_samples/with_program_c.rb +28 -0
  45. data/lib/HDLRuby/hdr_samples/with_program_ruby.rb +28 -0
  46. data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb +234 -0
  47. data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb +23 -0
  48. data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb +58 -0
  49. data/lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb +56 -0
  50. data/lib/HDLRuby/hdr_samples/with_sequencer.rb +17 -0
  51. data/lib/HDLRuby/hdr_samples/with_sequencer_channel.rb +58 -0
  52. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +10 -0
  53. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +18 -4
  54. data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +2 -4
  55. data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +2 -1
  56. data/lib/HDLRuby/hdrcc.rb +72 -21
  57. data/lib/HDLRuby/hruby_error.rb +13 -0
  58. data/lib/HDLRuby/hruby_high.rb +125 -26
  59. data/lib/HDLRuby/hruby_low.rb +171 -3
  60. data/lib/HDLRuby/hruby_low2programs.rb +47 -0
  61. data/lib/HDLRuby/hruby_low_resolve.rb +3 -2
  62. data/lib/HDLRuby/hruby_low_without_namespace.rb +133 -5
  63. data/lib/HDLRuby/hruby_low_without_subsignals.rb +1 -1
  64. data/lib/HDLRuby/hruby_rcsim.rb +113 -6
  65. data/lib/HDLRuby/hruby_serializer.rb +2 -1
  66. data/lib/HDLRuby/hruby_verilog.rb +94 -20
  67. data/lib/HDLRuby/hruby_verilog_name.rb +3 -17
  68. data/lib/HDLRuby/std/clocks.rb +118 -50
  69. data/lib/HDLRuby/std/fixpoint.rb +2 -2
  70. data/lib/HDLRuby/std/function_generator.rb +1 -1
  71. data/lib/HDLRuby/std/linear.rb +7 -7
  72. data/lib/HDLRuby/std/sequencer.rb +263 -13
  73. data/lib/HDLRuby/std/sequencer_channel.rb +90 -0
  74. data/lib/HDLRuby/std/sequencer_func.rb +28 -15
  75. data/lib/HDLRuby/std/std.rb +6 -0
  76. data/lib/HDLRuby/ui/hruby_board.rb +1079 -0
  77. data/lib/HDLRuby/version.rb +1 -1
  78. data/lib/c/Rakefile +8 -0
  79. data/lib/c/cHDL.h +12 -0
  80. data/lib/c/extconf.rb +7 -0
  81. data/lib/rubyHDL.rb +33 -0
  82. data/tuto/gui_accum.png +0 -0
  83. data/tuto/gui_board.png +0 -0
  84. data/tuto/tutorial_sw.html +2263 -1890
  85. data/tuto/tutorial_sw.md +957 -62
  86. metadata +43 -5
  87. data/README.pdf +0 -0
  88. data/tuto/tutorial_sw.pdf +0 -0
@@ -0,0 +1,56 @@
1
+
2
+ # A benchmark for testing the use of Ruby software code.
3
+ system :with_ruby_thread do
4
+ inner :clk, :rst, :req, :ack
5
+ [8].inner :count
6
+
7
+ program(:ruby,:boot) do
8
+ actport rst.negedge
9
+ inport din: count
10
+ outport ack: ack
11
+ code "ruby_program/sw_log.rb"
12
+ end
13
+
14
+ program(:ruby,:log) do
15
+ actport req.posedge
16
+ code "ruby_program/sw_log.rb"
17
+ end
18
+
19
+ par(ack.posedge) { count <= count + 1 }
20
+
21
+
22
+ timed do
23
+ clk <= 0
24
+ rst <= 0
25
+ count <= 0
26
+ req <= 0
27
+ !10.ns
28
+ clk <= 1
29
+ !10.ns
30
+ clk <= 0
31
+ rst <= 1
32
+ !10.ns
33
+ clk <= 1
34
+ !10.ns
35
+ clk <= 0
36
+ rst <= 0
37
+ !10.ns
38
+ clk <= 1
39
+ !10.ns
40
+ clk <= 0
41
+ !10.ns
42
+ repeat(100) do
43
+ clk <= 1
44
+ req <= 1
45
+ !10.ns
46
+ clk <= 0
47
+ !10.ns
48
+ clk <= 1
49
+ req <= 0
50
+ !10.ns
51
+ clk <= 0
52
+ !10.ns
53
+ end
54
+
55
+ end
56
+ end
@@ -16,6 +16,7 @@ include HDLRuby::High::Std
16
16
  # - One sequencer puts the sum of two arrays in a third one.
17
17
  # - One sequencer iterates over two arrays.
18
18
  # - One sequencer iterates downward.
19
+ # - One sequencer checks sub iterators (HDLRuby special).
19
20
  system :my_seqencer do
20
21
 
21
22
  inner :clk,:rst
@@ -161,6 +162,22 @@ system :my_seqencer do
161
162
  # hprint(")2 res6=",res6,"\n")
162
163
  end
163
164
 
165
+ [8].inner :res7,:res8
166
+
167
+ sequencer(clk.posedge,rst) do
168
+ res7 <= 0
169
+ res8 <= 0
170
+ ar0.seach_range(0..3) do |elem|
171
+ res7 <= elem
172
+ end
173
+ ar0.seach_range(4..9) do |elem|
174
+ res7 <= elem
175
+ end
176
+ (_h00.._h07).seach_range(1..4) do |elem|
177
+ res8 <= elem
178
+ end
179
+ end
180
+
164
181
 
165
182
  timed do
166
183
  clk <= 0
@@ -0,0 +1,58 @@
1
+ require 'std/sequencer.rb'
2
+
3
+ include HDLRuby::High::Std
4
+
5
+ # Checking the usage of sequencers' channels.
6
+ system :my_seqencer do
7
+
8
+ inner :clk,:rst,filled: 0
9
+ bit[16][-16].inner :mem
10
+ [16].inner :res0, :res1, :res2, :res3
11
+
12
+ ch_read = schannel(bit[16],16) do |i|
13
+ mem[i]
14
+ end
15
+
16
+ ch_write = schannel(bit[16],16) do |i,val|
17
+ mem[i] <= val
18
+ end
19
+
20
+ sequencer(clk.posedge,rst) do
21
+ 16.stimes { |i| ch_write.snext!(i) }
22
+ filled <= 1
23
+ 16.stimes do |i|
24
+ res0 <= ch_read.snext
25
+ res1 <= ch_read[15-i]
26
+ end
27
+ end
28
+
29
+ sequencer(clk.posedge,rst) do
30
+ swhile(~filled);
31
+ 16.stimes do |i|
32
+ res2 <= ch_read.snext
33
+ res3 <= ch_read[15-i]
34
+ end
35
+ end
36
+
37
+
38
+ timed do
39
+ clk <= 0
40
+ rst <= 0
41
+ !10.ns
42
+ clk <= 1
43
+ !10.ns
44
+ clk <= 0
45
+ rst <= 1
46
+ !10.ns
47
+ clk <= 1
48
+ !10.ns
49
+ clk <= 0
50
+ rst <= 0
51
+ !10.ns
52
+ clk <= 1
53
+ repeat(100) do
54
+ !10.ns
55
+ clk <= ~clk
56
+ end
57
+ end
58
+ end
@@ -34,6 +34,7 @@ include HDLRuby::High::Std
34
34
  # - The twenty nineth sequencer checks stake and stake_while
35
35
  # - The thirtieth sequencer checks suniq
36
36
  # - The thirty first sequencer checks szip
37
+ # - The thirty second sequnecer checks seach_nexts (HDLRuby special)
37
38
  #
38
39
  # __WARNING__: All the operations on enumerators generate their own result
39
40
  # signal. Therefore, in a real circuit, there is no need to
@@ -414,6 +415,15 @@ system :my_seqencer do
414
415
  # hprint("}1 res52=",res52," res53=",res53,"\n")
415
416
  end
416
417
 
418
+ [8].inner :res54,:res55
419
+
420
+ sequencer(clk.posedge,rst) do
421
+ res54 <= 0
422
+ res55 <= 0
423
+ vals.seach_nexts(6) { |i| res54 <= i }
424
+ res55 <= vals.seach_nexts(4).ssum
425
+ end
426
+
417
427
 
418
428
 
419
429
  timed do
@@ -52,16 +52,30 @@ system :my_seqencer do
52
52
 
53
53
  data <= mem[addr]
54
54
 
55
- mem_enum = senumerator(bit[8],8) do |i|
56
- addr <= i
57
- step
58
- data
55
+ mem_enum = senumerator(bit[8],8) do |i,val|
56
+ if val then
57
+ # Write
58
+ mem[i] <= val
59
+ step
60
+ val
61
+ else
62
+ # Read
63
+ addr <= i
64
+ step
65
+ data
66
+ end
59
67
  end
60
68
 
61
69
  sequencer(clk.posedge,rst) do
62
70
  # hprint("~0\n")
63
71
  res6 <= 0
64
72
  res6 <= mem_enum.ssum
73
+ mem_enum.srewind
74
+ mem_enum.snext!(_hAA)
75
+ mem_enum.snext!(_hBB)
76
+ mem_enum.srewind
77
+ res6 <= mem_enum.snext
78
+ res6 <= mem_enum.snext
65
79
  # hprint("~1 res6=",res6,"\n")
66
80
  end
67
81
 
@@ -1,7 +1,3 @@
1
- require 'std/sequencer_func.rb'
2
-
3
- include HDLRuby::High::Std
4
-
5
1
 
6
2
  # A factorial with default stack depth.
7
3
  sdef(:fact) do |n|
@@ -31,11 +27,13 @@ system :my_seqencer do
31
27
  5.stimes do |i|
32
28
  val <= i
33
29
  res <= fact(val)
30
+ hprint("res=",res,"\n")
34
31
  end
35
32
  hprint("Going to overflow...\n")
36
33
  4.stimes do |i|
37
34
  val <= i
38
35
  res <= fact_over(val)
36
+ hprint("res=",res,"\n")
39
37
  end
40
38
  hprint("stack_overflow_error=",stack_overflow_error,"\n")
41
39
  end
@@ -13,7 +13,8 @@ system :my_seqencer do
13
13
  arbiter(:arbiter0).(x1)
14
14
 
15
15
  par(clk.posedge) do
16
- x0.select <= x0.select + 1
16
+ hif(rst) { x0.select(0) }
17
+ helse { x0.select(x0.select + 1) }
17
18
  end
18
19
 
19
20
  sequencer(clk.posedge,rst) do
data/lib/HDLRuby/hdrcc.rb CHANGED
@@ -37,19 +37,19 @@ if ARGV.include?("-I") || ARGV.include?("--interactive") then
37
37
  end
38
38
 
39
39
 
40
- begin
41
- # We can check the memory.
42
- require 'get_process_mem'
43
- $memory_check = GetProcessMem.new
44
- def show_mem
45
- " | "+$memory_check.bytes.to_s+"B"
46
- end
47
- rescue LoadError
48
- # We cannot check the memory.
40
+ # begin
41
+ # # We can check the memory.
42
+ # require 'get_process_mem'
43
+ # $memory_check = GetProcessMem.new
44
+ # def show_mem
45
+ # " | "+$memory_check.bytes.to_s+"B"
46
+ # end
47
+ # rescue LoadError
48
+ # # We cannot check the memory.
49
49
  def show_mem
50
50
  ""
51
51
  end
52
- end
52
+ # end
53
53
 
54
54
 
55
55
  require 'fileutils'
@@ -84,6 +84,10 @@ require 'HDLRuby/backend/hruby_c_allocator'
84
84
 
85
85
  require 'HDLRuby/version.rb'
86
86
 
87
+ # Global flags
88
+ $sim = false # Tells if hdrcc is in simulation mode
89
+ $gen = false # Tells if hdrcc is in hardware generation mode
90
+
87
91
 
88
92
  ##
89
93
  # HDLRuby compiler interface program
@@ -363,29 +367,33 @@ $optparse = OptionParser.new do |opts|
363
367
  opts.on("-r", "--hdr","Output in HDLRuby format") do |v|
364
368
  $options[:hdr] = v
365
369
  end
366
- opts.on("-C", "--clang","Output in C format (simulator)") do |v|
367
- $options[:clang] = v
368
- $options[:multiple] = v
369
- end
370
- opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
371
- $options[:allocate] = v
372
- end
370
+ # opts.on("-C", "--clang","Output in C format (simulator, deprecated)") do |v|
371
+ # $options[:clang] = v
372
+ # $options[:multiple] = v
373
+ # end
374
+ # opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
375
+ # $options[:allocate] = v
376
+ # end
373
377
  opts.on("-S","--sim","Default simulator (hybrid C-Ruby)") do |v|
374
378
  $options[:rcsim] = v
375
379
  $options[:multiple] = v
380
+ $sim = true
376
381
  end
377
- opts.on("--csim","Standalone C-based simulator") do |v|
382
+ opts.on("--csim","Standalone C-based simulator (deprecated)") do |v|
378
383
  $options[:clang] = v
379
384
  $options[:multiple] = v
380
385
  $options[:csim] = v
386
+ $sim = true
381
387
  end
382
- opts.on("--rsim","Ruby-based simulator") do |v|
388
+ opts.on("--rsim","Ruby-based simulator (deprecated)") do |v|
383
389
  $options[:rsim] = v
384
390
  $options[:multiple] = v
391
+ $sim = true
385
392
  end
386
393
  opts.on("--rcsim","Hybrid C-Ruby-based simulator") do |v|
387
394
  $options[:rcsim] = v
388
395
  $options[:multiple] = v
396
+ $sim = true
389
397
  end
390
398
  opts.on("--mute", "The simulator will not generate any output") do |v|
391
399
  $options[:mute] = v
@@ -393,15 +401,44 @@ $optparse = OptionParser.new do |opts|
393
401
  opts.on("--vcd", "The simulator will generate a vcd file") do |v|
394
402
  $options[:vcd] = v
395
403
  end
404
+ opts.on("--ch dir", "Generates the files for compiling a software extension") do |dir|
405
+ # Check the target directory.
406
+ if !dir or dir.empty? then
407
+ raise "Need a program name for generating the compiling files."
408
+ end
409
+ # Create the source path.
410
+ src_path = File.dirname(__FILE__) + "/../c/"
411
+ # Create the target directory.
412
+ Dir.mkdir(dir) unless File.exist?(dir)
413
+ # Copy the header files.
414
+ ## FileUtils.copy(src_path + "cHDL.h",dir)
415
+ # And update it with any empty initialization function
416
+ # (not used but required for compiling for windows).
417
+ lines = nil
418
+ File.open(src_path + "cHDL.h","r") {|f| lines = f.readlines }
419
+ lines = ["void Init_#{dir}() {}\n\n"] + lines
420
+ File.open(dir + "/" + "cHDL.h", "w") {|f| lines.each {|l| f.write(l) } }
421
+ # Copy and modify the files for rake.
422
+ ["extconf.rb", "Rakefile"].each do |fname|
423
+ lines = nil
424
+ File.open(src_path + fname,"r") {|f| lines = f.readlines }
425
+ # puts "Checking dir: #{File.dirname(__FILE__)+"/../hruby_sim/"}"
426
+ lines = ["C_PROGRAM = '#{dir}'\nRCSIM_DIR = '#{File.dirname(__FILE__)+"/../hruby_sim/"}'\n"] + lines
427
+ File.open(dir + "/" + fname, "w") {|f| lines.each {|l| f.write(l) } }
428
+ end
429
+ exit
430
+ end
396
431
  opts.on("-v", "--verilog","Output in Verlog HDL format") do |v|
397
432
  $options[:verilog] = v
398
433
  $options[:multiple] = v
434
+ $gen = true
399
435
  end
400
436
  opts.on("-V", "--vhdl","Output in VHDL format") do |v|
401
437
  HDLRuby::Low::Low2VHDL.vhdl08 = false
402
438
  $options[:vhdl] = v
403
439
  $options[:multiple] = v
404
440
  $options[:vhdl08] = false
441
+ $gen = true
405
442
  end
406
443
  opts.on("-A", "--alliance","Output in Alliance-compatible VHDL format") do |v|
407
444
  HDLRuby::Low::Low2VHDL.vhdl08 = false
@@ -410,12 +447,14 @@ $optparse = OptionParser.new do |opts|
410
447
  $options[:alliance] = v
411
448
  $options[:multiple] = v
412
449
  $options[:vhdl08] = false
450
+ $gen = true
413
451
  end
414
452
  opts.on("-U", "--vhdl08","Output in VHDL'08 format") do |v|
415
453
  HDLRuby::Low::Low2VHDL.vhdl08 = true
416
454
  $options[:vhdl] = v
417
455
  $options[:multiple] = v
418
456
  $options[:vhdl08] = true
457
+ $gen = true
419
458
  end
420
459
  opts.on("-s", "--syntax","Output the Ruby syntax tree") do |s|
421
460
  $options[:syntax] = s
@@ -454,14 +493,26 @@ $optparse = OptionParser.new do |opts|
454
493
  $options[:dump] = v
455
494
  $options[:multiple] = v
456
495
  end
457
- opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one, the exit") do
496
+ opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one, then exit") do
458
497
  FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples","./hdr_samples")
498
+ FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/c_program","./hdr_samples/c_program")
499
+ FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/ruby_program","./hdr_samples/ruby_program")
500
+ exit
501
+ end
502
+ opts.on("--get-tuto", "Copy the tutorial directory (tuto) to current one, then exit") do
503
+ FileUtils.copy_entry(File.dirname(__FILE__) + "../../tuto","./tuto")
459
504
  exit
460
505
  end
461
506
  opts.on("--version", "Show the version of HDLRuby, then exit") do |v|
462
507
  puts VERSION
463
508
  exit
464
509
  end
510
+ opts.on("--path","Shows the path where HDLRuby is install.") do |v|
511
+ require 'pathname'
512
+ path = Pathname.new(__FILE__ + "../../../../").cleanpath
513
+ puts path.to_s
514
+ exit
515
+ end
465
516
  # opts.on_tail("-h", "--help", "Show this message") do
466
517
  opts.on("-h", "--help", "Show this message") do
467
518
  puts opts
@@ -571,7 +622,7 @@ if $options[:syntax] then
571
622
  $output << $loader.show_all
572
623
  exit
573
624
  end
574
- HDLRuby.show "#{Time.now}#{show_mem}"
625
+ # HDLRuby.show "#{Time.now}#{show_mem}"
575
626
  HDLRuby.show "##### Starting parser #####"
576
627
 
577
628
  if $options[:debug] then
@@ -5,6 +5,10 @@ module HDLRuby
5
5
  class AnyError < ::StandardError
6
6
  end
7
7
 
8
+ ## The HDLRuby UI error class.
9
+ class UIError < ::StandardError
10
+ end
11
+
8
12
  module High
9
13
  ## The HDLRuby::High error class.
10
14
  class AnyError < HDLRuby::AnyError
@@ -13,12 +17,21 @@ module HDLRuby
13
17
  ## The HDLRuby error class replacing the standard Ruby NoMethodError
14
18
  class NotDefinedError < AnyError
15
19
  end
20
+
21
+ ## The HDLRuby::High UI error class.
22
+ class UIError < HDLRuby::UIError
23
+ end
16
24
  end
17
25
 
26
+
18
27
  module Low
19
28
  ## The HDLRuby::Low error class.
20
29
  class AnyError < HDLRuby::AnyError
21
30
  end
31
+
32
+ ## The HDLRuby::Low UI error class.
33
+ class UIError < HDLRuby::UIError
34
+ end
22
35
  end
23
36
 
24
37
  ## Execution context for processing error messages in +code+.