HDLRuby 3.1.0 → 3.3.0

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Files changed (88) hide show
  1. checksums.yaml +4 -4
  2. data/HDLRuby.gemspec +1 -0
  3. data/README.html +2330 -2670
  4. data/README.md +400 -100
  5. data/ext/hruby_sim/hruby_rcsim_build.c +402 -3
  6. data/ext/hruby_sim/hruby_sim.h +2 -1
  7. data/ext/hruby_sim/hruby_sim_calc.c +34 -7
  8. data/ext/hruby_sim/hruby_sim_core.c +15 -5
  9. data/ext/hruby_sim/hruby_sim_tree_calc.c +112 -23
  10. data/lib/HDLRuby/hdr_samples/c_program/echo.c +33 -0
  11. data/lib/HDLRuby/hdr_samples/comparison_bench.rb +2 -2
  12. data/lib/HDLRuby/hdr_samples/counter_bench.rb +1 -1
  13. data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +8 -7
  14. data/lib/HDLRuby/hdr_samples/dff_properties.rb +2 -0
  15. data/lib/HDLRuby/hdr_samples/enum_as_param.rb +52 -0
  16. data/lib/HDLRuby/hdr_samples/linear_test.rb +2 -0
  17. data/lib/HDLRuby/hdr_samples/logic_bench.rb +6 -0
  18. data/lib/HDLRuby/hdr_samples/mei8.rb +6 -6
  19. data/lib/HDLRuby/hdr_samples/mei8_bench.rb +6 -6
  20. data/lib/HDLRuby/hdr_samples/memory_test.rb +2 -0
  21. data/lib/HDLRuby/hdr_samples/named_sub.rb +9 -5
  22. data/lib/HDLRuby/hdr_samples/ram.rb +7 -6
  23. data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +2 -0
  24. data/lib/HDLRuby/hdr_samples/ruby_program/echo.rb +9 -0
  25. data/lib/HDLRuby/hdr_samples/ruby_program/stdrw.rb +6 -0
  26. data/lib/HDLRuby/hdr_samples/ruby_program/sw_cpu_terminal.rb +614 -0
  27. data/lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb +32 -0
  28. data/lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb +33 -0
  29. data/lib/HDLRuby/hdr_samples/struct.rb +15 -3
  30. data/lib/HDLRuby/hdr_samples/with_board.rb +63 -0
  31. data/lib/HDLRuby/hdr_samples/with_bram.rb +1 -1
  32. data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +1 -1
  33. data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +1 -1
  34. data/lib/HDLRuby/hdr_samples/with_channel.rb +2 -0
  35. data/lib/HDLRuby/hdr_samples/with_channel_other.rb +2 -0
  36. data/lib/HDLRuby/hdr_samples/with_class.rb +3 -1
  37. data/lib/HDLRuby/hdr_samples/with_clocks.rb +42 -0
  38. data/lib/HDLRuby/hdr_samples/with_connector.rb +2 -0
  39. data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -0
  40. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +6 -0
  41. data/lib/HDLRuby/hdr_samples/with_fixpoint_adv.rb +73 -0
  42. data/lib/HDLRuby/hdr_samples/with_leftright.rb +1 -1
  43. data/lib/HDLRuby/hdr_samples/with_of.rb +1 -1
  44. data/lib/HDLRuby/hdr_samples/with_program_c.rb +28 -0
  45. data/lib/HDLRuby/hdr_samples/with_program_ruby.rb +28 -0
  46. data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb +234 -0
  47. data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb +23 -0
  48. data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb +58 -0
  49. data/lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb +56 -0
  50. data/lib/HDLRuby/hdr_samples/with_sequencer.rb +17 -0
  51. data/lib/HDLRuby/hdr_samples/with_sequencer_channel.rb +58 -0
  52. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +10 -0
  53. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +18 -4
  54. data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +2 -4
  55. data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +2 -1
  56. data/lib/HDLRuby/hdrcc.rb +72 -21
  57. data/lib/HDLRuby/hruby_error.rb +13 -0
  58. data/lib/HDLRuby/hruby_high.rb +125 -26
  59. data/lib/HDLRuby/hruby_low.rb +171 -3
  60. data/lib/HDLRuby/hruby_low2programs.rb +47 -0
  61. data/lib/HDLRuby/hruby_low_resolve.rb +3 -2
  62. data/lib/HDLRuby/hruby_low_without_namespace.rb +133 -5
  63. data/lib/HDLRuby/hruby_low_without_subsignals.rb +1 -1
  64. data/lib/HDLRuby/hruby_rcsim.rb +113 -6
  65. data/lib/HDLRuby/hruby_serializer.rb +2 -1
  66. data/lib/HDLRuby/hruby_verilog.rb +94 -20
  67. data/lib/HDLRuby/hruby_verilog_name.rb +3 -17
  68. data/lib/HDLRuby/std/clocks.rb +118 -50
  69. data/lib/HDLRuby/std/fixpoint.rb +2 -2
  70. data/lib/HDLRuby/std/function_generator.rb +1 -1
  71. data/lib/HDLRuby/std/linear.rb +7 -7
  72. data/lib/HDLRuby/std/sequencer.rb +263 -13
  73. data/lib/HDLRuby/std/sequencer_channel.rb +90 -0
  74. data/lib/HDLRuby/std/sequencer_func.rb +28 -15
  75. data/lib/HDLRuby/std/std.rb +6 -0
  76. data/lib/HDLRuby/ui/hruby_board.rb +1079 -0
  77. data/lib/HDLRuby/version.rb +1 -1
  78. data/lib/c/Rakefile +8 -0
  79. data/lib/c/cHDL.h +12 -0
  80. data/lib/c/extconf.rb +7 -0
  81. data/lib/rubyHDL.rb +33 -0
  82. data/tuto/gui_accum.png +0 -0
  83. data/tuto/gui_board.png +0 -0
  84. data/tuto/tutorial_sw.html +2263 -1890
  85. data/tuto/tutorial_sw.md +957 -62
  86. metadata +43 -5
  87. data/README.pdf +0 -0
  88. data/tuto/tutorial_sw.pdf +0 -0
@@ -1,3 +1,3 @@
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  module HDLRuby
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- VERSION = "3.1.0"
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+ VERSION = "3.3.0"
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  end
data/lib/c/Rakefile ADDED
@@ -0,0 +1,8 @@
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+ require 'rake/extensiontask'
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+
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+ Rake::ExtensionTask.new do |ext|
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+ ext.name = C_PROGRAM
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+ ext.ext_dir = './'
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+ ext.lib_dir = './'
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+ end
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+
data/lib/c/cHDL.h ADDED
@@ -0,0 +1,12 @@
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+ /**
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+ * Interface for C program with HDLRuby hardware.
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+ **/
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+
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+ /** The wrapper for getting an interface port for C software. */
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+ extern void* c_get_port(const char* name);
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+
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+ /** The wrapper for getting a value from a port. */
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+ extern unsigned long long c_read_port(void* port);
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+
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+ /** The wrapper for setting a value to a port. */
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+ extern unsigned long long c_write_port(void* port, unsigned long long val);
data/lib/c/extconf.rb ADDED
@@ -0,0 +1,7 @@
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+ require 'mkmf'
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+
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+ append_ldflags("-L #{RCSIM_DIR} -l:hruby_sim.so") if Gem.win_platform?
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+
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+ # $LDFLAGS << " -L #{RCSIM_DIR} -l:hruby_sim.so" if Gem.win_platform?
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+
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+ create_makefile(C_PROGRAM)
data/lib/rubyHDL.rb ADDED
@@ -0,0 +1,33 @@
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+ require 'hruby_sim/hruby_sim'
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+
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+ ##
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+ # Module for accessing HDLRuby hardware from a ruby program excuted on
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+ # an embedded processor: HDLRuby simulator version.
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+ ########################################################################
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+ module RubyHDL
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+
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+ # Creates a new port 'name' assigned to signal 'sig' for reading.
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+ def self.inport(name,sig)
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+ # Create the accessing methods.
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+ # For reading.
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+ define_singleton_method(name.to_sym) do
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+ RCSim.rcsim_get_signal_fixnum(sig)
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+ end
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+ end
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+
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+ # Creates a new wport 'name' assigned to signal 'sig' for writing.
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+ def self.outport(name,sig)
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+ # For writing.
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+ define_singleton_method(:"#{name}=") do |val|
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+ RCSim.rcsim_transmit_fixnum_to_signal_seq(sig,val)
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+ end
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+ end
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+
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+ # Creates a new program 'name' assign to simulator code 'code'.
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+ def self.program(name,code)
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+ # Create the accessing method.
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+ define_singleton_method(name.to_sym) do
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+ code
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+ end
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+ end
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+ end
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