HDLRuby 3.1.0 → 3.3.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/HDLRuby.gemspec +1 -0
- data/README.html +2330 -2670
- data/README.md +400 -100
- data/ext/hruby_sim/hruby_rcsim_build.c +402 -3
- data/ext/hruby_sim/hruby_sim.h +2 -1
- data/ext/hruby_sim/hruby_sim_calc.c +34 -7
- data/ext/hruby_sim/hruby_sim_core.c +15 -5
- data/ext/hruby_sim/hruby_sim_tree_calc.c +112 -23
- data/lib/HDLRuby/hdr_samples/c_program/echo.c +33 -0
- data/lib/HDLRuby/hdr_samples/comparison_bench.rb +2 -2
- data/lib/HDLRuby/hdr_samples/counter_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +8 -7
- data/lib/HDLRuby/hdr_samples/dff_properties.rb +2 -0
- data/lib/HDLRuby/hdr_samples/enum_as_param.rb +52 -0
- data/lib/HDLRuby/hdr_samples/linear_test.rb +2 -0
- data/lib/HDLRuby/hdr_samples/logic_bench.rb +6 -0
- data/lib/HDLRuby/hdr_samples/mei8.rb +6 -6
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +6 -6
- data/lib/HDLRuby/hdr_samples/memory_test.rb +2 -0
- data/lib/HDLRuby/hdr_samples/named_sub.rb +9 -5
- data/lib/HDLRuby/hdr_samples/ram.rb +7 -6
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +2 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/echo.rb +9 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/stdrw.rb +6 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_cpu_terminal.rb +614 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb +32 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb +33 -0
- data/lib/HDLRuby/hdr_samples/struct.rb +15 -3
- data/lib/HDLRuby/hdr_samples/with_board.rb +63 -0
- data/lib/HDLRuby/hdr_samples/with_bram.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_channel.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_channel_other.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_class.rb +3 -1
- data/lib/HDLRuby/hdr_samples/with_clocks.rb +42 -0
- data/lib/HDLRuby/hdr_samples/with_connector.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +6 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint_adv.rb +73 -0
- data/lib/HDLRuby/hdr_samples/with_leftright.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_of.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_program_c.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb +234 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb +23 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb +58 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb +56 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +17 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_channel.rb +58 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +10 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +18 -4
- data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +2 -4
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +2 -1
- data/lib/HDLRuby/hdrcc.rb +72 -21
- data/lib/HDLRuby/hruby_error.rb +13 -0
- data/lib/HDLRuby/hruby_high.rb +125 -26
- data/lib/HDLRuby/hruby_low.rb +171 -3
- data/lib/HDLRuby/hruby_low2programs.rb +47 -0
- data/lib/HDLRuby/hruby_low_resolve.rb +3 -2
- data/lib/HDLRuby/hruby_low_without_namespace.rb +133 -5
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +1 -1
- data/lib/HDLRuby/hruby_rcsim.rb +113 -6
- data/lib/HDLRuby/hruby_serializer.rb +2 -1
- data/lib/HDLRuby/hruby_verilog.rb +94 -20
- data/lib/HDLRuby/hruby_verilog_name.rb +3 -17
- data/lib/HDLRuby/std/clocks.rb +118 -50
- data/lib/HDLRuby/std/fixpoint.rb +2 -2
- data/lib/HDLRuby/std/function_generator.rb +1 -1
- data/lib/HDLRuby/std/linear.rb +7 -7
- data/lib/HDLRuby/std/sequencer.rb +263 -13
- data/lib/HDLRuby/std/sequencer_channel.rb +90 -0
- data/lib/HDLRuby/std/sequencer_func.rb +28 -15
- data/lib/HDLRuby/std/std.rb +6 -0
- data/lib/HDLRuby/ui/hruby_board.rb +1079 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/lib/c/Rakefile +8 -0
- data/lib/c/cHDL.h +12 -0
- data/lib/c/extconf.rb +7 -0
- data/lib/rubyHDL.rb +33 -0
- data/tuto/gui_accum.png +0 -0
- data/tuto/gui_board.png +0 -0
- data/tuto/tutorial_sw.html +2263 -1890
- data/tuto/tutorial_sw.md +957 -62
- metadata +43 -5
- data/README.pdf +0 -0
- data/tuto/tutorial_sw.pdf +0 -0
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@@ -121,6 +121,9 @@ Value calc_expression(Expression expr, Value res) {
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free_value();
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/* Performs the access. */
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res = read_range(value,index,index,rexpr->type,res);
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/* Set the type to the one of the reference since it is
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* an index access and not a range one. */
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res->type = rexpr->type;
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free_value();
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break;
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}
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@@ -174,6 +177,82 @@ Value calc_expression(Expression expr, Value res) {
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}
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/** Calculates a range access from a reference.
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* Recurse over the multiple references.
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* @param ref the reference to work on.
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* @param first the first index of the access.
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* @param last the last index of the access.
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* @param sig the target signal. */
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void calc_ref_rangeS(Reference ref, long long* first, long long *last,
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SignalI* sig) {
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// printf("calc_ref_rangeS with kind=%d\n",ref->kind);
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if (ref->kind == CAST) {
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/* Create a new reference for the computation that changes the type. */
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Cast refc = (Cast)ref;
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/* Compute the range for the child. */
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long long cfirst, clast;
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calc_ref_rangeS(refc->child,&cfirst,&clast,sig);
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/* Update first and last using the cast. */
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/* Both first and last should be equal since the type of the cast sets
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* the width */
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// printf("cfirst=%d clast=%d\n",cfirst,clast);
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*first = *last = cfirst;
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}
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else if (ref->kind == REF_INDEX) {
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RefIndex refi = (RefIndex)ref;
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/* Compute the index of refi. */
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Value indexV = get_value();
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indexV = calc_expression(refi->index,indexV);
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long long index = value2integer(indexV);
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// printf("index=%d\n",index);
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free_value();
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/* Is the reference a signal? */
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if (refi->ref->kind == SIGNALI) {
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/* Yes, end here. */
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*first = index;
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*last = index;
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*sig = (SignalI)(refi->ref);
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} else {
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/* No, need to recurse. */
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long long pfirst, plast;
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calc_ref_rangeS(refi->ref,&pfirst,&plast,sig);
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// printf("pfirst=%d plast=%d\n",pfirst,plast);
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/* Calculate the final first and last. */
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*first = *last = pfirst + index;
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}
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} else if (ref->kind == REF_RANGE) {
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RefRangeE refr = (RefRangeE)ref;
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/* Compute the range of refr */
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Value firstV = get_value();
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firstV = calc_expression(refr->first,firstV);
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long long firstR = value2integer(firstV);
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free_value();
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Value lastV = get_value();
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lastV = calc_expression(refr->last,lastV);
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long long lastR = value2integer(lastV);
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free_value();
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// printf("firstR=%d lastR=%d\n",firstR,lastR);
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/* Is the reference a signal? */
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if (refr->ref->kind == SIGNALI) {
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/* Yes, end here. */
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*first = firstR;
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*last = lastR;
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*sig = (SignalI)(refr->ref);
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} else {
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/* No, need to recurse. */
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long long pfirst, plast;
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calc_ref_rangeS(refr->ref,&pfirst,&plast,sig);
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/* Calculate the final first and last. */
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*first = pfirst + firstR;
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*last = plast + lastR;
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}
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} else {
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perror("Invalid reference for converting to range access.");
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exit(1);
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}
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}
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/** Executes a statement.
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* @param stmnt the statement to execute.
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@@ -205,15 +284,22 @@ void execute_statement(Statement stmnt, int mode, Behavior behavior) {
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{
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/* Transmission to sub element. */
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RefIndex refi = (RefIndex)(trans->left);
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/* Compute the index. */
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Value indexV = get_value();
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indexV = calc_expression(refi->index,indexV);
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long long index = value2integer(indexV);
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free_value();
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/* Generate the reference inside the left value. */
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// /* Compute the index. */
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// Value indexV = get_value();
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// indexV = calc_expression(refi->index,indexV);
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// long long index = value2integer(indexV);
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// free_value();
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// /* Generate the reference inside the left value. */
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// RefRangeS ref =
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// make_ref_rangeS((SignalI)(refi->ref),refi->type,
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// index,index);
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/* Compute the range. */
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long long first,last;
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SignalI sig;
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calc_ref_rangeS((Reference)refi,&first,&last,&sig);
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/* Now can create the range. */
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RefRangeS ref =
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make_ref_rangeS(
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index,index);
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make_ref_rangeS(sig,refi->type,first,last);
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/* Perform the transmit. */
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if(mode)
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transmit_to_signal_range_seq(right,ref);
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/* Transmission to range of sub elements. */
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RefRangeE refr = (RefRangeE)(trans->left);
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/* Compute the range. */
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// Value firstV =
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//
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//
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// Value firstV = get_value();
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// firstV = calc_expression(refr->first,firstV);
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// long long first = value2integer(firstV);
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// free_value();
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// Value lastV = get_value();
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// lastV = calc_expression(refr->last,lastV);
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// long long last = value2integer(lastV);
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// free_value();
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// /* Generate the reference inside the left value. */
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// RefRangeS ref =
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// make_ref_rangeS((SignalI)(refr->ref),refr->type,
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// first,last);
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long long first,last;
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SignalI sig;
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calc_ref_rangeS((Reference)refr,&first,&last,&sig);
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/* Now can create the range. */
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RefRangeS ref =
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make_ref_rangeS(
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first,last);
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make_ref_rangeS(sig,refr->type,first,last);
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/* Perform the transmit. */
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if(mode)
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transmit_to_signal_range_seq(right,ref);
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}
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default:
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perror("Invalid kind for
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perror("Invalid kind for a statement.");
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}
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}
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@@ -0,0 +1,33 @@
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#include <stdio.h>
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#include "cHDL.h"
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#if defined(_WIN32) || defined(_WIN64)
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__declspec(dllexport)
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#endif
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void echo(void* code) {
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static void* inP = NULL;
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static void* outP = NULL;
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unsigned long long data;
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/* Is the input port obtained? */
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if (inP == NULL) {
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/* No, get it. */
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inP = c_get_port("inP");
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}
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/* Is the input port obtained? */
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if (outP == NULL) {
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/* No, get it. */
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outP = c_get_port("outP");
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}
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/* Get data from the input port. */
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data = c_read_port(inP);
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/* Display it. */
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printf("Echoing: %llu\n", data);
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/* Echoing the data. */
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c_write_port(outP,data);
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}
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@@ -1,34 +1,35 @@
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# A simple D-FF
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system :dff do
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input :clk, :d
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input :clk, :rst, :d
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output :q
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(q <= d).at(clk.posedge)
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(q <= d & ~rst).at(clk.posedge)
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end
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# A benchmark for the dff.
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system :dff_bench do
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inner :clk
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inner :clk, :rst
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inner :d0, :q0, :d1, :q1
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dff(:my_dff0).(clk,d0,q0)
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dff(:my_dff1).(d0,d1,q1)
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dff(:my_dff0).(clk,rst,d0,q0)
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dff(:my_dff1).(d0,rst,d1,q1)
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d0 <= ~q0
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d1 <= ~q1
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timed do
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d0 <= 0
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d1 <= 0
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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@@ -0,0 +1,52 @@
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1
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# Check if an enum can be passed as generic parameter.
|
|
2
|
+
|
|
3
|
+
|
|
4
|
+
system :machin do |vals|
|
|
5
|
+
input :clk,:rst
|
|
6
|
+
[8].output :res
|
|
7
|
+
sequencer(clk,rst) do
|
|
8
|
+
vals.seach { |val| res <= val }
|
|
9
|
+
end
|
|
10
|
+
end
|
|
11
|
+
|
|
12
|
+
system :truc do |sig|
|
|
13
|
+
[8].output :res
|
|
14
|
+
|
|
15
|
+
res <= sig
|
|
16
|
+
end
|
|
17
|
+
|
|
18
|
+
system :machin_bench do
|
|
19
|
+
inner :clk,:rst
|
|
20
|
+
|
|
21
|
+
bit[8][-4].inner vals: [ _h01,_h02,_h03,_h05 ]
|
|
22
|
+
[8].inner :res0
|
|
23
|
+
|
|
24
|
+
machin(vals).(:my_machin).(clk,rst,res0)
|
|
25
|
+
|
|
26
|
+
[8].inner :val, :res1
|
|
27
|
+
truc(val).(:my_truc).(res1)
|
|
28
|
+
|
|
29
|
+
timed do
|
|
30
|
+
val <= 10
|
|
31
|
+
clk <= 0
|
|
32
|
+
rst <= 0
|
|
33
|
+
!10.ns
|
|
34
|
+
clk <= 1
|
|
35
|
+
rst <= 0
|
|
36
|
+
!10.ns
|
|
37
|
+
clk <= 0
|
|
38
|
+
rst <= 1
|
|
39
|
+
!10.ns
|
|
40
|
+
clk <= 1
|
|
41
|
+
!10.ns
|
|
42
|
+
clk <= 0
|
|
43
|
+
rst <= 0
|
|
44
|
+
!10.ns
|
|
45
|
+
repeat(15) do
|
|
46
|
+
clk <= 1
|
|
47
|
+
!10.ns
|
|
48
|
+
clk <= 0
|
|
49
|
+
!10.ns
|
|
50
|
+
end
|
|
51
|
+
end
|
|
52
|
+
end
|
|
@@ -3,6 +3,8 @@
|
|
|
3
3
|
system :logic_bench do
|
|
4
4
|
[3].inner :x,:y
|
|
5
5
|
[3].inner :s_not, :s_and, :s_or, :s_xor, :s_nxor
|
|
6
|
+
|
|
7
|
+
signed[16].inner :a,:b,:shl,:shr
|
|
6
8
|
|
|
7
9
|
timed do
|
|
8
10
|
8.times do |i|
|
|
@@ -15,6 +17,10 @@ system :logic_bench do
|
|
|
15
17
|
s_xor <= x ^ y
|
|
16
18
|
s_nxor <= (x == y)
|
|
17
19
|
!10.ns
|
|
20
|
+
a <= i
|
|
21
|
+
b <= j
|
|
22
|
+
shl <= (a << b)
|
|
23
|
+
shr <= (a >> b)
|
|
18
24
|
end
|
|
19
25
|
end
|
|
20
26
|
end
|
|
@@ -54,7 +54,7 @@ system :mei8 do |prog_file = "./prog.obj"|
|
|
|
54
54
|
end
|
|
55
55
|
|
|
56
56
|
# The control part for choosing between 0, add, sub and neg.
|
|
57
|
-
par do
|
|
57
|
+
par(opr,x,y) do
|
|
58
58
|
# Default computations
|
|
59
59
|
cf <= 0; vf <= 0; zf <= (z == 0); sf <= z[7]
|
|
60
60
|
add.(0,0,0)
|
|
@@ -148,14 +148,14 @@ system :mei8 do |prog_file = "./prog.obj"|
|
|
|
148
148
|
end
|
|
149
149
|
end
|
|
150
150
|
|
|
151
|
+
# Handling of the 3-state data bus
|
|
152
|
+
dbus <= mux(io_rwb,io_out,_bzzzzzzzz)
|
|
153
|
+
io_in <= dbus
|
|
154
|
+
|
|
151
155
|
# The io unit.
|
|
152
156
|
fsm(clk.posedge,rst,:async) do
|
|
153
157
|
default { io_done <= 0; req <= 0; rwb <= 0; addr <= 0
|
|
154
|
-
io_r_done <= 0
|
|
155
|
-
# Default handling of the 3-state data bus
|
|
156
|
-
hif(io_rwb) { dbus <= _zzzzzzzz }
|
|
157
|
-
helse { dbus <= io_out }
|
|
158
|
-
io_in <= dbus }
|
|
158
|
+
io_r_done <= 0 }
|
|
159
159
|
reset(:sync) { data <= 0; }
|
|
160
160
|
state(:wait) { goto(io_req,:start,:wait) } # Waiting for an IO
|
|
161
161
|
state(:start) { req <= 1; rwb <= io_rwb; addr <= g # Start an IO
|
|
@@ -56,7 +56,7 @@ system :mei8 do |prog_file = "./prog.obj"|
|
|
|
56
56
|
end
|
|
57
57
|
|
|
58
58
|
# The control part for choosing between 0, add, sub and neg.
|
|
59
|
-
par do
|
|
59
|
+
par(opr,x,y) do
|
|
60
60
|
# Default computations
|
|
61
61
|
cf <= 0; vf <= 0; zf <= (z == 0); sf <= z[7]
|
|
62
62
|
add.(0,0,0)
|
|
@@ -150,14 +150,14 @@ system :mei8 do |prog_file = "./prog.obj"|
|
|
|
150
150
|
end
|
|
151
151
|
end
|
|
152
152
|
|
|
153
|
+
# Handling of the 3-state data bus
|
|
154
|
+
dbus <= mux(io_rwb,io_out,_bzzzzzzzz)
|
|
155
|
+
io_in <= dbus
|
|
156
|
+
|
|
153
157
|
# The io unit.
|
|
154
158
|
fsm(clk.posedge,rst,:async) do
|
|
155
159
|
default { io_done <= 0; req <= 0; rwb <= 0; addr <= 0
|
|
156
|
-
io_r_done <= 0
|
|
157
|
-
# Default handling of the 3-state data bus
|
|
158
|
-
hif(io_rwb) { dbus <= _zzzzzzzz }
|
|
159
|
-
helse { dbus <= io_out }
|
|
160
|
-
io_in <= dbus }
|
|
160
|
+
io_r_done <= 0 }
|
|
161
161
|
reset(:sync) { data <= 0; }
|
|
162
162
|
state(:wait) { goto(io_req,:start,:wait) } # Waiting for an IO
|
|
163
163
|
state(:start) { req <= 1; rwb <= io_rwb; addr <= g # Start an IO
|
|
@@ -4,9 +4,9 @@
|
|
|
4
4
|
|
|
5
5
|
|
|
6
6
|
# A simple circuit with named sub
|
|
7
|
-
system :named_sub do
|
|
8
|
-
input :
|
|
9
|
-
output :s
|
|
7
|
+
system :named_sub do |x|
|
|
8
|
+
input :y
|
|
9
|
+
output :s, :z
|
|
10
10
|
|
|
11
11
|
sub :somesub do
|
|
12
12
|
inner :sig
|
|
@@ -17,13 +17,17 @@ system :named_sub do
|
|
|
17
17
|
s <= ~somesub.sig
|
|
18
18
|
end
|
|
19
19
|
|
|
20
|
+
z <= s
|
|
21
|
+
|
|
20
22
|
end
|
|
21
23
|
|
|
22
24
|
# A benchmark for the circuit.
|
|
23
25
|
system :named_sub_bench do
|
|
24
|
-
inner :x, :y, :s
|
|
26
|
+
inner :x, :y, :s, :z
|
|
27
|
+
|
|
28
|
+
named_sub(x).(:my_named_sub).(y,s)
|
|
25
29
|
|
|
26
|
-
|
|
30
|
+
z <= my_named_sub.z
|
|
27
31
|
|
|
28
32
|
timed do
|
|
29
33
|
x <= 0
|
|
@@ -4,15 +4,16 @@ system :ram8_16 do
|
|
|
4
4
|
[7..0].input :addr
|
|
5
5
|
[7..0].inout :data
|
|
6
6
|
|
|
7
|
+
[7..0].inner :data_in
|
|
8
|
+
|
|
7
9
|
bit[7..0][2**8].inner :content
|
|
8
10
|
|
|
9
|
-
|
|
11
|
+
data <= mux(en & rwb, _bzzzzzzzz, content[addr])
|
|
12
|
+
data_in <= data
|
|
13
|
+
|
|
10
14
|
par(clk.posedge) do
|
|
11
|
-
hif(en) do
|
|
12
|
-
|
|
13
|
-
hif(rwb) { data <= content[addr] }
|
|
14
|
-
helse { content[addr] <= data }
|
|
15
|
+
hif(en & ~rwb) do
|
|
16
|
+
content[addr] <= data_in
|
|
15
17
|
end
|
|
16
|
-
helse { data <= _bZZZZZZZZ }
|
|
17
18
|
end
|
|
18
19
|
end
|