HDLRuby 3.1.0 → 3.3.0

data/lib/HDLRuby/hdr_samples/with_board.rb

@@ -0,0 +1,63 @@
+
+# A benchmark for testing the use of a board model implementing:
+# * a simple adder whose input are set using slide switches, and
+#   whose output bits are showns on LEDs.
+# * simple unsigned and signed counters whose values are shown using
+#   decimal or hexadecimal displays, and oscilloscopes.
+system :with_board do
+    inner :clk, :clk2
+    [8].inner clk_cnt: 0
+    inner rst: 0
+    [8].inner :sw_a, :sw_b
+    [9].inner :led_z
+    [16].inner counter: 0
+    [8].inner :counter8
+    signed[8].inner :scounter8
+
+    # Description of the board.
+    # It is updated at each rising edge of +clk2+.
+    board(:some_board) do
+        actport clk2.posedge
+        bt  reset:    rst
+        row
+        sw  sw_a:     sw_a
+        sw  sw_b:     sw_b
+        led led_z:    led_z
+        row
+        digit cnt_d:  counter
+        hexa  cnt_h:  counter
+        digit cnt_s:  scounter8
+        row
+        scope scope:  counter8
+        scope scope_s:scounter8
+    end
+
+    # The adder.
+    led_z <= sw_a.as(bit[9]) + sw_b
+
+    # The counters and the generation of +clk2+.
+    counter8 <= counter[7..0]
+    scounter8 <= counter[7..0]
+
+    seq(clk.posedge) do
+      hif(rst) { counter <= 0 }
+      helse { counter <= counter + 1 }
+      clk_cnt <= clk_cnt + 1
+      hif(clk_cnt & 3 == 0) { clk2 <= ~clk2 }
+    end
+
+
+
+    timed do
+        clk <= 0
+        clk2 <= 0
+        !10.ns
+        repeat(1000) do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+
+    end
+end

data/lib/HDLRuby/hdr_samples/with_bram.rb

@@ -10,7 +10,7 @@ system :bram_test do
     widthD = 8
 
 
-    input :clk,:rwb
+    inner :clk,:rwb
     [widthA].inner :addr
     [widthD].inner  :din,:dout
 

data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb

@@ -11,7 +11,7 @@ system :bram_stach_test do
     depth = 16
 
 
-    input :clk, :rst, :ce
+    inner :clk, :rst, :ce
     [2].inner :cmd
     { frame: bit[depth.width], offset: bit[size.width] }.inner :loc
     [size.width].inner :frame_size

data/lib/HDLRuby/hdr_samples/with_bram_stack.rb

@@ -10,7 +10,7 @@ system :bram_stach_test do
     widthD = 8
 
 
-    input :clk, :rst, :ce
+    inner :clk, :rst, :ce
     inner :cmd
     [widthD].inner  :din,:dout
     inner :empty, :full

data/lib/HDLRuby/hdr_samples/with_channel.rb

@@ -1,5 +1,7 @@
 require 'std/channel.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 # Implementation of a handshaker channel transmitting generic values

data/lib/HDLRuby/hdr_samples/with_channel_other.rb

@@ -1,6 +1,8 @@
 require 'std/channel.rb'
 require 'std/hruby_unit.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 # A clocked handshake channel for testing purpuse.

data/lib/HDLRuby/hdr_samples/with_class.rb

@@ -1,5 +1,7 @@
 # A class for a handshake transmission.
 
+raise "Deprecated code."
+
 class Handshaker
 
     ## Create a new handshaker for transmitting +type+ data.
@@ -179,7 +181,7 @@ end
 
 # A system testing the producer/consumer.
 system :hs_test do
-    input :clk,:rst
+    inner :clk,:rst
 
     # Declares the handshaker
     hs = Handshaker.new([8])

data/lib/HDLRuby/hdr_samples/with_clocks.rb

@@ -0,0 +1,42 @@
+# A system for testing the clock generator.
+system :with_clocks do
+    inner :clk, :rst
+    [8].inner :cnt1, :cnt2, :cnt3, :cnt4, :cnt5
+    [8].inner :cnta, :cntb, :cntc, :cntd
+
+    configure_clocks(rst)
+
+    (cnt1 <= cnt1 + 1).at(clk.posedge)
+    (cnt2 <= cnt2 + 1).at(clk.posedge*2)
+    (cnt3 <= cnt3 + 1).at(clk.posedge*3)
+    (cnt4 <= cnt4 + 1).at(clk.posedge*4)
+    (cnt5 <= cnt5 + 1).at(clk.posedge*5)
+
+    configure_clocks(nil)
+
+    (cnta <= cnta + 1).at(clk.posedge*2)
+    (cntb <= cntb + 1).at(clk.posedge*3)
+    (cntc <= cntc + 1).at(clk.posedge*4)
+    (cntd <= cntd + 1).at(clk.posedge*5)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        cnt1 <= 0; cnt2 <= 0; cnt3 <= 0; cnt4 <= 0; cnt5 <= 0
+        cnta <= 0; cntb <= 0; cntc <= 0; cntd <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        repeat(100) do
+            !10.ns
+            clk <= ~clk
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_connector.rb

@@ -1,6 +1,8 @@
 require 'std/channel.rb'
 require 'std/connector.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 # Sample for testing the connectors of channels.

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -3,6 +3,8 @@ require "std/fixpoint.rb"
 require 'std/channel.rb'
 require 'std/connector.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 system :channel_connector do

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -11,6 +11,12 @@ system :fix_test do
     bit[3..0,3..0].inner :x,:y,:z
     # Declare three 8-bit integer part 8-bit fractional part
     signed[3..0,3..0].inner :a,:b,:c,:d
+    # Declare the comparison results.
+    bit.inner :cmpU, :cmpS
+
+    cmpU <= (x >= y)
+    cmpS <= (a >= b)
+
 
     # Performs calculation between then
     timed do

data/lib/HDLRuby/hdr_samples/with_fixpoint_adv.rb

@@ -0,0 +1,73 @@
+# Sample for testing advanced expressions with fixpoint.
+
+system :with_fixpoint_adv do
+    inner :clk,:rst
+    signed[8,8].inner :x,:y,:z,:u,:v,:w,:a,:b,:c,:d
+    bit.inner :cmp
+
+    cmp <= (x >= y)
+    u   <= (x >= y)
+
+    sequencer(clk,rst) do
+        hif(5>4) { w <= _hFFFF }
+        helse    { w <= _h0000 }
+        swhile(w<_h0000) do
+            hif(5>6) { w <= _hFFFF }
+            helse    { w <= _h0000 }
+        end
+        5.stimes do
+            x <= _h0100
+            y <= _hFF34
+            a <= _h0100
+            b <= _h0100
+            c <= _h0100
+            step
+            x <= x*a
+            hif(x>=y) { z <= _hFFFF }
+            helse     { z <= _h0000 }
+            v <= mux(x>=y,_h0000,_hFFFF)
+            hif(10>0) { w <= _hFFFF }
+            helse     { w <= _h0000 }
+            d <= a*b*c
+            step
+            x <= _h0000
+            x <= x*a
+            y <= _hFE68
+            hif(x>=y) { z <= _hFFFF }
+            helse     { z <= _h0000 }
+            v <= mux(x>=y,_h0000,_hFFFF)
+            hif(1>20) { w <= _hFFFF }
+            helse     { w <= _h0000 }
+            a <= _h0200
+            d <= a*b*c
+            step
+            x <= _hFE00
+            x <= x*a
+            y <= _hFE02
+            hif(x>=y) { z <= _hFFFF }
+            helse     { z <= _h0000 }
+            v <= mux(x>=y,_h0000,_hFFFF)
+            b <= _h0200
+            d <= a*b*c
+        end
+    end
+
+    def cstep(n=1)
+        n.times do
+            clk <= ~clk
+            !10.ns
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        cstep(2)
+        rst <= 1
+        cstep(2)
+        rst <= 0
+        cstep(40)
+    end
+    
+end

data/lib/HDLRuby/hdr_samples/with_leftright.rb

@@ -3,7 +3,7 @@
 system :leftright_bench do
     [8].inner :l,:r0,:r1,:lr
 
-    par do
+    seq do
         lr <= r0*2
         l <= [lr[7],lr[6..0]].to_expr + r1
     end

data/lib/HDLRuby/hdr_samples/with_of.rb

@@ -28,7 +28,7 @@ end
 
 
 # A system for testing inheritance and of?
-system :with_reconf do
+system :with_of do
     input :clk,:rst
     input :d
     output :q

data/lib/HDLRuby/hdr_samples/with_program_c.rb

@@ -0,0 +1,28 @@
+
+# A benchmark for testing the use of Ruby software code.
+system :with_ruby_prog do
+    inner :clk
+    [8].inner :count, :echo
+
+    program(:c,:echo) do
+        actport clk.posedge
+        inport  inP: count
+        outport outP: echo
+        code "c_program/c_program"
+    end
+
+
+    timed do
+        clk <= 0
+        count <= 0
+        !10.ns
+        repeat(10) do
+            clk <= 1
+            !10.ns
+            count <= count + 1
+            clk <= 0
+            !10.ns
+        end
+
+    end
+end

data/lib/HDLRuby/hdr_samples/with_program_ruby.rb

@@ -0,0 +1,28 @@
+
+# A benchmark for testing the use of Ruby software code.
+system :with_ruby_prog do
+    inner :clk
+    [8].inner :count, :echo
+
+    program(:ruby,:echo) do
+        actport clk.posedge
+        inport  inP: count
+        outport outP: echo
+        code "ruby_program/echo.rb"
+    end
+
+
+    timed do
+        clk <= 0
+        count <= 0
+        !10.ns
+        repeat(10) do
+            clk <= 1
+            !10.ns
+            count <= count + 1
+            clk <= 0
+            !10.ns
+        end
+
+    end
+end

data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb

@@ -0,0 +1,234 @@
+
+# A benchmark for testing the use of Ruby software code.
+system :with_ruby_prog_cpu do
+    ## The processor interface signals.
+
+    inner :sim              # The signal configuring the simulation.
+
+    inner :clk, :rst
+    inner :br, :bg, :rwb
+    [16].inner :addr
+    [8].inner  :dout #, :din
+    inner :req, :ack
+
+    [8].inner :key_reg      # Memory-mapped register containing the latest key.
+
+    ## The configuration parameters.
+    [9].inner :hSIZE, :hSTART, :hEND  # Display horizontal size and borders.
+    [8].inner :vSIZE, :vSTART, :vEND  # Display vertical size and borders.
+    [8].inner :rxCYCLE              # Time for transmitting one bit with the UART
+    [16].inner :vADDR, :kADDR         # The display and keyboard start addresses 
+
+    program(:ruby,:configure) do
+        actport sim.posedge
+        outport hSIZE: hSIZE, hSTART: hSTART, hEND: hEND
+        outport vSIZE: vSIZE, vSTART: vSTART, vEND: vEND
+        outport rxCYCLE: rxCYCLE
+        outport vADDR: vADDR, kADDR: kADDR
+        code "ruby_program/sw_cpu_terminal.rb"
+    end
+
+    ## The processor model.
+
+    # This is the bus part of the CPU.
+    program(:ruby,:cpu_bus) do
+        actport clk.posedge
+        inport  br:   br      # Bus request
+        outport bg:   bg      # Bus granted
+        inport  ain:  addr
+        inport  aout: addr
+        inport  rwb:  rwb
+        # inport  din:  din
+        outport dout: dout
+
+        inport key_reg: key_reg
+
+        code "ruby_program/sw_cpu_terminal.rb"
+    end
+
+    # This is the reset part of the CPU.
+    program(:ruby, :cpu_rst) do
+        actport rst.posedge
+        code "ruby_program/sw_cpu_terminal.rb"
+    end
+
+    # This is the interrupt part of the CPU.
+    program(:ruby,:cpu_irq) do
+        actport req.posedge
+        outport ack:   ack
+        code "ruby_program/sw_cpu_terminal.rb"
+    end
+
+
+    ## Simplistic circuitry that generates a monochrome video signal
+    #  For a 320x200 screen with 512-320 pixels horizontal blank and 
+    #  256-200 lines vertical blank and centered screen.
+    #  The memory bus is requested at the begining of a line, and if it is
+    #  not granted on time the pixels are skipped.
+
+    [1].inner :vclk_count
+    inner :vclk
+    [9].inner :hcount
+    [8].inner :vcount
+    [16].inner :vaddr
+    inner :hblank, :vblank
+    [8].inner :pixel
+
+    # Generate the video clock: every 4 cycles (for not too long simulation).
+    # NOTE: requires reset to last two cycles or more.
+    seq(clk.posedge) do
+        hif(rst) { vclk_count <= 0; vclk <=0 }
+        helse do
+            vclk_count <= vclk_count + 1
+            hif(vclk_count == 1) { vclk <= ~vclk }
+        end
+    end
+
+    # Generates the signal.
+    seq(vclk.posedge,rst.posedge) do
+        hif(rst) do
+            hcount <= 0; vcount <= 0
+            hblank <= 0; vblank <= 0
+            vaddr <= vADDR
+            pixel <= 0
+        end
+        helse do
+            hif((hcount >= hSIZE + hSTART) | (hcount < hSTART)) { hblank <= 1 }
+            hif((vcount >= vSIZE + vSTART) | (vcount < vSTART)) { vblank <= 1 }
+            hif((hcount < hSIZE+hSTART) & (vcount < vSIZE+vSTART) & (vcount >= vSTART)) { br <= 1 } #; rwb <= 1 }
+            helse { br <= 0} #; rwb <= 0 }
+            hif((hcount >= hSTART) & (hcount < hSIZE+hSTART) &
+                (vcount >= vSTART) & (vcount < vSIZE+vSTART)) do
+                hblank <= 0; vblank <= 0
+                hif(bg) { pixel <= dout }
+                vaddr <= vaddr + 1
+            end
+            hcount <= hcount + 1
+            hif(hcount >= hSIZE+hSTART+hEND) do
+                hcount <= 0
+                vcount <= vcount + 1
+                hif (vcount >= vSIZE+vSTART+vEND) do
+                    vcount <= 0
+                    vaddr  <= vADDR
+                end
+            end
+        end
+    end
+
+    # Connect to the memory as well as the keyboard register.
+    rwb  <= mux(bg, _b0, _b1)
+    # addr <= mux(bg, kADDR, vaddr)
+    addr <= mux(bg, _hzz, vaddr)
+
+    # # Connect the key register.
+    # din <= mux(~bg, _hzz, key_reg)
+
+    # This is the monitor simulator.
+    program(:ruby,:monitor) do
+        actport vclk.negedge
+        inport vblank: vblank, hblank: hblank, pixel: pixel
+        code "ruby_program/sw_cpu_terminal.rb"
+    end
+
+
+    ## Simplisitic circuitry that receives bytes from a UART and write them
+    #  into a memory-map register before raising an interrupt.
+    #  Only 8-bit values, and no parity.
+
+    # The clock signal generation of the keyboard device
+    [2].inner :uclk_count 
+    inner     :uclk, :urst
+
+    # Generate the UART chip clock: every 8 cycles (for not too long
+    # simulation).
+    seq(clk.posedge) do
+        hif(rst) { uclk_count <= 0; uclk <= 0; urst <= 1 }
+        helse do
+            uclk_count <= uclk_count + 1
+            hif(uclk_count == 1) { uclk <= ~uclk }
+            hif(uclk_count == 0) { urst <= 0 }
+        end
+    end
+
+    # The UART signals.
+    inner :rx
+
+    # This is the UART keyboard simulator.
+    program(:ruby,:keyboard) do
+        actport uclk.negedge
+        outport rx: rx
+        code "ruby_program/sw_cpu_terminal.rb"
+    end
+
+    # The signals for getting key values from UART
+    [2].inner :rx_bit_count # The received bit count.
+    [8].inner :rx_bits      # The rx bit buffer (a shift register).
+
+    # The sequencer receiving the keyboard data and writing the to a
+    # memory-mapped register.
+    sequencer(uclk.posedge,urst) do
+        sloop do
+            # At first no interrupt and nothing received yet.
+            req          <= 0
+            rx_bit_count <= 0
+            rx_bits      <= 0
+            key_reg      <= 0
+
+            # Wait for a start bit: falling edge of rx.
+            swhile(rx != 0)
+            # Now can get the 8 bits.
+            8.stimes do
+                # Wait one Rx cycle.
+                rxCYCLE.stimes;
+                # Get one bit.
+                rx_bits <= [rx_bits[6..0],rx]
+            end
+            # All is done, wait end of transmission.
+            swhile(rx == 0)
+            # Save the received value.
+            key_reg <= rx_bits
+            # And wait the computer is ready to receive an interrupt
+            # and the BUS is not used by the video chip.
+            swhile((ack == 1) | (rwb == 1) )
+            # Now raise an interrupt.
+            req <= 1
+            # Wait for its process to start.
+            swhile(ack != 0)
+        end
+    end
+
+
+
+
+    ## The simulation part.
+
+    timed do
+        clk   <= 0
+        rst   <= 0
+        sim   <= 0
+        !10.ns
+        sim <= 1
+        !10.ns
+        sim <= 0
+        repeat(5) do
+          !10.ns
+          clk <= 1
+          !10.ns
+          clk <= 0
+        end
+        rst <= 1
+        repeat(5) do
+          !10.ns
+          clk <= 1
+          !10.ns
+          clk <= 0
+        end
+        rst <= 0
+        repeat(10_000_000) do
+          !10.ns
+          clk <= 1
+          !10.ns
+          clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb

@@ -0,0 +1,23 @@
+system :accum do
+  inner :clk
+  [32].inner :sigI, :sigO
+
+  program(:ruby,:stdrw) do
+    actport clk.posedge
+    outport sigI: sigI
+    inport  sigO: sigO
+    code "ruby_program/stdrw.rb"
+  end
+
+  (sigO <= sigO+sigI).at(clk.negedge)
+
+  timed do
+    clk <= 0
+    sigO <= 0
+    sigI <= 0
+    repeat(10) do
+       !10.ns
+       clk <= ~clk
+    end
+  end
+end

data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb

@@ -0,0 +1,58 @@
+
+# A benchmark for testing the use of Ruby software code.
+system :with_ruby_prog_mem do
+    inner :clk, :req, :rwb
+    [8].inner :addr, :index, :count, :data
+
+    # This is actually a CPU embedded memory.
+    program(:ruby,:mem) do
+        actport clk.posedge
+        inport  addr: addr
+        inport  rwb:  rwb
+        inport  din:  count
+        outport dout: data
+        code "ruby_program/sw_inc_mem.rb"
+    end
+
+    # This is real software.
+    program(:ruby,:inc_mem) do
+        actport req.posedge
+        inport  index: index
+        code "ruby_program/sw_inc_mem.rb"
+    end
+
+
+    timed do
+        clk   <= 0
+        addr  <= 0
+        index <= 0
+        req   <= 0
+        count <= 0
+        rwb   <= 0
+        !10.ns
+        req <= 1
+        !10.ns
+        repeat(10) do
+            clk   <= 1
+            req   <= 0
+            !10.ns
+            req   <= 1
+            clk   <= 0
+            count <= count + 2
+            addr  <= addr + 1
+            !10.ns
+            index <= index + 1
+        end
+        !10.ns
+        addr <= 0
+        clk  <= 0
+        rwb  <= 1
+        repeat(10) do
+            !10.ns
+            clk  <= 1
+            !10.ns
+            clk  <= 0
+            addr <= addr + 1
+        end
+    end
+end