HDLRuby 3.1.0 → 3.3.0

data/lib/HDLRuby/std/clocks.rb

@@ -4,10 +4,10 @@ module HDLRuby::High::Std
 # Standard HDLRuby::High library: clocks
 # 
 ########################################################################
-
+    @@__clocks_rst = nil
 
     # Initialize the clock generator with +rst+ as reset signal.
-    def configure_clocks(rst = $rst)
+    def configure_clocks(rst = nil)
         @@__clocks_rst = rst
     end
 
@@ -19,13 +19,22 @@ module HDLRuby::High::Std
         HDLRuby::High.cur_system.open do
 
             # Ensures times is a value.
-            times = times.to_value
+            times = times.to_value - 1
+            if (times == 0) then
+              AnyError.new("Clock multiplier must be >= 2.") 
+            end
 
             # Create the counter.
             # Create the name of the counter.
             name = HDLRuby.uniq_name
             # Declare the counter.
-            [times.width].inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                [times.width].inner(name)
+            else
+                # There is no reset, so need to initialize.
+              [times.width].inner(name => times)
+            end
             # Get the signal of the counter.
             counter = get_inner(name)
 
@@ -33,51 +42,77 @@ module HDLRuby::High::Std
             # Create the name of the clock.
             name = HDLRuby.uniq_name
             # Declares the clock.
-            bit.inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                bit.inner(name)
+            else
+                # There is no reset, so need to initialize.
+                bit.inner(name => times)
+            end
             # Get the signal of the clock.
             clock = get_inner(name)
             
             # Control it.
             par(event) do
-                hif(@@__clocks_rst) do
-                    counter.to_ref <= times.to_expr
-                    clock.to_ref <= 0
-                end
-                helsif(counter.to_expr == 0) do
-                    counter.to_ref <= times.to_expr 
-                    clock.to_ref <= ~ clock.to_expr
-                end
-                helse do
-                    counter.to_ref <= counter.to_expr + 1
+                if @@__clocks_rst then
+                    # There is a reset, handle it.
+                    hif(@@__clocks_rst) do
+                      counter <= times
+                        clock <= 0
+                    end
+                    helsif(counter.to_expr == 0) do
+                        counter <= times 
+                        clock   <= ~ clock
+                    end
+                    helse do
+                        counter <= counter - 1
+                    end
+                else
+                    # There is no reset.
+                    hif(counter == 0) do
+                        counter <= times 
+                        clock   <= ~ clock
+                    end
+                    helse do
+                        counter <= counter - 1
+                    end
                 end
             end
         end
         return clock
     end
 
-    # module clk_div3(clk,reset, clk_out);
-
-    #     input clk;
-    #     input reset;
-    #     output clk_out;
-
-    #     reg [1:0] pos_count, neg_count;
-    #     wire [1:0] r_nxt;
-
-    #     always @(posedge clk)
-    #     if (reset)
-    #         pos_count <=0;
-    #     else if (pos_count ==2) pos_count <= 0;
-    #     else pos_count<= pos_count +1;
 
-    #     always @(negedge clk)
-    #     if (reset)
-    #         neg_count <=0;
-    #     else  if (neg_count ==2) neg_count <= 0;
-    #     else neg_count<= neg_count +1;
+# https://referencedesigner.com/tutorials/verilogexamples/verilog_ex_07.php
+# 
+# module clk_divn #(
+# parameter WIDTH = 3,
+# parameter N = 5)
+#  
+# (clk,reset, clk_out);
+#  
+# input clk;
+# input reset;
+# output clk_out;
+#  
+# reg [WIDTH-1:0] pos_count, neg_count;
+# wire [WIDTH-1:0] r_nxt;
+#  
+#  always @(posedge clk)
+#  if (reset)
+#  pos_count <=0;
+#  else if (pos_count ==N-1) pos_count <= 0;
+#  else pos_count<= pos_count +1;
+#  
+#  always @(negedge clk)
+#  if (reset)
+#  neg_count <=0;
+#  else  if (neg_count ==N-1) neg_count <= 0;
+#  else neg_count<= neg_count +1; 
+#  
+# assign clk_out = ((pos_count > (N>>1)) | (neg_count > (N>>1))); 
+# endmodule
 
-    #     assign clk_out = ((pos_count == 2) | (neg_count == 2));
-    # endmodule
 
     # Creates a clock inverted every +times+ occurence of an +event+ and its
     # everted.
@@ -87,13 +122,22 @@ module HDLRuby::High::Std
         # Enters the current system
         HDLRuby::High.cur_system.open do
             # Ensure times is a value.
-            times = times.to_value
+            times = times.to_value 
+            if (times == 1) then
+              AnyError.new("Clock multiplier must be >= 2.") 
+            end
 
             # Create the event counter.
             # Create the name of the counter.
             name = HDLRuby.uniq_name
             # Declare the counter.
-            [times.width].inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                [times.width].inner(name)
+            else
+                # There is no reset, so need to initialize.
+                [times.width].inner(name => 0)
+            end
             # Get the signal of the counter.
             counter = get_inner(name)
 
@@ -101,7 +145,13 @@ module HDLRuby::High::Std
             # Create the name of the counter.
             name = HDLRuby.uniq_name
             # Declare the counter.
-            [times.width].inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                [times.width].inner(name)
+            else
+                # There is no reset, so need to initialize.
+              [times.width].inner(name => 0)
+            end
             # Get the signal of the counter.
             counter_inv = get_inner(name)
 
@@ -109,32 +159,50 @@ module HDLRuby::High::Std
             # Create the name of the clock.
             name = HDLRuby.uniq_name
             # Declare the clock.
-            bit.inner(name)
+            if @@__clocks_rst then
+                # There is a reset, so no need to initialize.
+                bit.inner(name)
+            else
+                # There is no reset, so need to initialize.
+                bit.inner(name => 0)
+            end
             # Get the signal of the clock.
             clock = get_inner(name)
 
-            # Control the event counter
+            # Control the even counter.
             par(event) do
-                hif(@@__clocks_rst | counter.to_expr == 0) do
-                    counter.to_ref <= times.to_expr/2 + 1
+                if @@__clocks_rst then
+                    hif(@@__clocks_rst)        { counter <= 0 }
+                    helsif(counter == times-1) { counter <= 0 }
+                    helse                      { counter <= counter + 1 }
+                else
+                    hif(counter == times-1)     { counter <= 0 }
+                    helse                      { counter <= counter + 1 }
                 end
             end
-            # Control the inverteed event counter
+
+            # Control the odd counter.
             par(event.invert) do
-                hif(@@__clocks_rst | counter_inv.to_expr == 0) do
-                    counter_inv.to_ref <= times.to_expr/2 + 1
+                if @@__clocks_rst then
+                    hif(@@__clocks_rst)        { counter_inv <= 0 }
+                    helsif(counter == times-1) { counter_inv <= 0 }
+                    helse                      { counter_inv <= counter_inv + 1 }
+                else
+                    hif(counter == times-1)     { counter_inv <= 0 }
+                    helse                      { counter_inv <= counter_inv + 1 }
                 end
             end
-            # Compute the clock.
-            clock.to_ref <= (counter.to_expr == times.to_expr/2 + 1) |
-                (counter_inv.to_expr == times.to_expr/2 + 1)
+
+            clock <= ((counter > (times/2)) | (counter_inv > (times/2)))
         end
-        # Return it.
+        # Return the clock.
         return clock
     end
+
 end
 
 
+
 class HDLRuby::High::Event
     # Enhance the events with multiply operator.
 

data/lib/HDLRuby/std/fixpoint.rb

@@ -53,9 +53,9 @@ module HDLRuby::High::Std
                         # Redefine the multiplication and division for fixed point.
                         typ.define_operator(:*) do |left,right|
                             if (typ.signed?) then
-                                (left.as(signed[isize+fsize*2])*right) >> fsize
+                                ((left.as(signed[isize+fsize*2])*right) >> fsize).as(typ)
                             else
-                                (left.as(bit[isize+fsize*2])*right) >> fsize
+                                ((left.as(bit[isize+fsize*2])*right) >> fsize).as(typ)
                             end
                         end
                         typ.define_operator(:/) do |left,right|

data/lib/HDLRuby/std/function_generator.rb

@@ -75,7 +75,7 @@ module HDLRuby::High::Std
         base <= lut[address]
 
         # Assign the next_data discrete value.
-        next_data <= lut[address+_b1.as(address.type)]
+        next_data <= mux(address < lut_size-1,lut[address],lut[address+_b1.as(address.type)])
     end
 
 

data/lib/HDLRuby/std/linear.rb

@@ -16,7 +16,7 @@ module HDLRuby::High::Std
     # - +ruby_block+: the code of the linear computation kernel, it takes
     #                 as argument +ev+, and its own req and ack signals
     #                 (resp. +req_ker+ +ack_ker+).
-    function :linearun do |num,ev,req,ack,ruby_block|
+    hdef :linearun do |num,ev,req,ack,ruby_block|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
 
@@ -57,7 +57,7 @@ module HDLRuby::High::Std
     # Delcares a vector product by a scalar value.
     #
     # Can be used for scaling a vector.
-    function :scale do |typ,ev,req,ack,left,rights,prods,
+    hdef :scale do |typ,ev,req,ack,left,rights,prods,
                         mul = proc { |x,y| x*y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -101,7 +101,7 @@ module HDLRuby::High::Std
     # Declares a 1-dimension vector adder.
     #
     # Can be used for the sum of two vectors.
-    function :add_n do |typ,ev,req,ack,lefts, rights, sums,
+    hdef :add_n do |typ,ev,req,ack,lefts, rights, sums,
                         add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -143,7 +143,7 @@ module HDLRuby::High::Std
     end
 
     # Declares a 1-dimension vector element-wise multiplier.
-    function :mul_n do |typ,ev,req,ack,lefts, rights, prods,
+    hdef :mul_n do |typ,ev,req,ack,lefts, rights, prods,
                         mul = proc { |x,y| x*y }|
         add_n(typ,ev,req,ack,lefts,rights,prods,mul)
     end
@@ -152,7 +152,7 @@ module HDLRuby::High::Std
     # Declares a simple multiplier accumulator.
     #
     # Can be used for the scalar product of two vectors.
-    function :mac do |typ,ev,req,ack,left, right, acc,
+    hdef :mac do |typ,ev,req,ack,left, right, acc,
         mul = proc { |x,y| x*y }, add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -193,7 +193,7 @@ module HDLRuby::High::Std
     # Declares a simple multiple mac with single right data.
     #
     # Can be used for the product of a martix-vector product.
-    function :mac_n1 do |typ,ev,req,ack,lefts, right, accs,
+    hdef :mac_n1 do |typ,ev,req,ack,lefts, right, accs,
         mul = proc { |x,y| x*y }, add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -262,7 +262,7 @@ module HDLRuby::High::Std
     # Declares a simple pipelined multiple mac with single right data.
     #
     # Can be used for the product of a martix-vector product.
-    function :mac_np do |typ,ev,req,ack,lefts, rights, last,
+    hdef :mac_np do |typ,ev,req,ack,lefts, rights, last,
         mul = proc { |x,y| x*y }, add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)