HDLRuby 3.1.0 → 3.3.0

data/lib/HDLRuby/hruby_low_without_namespace.rb

@@ -122,10 +122,17 @@ module HDLRuby::Low
             # Extract the connections of the sub scopes.
             cnxs = self.each_scope.map(&:extract_connections!).flatten
             # Reinsert them to self.
-            cnxs.each { |beh| self.add_connection(beh) }
+            cnxs.each { |cnx| self.add_connection(cnx) }
+
+            # The fix the RefName using sub scopes since their target have
+            # been deplaced to current scope and renamed.
+            self_scopes = self.each_scope.to_a
+            self.each_behavior { |beh| beh.fix_scope_refnames!(self_scopes) }
+            self.each_connection { |cnx| cnx.fix_scope_refnames!(self_scopes) }
 
             # Now can delete the sub scopes since they are empty.
-            self.each_scope.to_a.each { |scope| self.delete_scope!(scope) }
+            # self.each_scope.to_a.each { |scope| self.delete_scope!(scope) }
+            self_scopes.each { |scope| self.delete_scope!(scope) }
         end
 
         # Extract the behaviors from the scope and returns them into an array.
@@ -219,9 +226,10 @@ module HDLRuby::Low
         # in the internals.
         def replace_names_subs!(former,nname)
             # puts "replace_names_subs! for #{self} with former=#{former} and nname=#{nname}"
-            self.each_type do |type|
-                type.replace_names!(former,nname)
-            end
+            # No need? 
+            # self.each_type do |type|
+            #     type.replace_names!(former,nname)
+            # end
             self.each_systemT do |systemT|
                 systemT.replace_names!(former,nname)
             end
@@ -460,6 +468,13 @@ module HDLRuby::Low
             # Recurse on the block.
             self.block.replace_names!(former,nname)
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+          self.block.fix_scope_refnames!(scopes)
+          return self
+        end
     end
 
 
@@ -498,6 +513,34 @@ module HDLRuby::Low
                 node.break_types!(types)
             end
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+          # By default, does nothing.
+          return self
+        end
+    end
+
+
+    class Transmit
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            self.set_left!(self.left.fix_scope_refnames!(scopes))
+            self.set_right!(self.right.fix_scope_refnames!(scopes))
+            return self
+        end
+    end
+
+    class Connection
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            self.set_left!(self.left.fix_scope_refnames!(scopes))
+            self.set_right!(self.right.fix_scope_refnames!(scopes))
+            return self
+        end
     end
 
 
@@ -527,6 +570,16 @@ module HDLRuby::Low
                 end
             end
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            # By default: recurse.
+            self.map_nodes! do |node|
+                node.fix_scope_refnames!(scopes)
+            end
+            return self
+        end
     end
 
     
@@ -578,6 +631,24 @@ module HDLRuby::Low
             # Recurse on the no if any.
             self.no.replace_names!(former,nname) if self.no
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            # Fix the condition.
+            self.set_condition!(self.condition.fix_scope_refnames!(scopes))
+            # Recurse on the yes.
+            self.yes.fix_scope_refnames!(scopes)
+            # Recurse on the alternate ifs.
+            self.map_noifs! do |cond,stmnt|
+                cond = cond.fix_scope_refnames!(scopes)
+                stmnt = stmnt.fix_scope_refnames!(scopes)
+                [cond,stmnt]
+            end
+            # Recruse on the no if any.
+            self.no.fix_scope_refnames!(scopes) if self.no
+            return self
+        end
     end
 
 
@@ -618,6 +689,16 @@ module HDLRuby::Low
                 end
             end
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            # Fix the match.
+            self.set_match!(self.match.fix_scope_refnames!(scopes))
+            # Recurse on the statement.
+            self.statement.fix_scope_refnames!(scopes)
+            return self
+        end
     end
 
 
@@ -655,6 +736,18 @@ module HDLRuby::Low
             # Recurse on the default.
             self.default.replace_names!(former,nname) if self.default
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            # Fix the value.
+            self.set_value!(self.value.fix_scope_refnames!(scopes))
+            # Recurse on the whens.
+            self.each_when {|w| w.fix_scope_refnames!(scopes) }
+            # Recurse on the default.
+            self.default.fix_scope_refnames!(scopes) if self.default
+            return self
+        end
     end
 
 
@@ -681,6 +774,14 @@ module HDLRuby::Low
             # Recurse on the statement.
             self.statement.replace_names!(former,nname)
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            # Recurse on the statement.
+            self.statement.fix_scope_refnames!(scopes)
+            return self
+        end
     end
 
 
@@ -738,6 +839,33 @@ module HDLRuby::Low
             # Recurse on the sub scopes and behaviors.
             replace_names_subs!(former,nname)
         end
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            self.each_statement {|stmnt| stmnt.fix_scope_refnames!(scopes) }
+            return self
+        end
+    end
+
+
+    class RefName
+        include ForceName
+
+        # Fix the references names using scopes given in +scopes + list (they
+        # are marked to be deleted).
+        def fix_scope_refnames!(scopes)
+            return self unless self.ref.is_a?(RefName)
+            # puts "fix_scope_refnames! with self.name=#{name} and self.ref=#{self.ref}"
+            # Recurse on the ref.
+            self.set_ref!(self.ref.fix_scope_refnames!(scopes))
+            # Rename and curt the subref if referening to one of the scopes.
+            if scopes.find {|scope| scope.name == self.ref.name } then
+                self.ref.extend_name!(self)
+                self.set_ref!(RefThis.new)
+            end
+            return self
+        end
     end
 
 end

data/lib/HDLRuby/hruby_low_without_subsignals.rb

@@ -243,7 +243,6 @@ module HDLRuby::Low
         # Flatten a reference to a list of reference to leaf signals
         # from signal +sig+ and add to result to +subrefs+
         def flatten_to(sig,subrefs)
-            # puts "flatten_to with sig name=#{sig.name}"
             # Shall we decompose 2d vectors, and is the current signal
             # for one of them?
             if SystemT.decompose_vec2d? and sig.type.is_a?(TypeVector) and
@@ -294,6 +293,7 @@ module HDLRuby::Low
         # Decompose the hierarchical signals in the statements.
         def signal2subs!
             # puts "signal2subs! for RefName: #{self.name}"
+            return self if self.type == void # Not a singal anyway.
             # Decompose it to a list of reference to each leaf sub signal.
             subrefs = []
             self.flatten_to(self.resolve,subrefs)

data/lib/HDLRuby/hruby_rcsim.rb

@@ -3,6 +3,8 @@ require 'HDLRuby'
 require 'hruby_high_fullname'
 require 'hruby_sim/hruby_sim'
 
+require 'rubyHDL'
+
 
 module HDLRuby::High
 
@@ -189,7 +191,6 @@ module HDLRuby::High
             rcbehs = self.each_behavior.map {|beh| beh.to_rcsim(subowner)} # +
                 # self.each_connection.map {|cxt| cxt.to_rcsim(subowner) }
             self.each_connection do |cnx|
-                # ICIICI
                 if !cnx.right.is_a?(RefObject) then
                     rcbehs << cnx.to_rcsim(subowner)
                 else
@@ -209,8 +210,11 @@ module HDLRuby::High
                 RCSim.rcsim_add_scope_behaviors(@rcscope,rcbehs)
             end
 
-            # Create and add the codes.
-            # TODO!!
+            # Create and add the programs.
+            rcprogs = self.each_program.map {|prog| prog.to_rcsim(subowner)} 
+            if rcprogs.any? then
+                RCSim.rcsim_add_scope_codes(@rcscope,rcprogs);
+            end
 
             return @rcscope
         end
@@ -512,12 +516,92 @@ module HDLRuby::High
 
     class Chunk
         ## Extends the Chunk class for hybrid Ruby-C simulation.
-        # TODO!!
+        # Deprecated!!
     end
 
     class Code
         ## Extends the Code class for hybrid Ruby-C simulation.
-        # TODO!!
+        # Deprecated!!
+    end
+
+    class Program
+        ## Extends the Program class for hybrid Ruby-C simulation.
+        #  NOTE: produce a low-level Code, and not program. For now,
+        #  Program is a high-level interface for software description and
+        #  is not ment to be simulated as is. It may hcange in the future 
+        #  though.
+
+        attr_reader :rccode # The access to the C version of the code.
+
+        # Generate the C description of the code comming from object
+        # whose C description is +rcowner+.
+        # NOTE: also update the table of signals accessed from software
+        # code.
+        def to_rcsim(rcowner)
+            # puts "to_rcsim for program=#{self}"
+
+            # Create the code C object.
+            # puts "make code with self.class=#{self.class}"
+            @rccode = RCSim.rcsim_make_code(self.language.to_s, self.function.to_s)
+
+            # Set the owner.
+            RCSim.rcsim_set_owner(@rccode,rcowner)
+
+            # Create and add the events.
+            if self.each_actport.any? then
+                RCSim.rcsim_add_code_events(@rccode, self.each_actport.map do|ev|
+                    ev.to_rcsim(@rccode)
+                end)
+            end
+
+            # Create the software interface.
+            if self.language == :ruby then
+                # Loads the code files.
+                self.each_code do |code|
+                    Kernel.require("./"+code.to_s)
+                end
+                # Add the input ports.
+                self.each_inport do |sym, sig|
+                    RubyHDL.inport(sym,sig.rcsignalI)
+                end
+                # Add the output ports.
+                self.each_outport do |sym, sig|
+                    RubyHDL.outport(sym,sig.rcsignalI)
+                end
+            elsif self.language == :c then
+                # Loads the code file: only the last one remains.
+                self.each_code do |code|
+                    code = code.to_s
+                    # Check if the file exists.
+                    unless File.file?(code) then
+                        # The code name may be not complete, 
+                        # try ".so", ".bundle" or ".dll" extensions.
+                        if File.file?(code+".so") then
+                            code += ".so"
+                        elsif File.file?(code + ".bundle") then
+                            code += ".bundle"
+                        elsif File.file?(code + ".dll") then
+                            code += ".dll"
+                        else
+                            # Code not found.
+                            raise "C code library not found: " + code
+                        end
+                    end
+                    RCSim.rcsim_load_c(@rccode,code,self.function.to_s)
+                end
+                # Add the input ports.
+                self.each_inport do |sym, sig|
+                    RCSim::CPorts[sym] = sig.rcsignalI
+                end
+                # Add the output ports.
+                self.each_outport do |sym, sig|
+                    RCSim::CPorts[sym] = sig.rcsignalI
+                end
+            end
+
+
+            return @rccode
+        end
     end
 
 
@@ -1000,7 +1084,30 @@ module HDLRuby::High
 
     class RefName
         ## Extends the RefName class for hybrid Ruby-C simulation.
-        # Should not be used with rcsim.
+        # Converted to RefRange.
+
+        # Generate the C description of the reference range (not ref name!).
+        def to_rcsim
+            # Convert the base to a bit vector.
+            type_base = Bit[self.ref.type.width]
+            # self.ref.parent = nil
+            # bit_base = Cast.new(type_base,self.ref)
+            bit_base = RCSim.rcsim_make_cast(type_base.to_rcsim,self.ref.to_rcsim)
+            # Compute range in bits of the field.
+            last = 0
+            self.ref.type.each.detect do |name,typ|
+                last += typ.width
+                name == self.name
+            end
+            first = last-self.type.width
+            last -= 1
+            # puts "name=#{self.name} first=#{first} last=#{last}"
+            type_int = Bit[type_base.width.width]
+            return RCSim.rcsim_make_refRange(self.type.to_rcsim,
+                                             Value.new(type_int,last).to_rcsim,
+                                             Value.new(type_int,first).to_rcsim,
+                                             bit_base)
+        end
     end
 
 

data/lib/HDLRuby/hruby_serializer.rb

@@ -23,7 +23,8 @@ module HDLRuby
                  Low::TypeSigned, Low::TypeUnsigned, Low::TypeFloat,
                  Low::TypeTuple, Low::TypeStruct,
                  Low::Behavior, Low::TimeBehavior, 
-                 Low::Event, Low::Block, Low::TimeBlock, Low::Code, 
+                 Low::Event, Low::Block, Low::TimeBlock, 
+                 Low::Program, Low::Code, 
                  Low::SignalI, Low::SignalC,
                  Low::SystemI, Low::Connection, 
                  Low::Transmit, Low::If, Low::Case, Low::When, Low::Cast,

data/lib/HDLRuby/hruby_verilog.rb

@@ -169,7 +169,17 @@ module HDLRuby::Low
 
         # Converts the system to Verilog code.
         def to_verilog
-            return "(#{self.left.to_verilog} #{self.operator} #{self.right.to_verilog})"
+            # In HDLRuby if on term is signed and the other is not, the
+            # computation is signed.
+            if self.left.type.signed? and self.right.type.unsigned? then
+                return "(#{self.left.to_verilog} #{self.operator} " +
+                    "$signed({1'b0,#{self.right.to_verilog}}))"
+            elsif self.left.type.unsigned? and right.type.signed? then
+                return "($signed({1'b0,#{self.left.to_verilog}})" +
+                    " #{self.operator} #{self.right.to_verilog})"
+            else
+                return "(#{self.left.to_verilog} #{self.operator} #{self.right.to_verilog})"
+            end
         end
 
         # Method called when two or more expression terms are present.
@@ -262,7 +272,6 @@ module HDLRuby::Low
             # Declaration of "inner" part within "always".
             block.each_inner do |inner|
                 if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
-                    # code << "      reg"
                     code << "#{" " * (spc+3)}reg"
                 else
                     code << "#{" " * (spc+3)}wire"
@@ -1501,7 +1510,14 @@ module HDLRuby::Low
 
         # Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
         def to_verilog
-            vname = name_to_verilog(self.name)
+            if (self.ref.is_a?(RefThis)) then
+                # End reference.
+                vname = name_to_verilog(self.name)
+            else
+                # Not end reference, recurse.
+                # vname = name_to_verilog(self.name) + "." + self.ref.to_verilog 
+                vname = self.ref.to_verilog + "." + name_to_verilog(self.name)
+            end
             # self.properties[:verilog_name] = vname
             return "#{vname}"
         end
@@ -1565,8 +1581,11 @@ module HDLRuby::Low
                 return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
             else
                 # No a pure signal, need to use a function for accessing.
-                sr = self.range.first.to_i..self.range.last.to_i
-                cr = (self.type.width-1)..0
+                # sr = self.range.first.to_i..self.range.last.to_i
+                # cr = (self.type.width-1)..0
+                sr = (self.range.first.to_i+1)*self.ref.type.base.width-1..
+                    self.range.last.to_i*self.ref.type.base.width
+                cr = (self.ref.type.width-1)..0
                 TruncersI.add(cr,sr)
                 return "#{TruncersI.truncer_name(cr,sr)}(#{self.ref.to_verilog})"
             end
@@ -1735,9 +1754,11 @@ module HDLRuby::Low
             if self.default then
                 result << " " * (spc+3) + "default: "
                 if self.default.each_statement.count >= 1 then
+                    result << "begin\n"
                     result << self.default.each_statement.map do |stmnt|
-                        stmnt.to_verilog(spc+3)
+                        stmnt.to_verilog(spc+6)
                     end.join("\n") << "\n"
+                    result << " " * (spc+3) + "end\n"
                 else
                     result << ";\n"
                 end
@@ -2027,11 +2048,60 @@ module HDLRuby::Low
         end
 
 
+        # Get the signals that can be declared as reg.
+        # If +vname+ is given, use as base for reference name.
+        def self.get_regs(expr,vname = nil)
+            if expr.is_a?(RefConcat) then
+                return expr.each_ref.map {|ref| self.get_regs(ref,vname) }.flatten
+            elsif expr.is_a?(RefName) then
+                if vname then
+                    puts "vname=#{vname} expr.name=#{expr.name}"
+                    if expr.ref && name_to_verilog(expr.name) == vname then
+                        return get_regs(expr.ref)
+                    else
+                        return []
+                    end
+                else
+                    return [expr]
+                end
+            else
+                return get_regs(expr.ref,vname)
+            end
+        end
+
+        # Get signals indirectly refered that have to become reg in
+        # a sub system. +vname+ is the name of the system whose signals
+        # are to be processed.
+        def self.get_indirect_verilog_regs(systemI,vname)
+            # Get the sub systemT.
+            sub_systemT = systemI.systemT
+            # Get the indirect reg inside it.
+            sub_systemT.each_behavior do |behavior|
+                behavior.each_block_deep do |block|
+                    block.each_statement do |statement|
+                        if statement.is_a?(Transmit) &&
+                                statement.left.to_verilog.include?(vname + ".")
+                            puts "hierachical=#{statement.left.to_verilog}"
+                            # HDLRuby::Low::VERILOG_REGS << SystemT.get_regs(statement.left.ref).to_verilog
+                            HDLRuby::Low::VERILOG_REGS.concat( SystemT.get_regs(statement.left,vname).map(&:to_verilog))
+                        end
+                    end
+                end
+            end
+            # And recurse on its systemIs.
+            sub_systemT.each_systemI do |sub_systemI|
+                SystemT.get_indirect_verilog_regs(sub_systemI,vname)
+            end
+        end
+
 
         # Converts the system to Verilog code.
         # NOTE: if +vcd+ is true, generate verilog code whose simulation
         #       produces a vcd file.
         def to_verilog(vcd = false)
+            # Create the name of the module.
+            vname = name_to_verilog(self.name)
+            # puts "Processing systemT named=#{vname}"
             # Detect the registers
             HDLRuby::Low::VERILOG_REGS.clear
             # The left values.
@@ -2039,11 +2109,15 @@ module HDLRuby::Low
                 behavior.each_block_deep do |block|
                     block.each_statement do |statement|
                         if statement.is_a?(Transmit)
-                            HDLRuby::Low::VERILOG_REGS << statement.left.to_verilog
+                            # HDLRuby::Low::VERILOG_REGS << SystemT.get_regs(statement.left).to_verilog
+                            HDLRuby::Low::VERILOG_REGS.concat(SystemT.get_regs(statement.left).map(&:to_verilog))
                         end
                     end
                 end
             end
+            self.each_systemI do |systemI|
+                SystemT.get_indirect_verilog_regs(systemI,vname)
+            end
             # And the initialized signals.
             self.each_output do |output|
                 # regs << output.to_verilog if output.value
@@ -2053,17 +2127,18 @@ module HDLRuby::Low
                 # regs << inner.to_verilog if inner.value
                 HDLRuby::Low::VERILOG_REGS << inner.to_verilog if inner.value
             end
-            # And the array types signals.
-            self.each_signal do |sig|
-                if sig.type.vector? && sig.type.base.vector? then
-                    HDLRuby::Low::VERILOG_REGS << sig.to_verilog
-                end
-            end
-            self.each_inner do |sig|
-                if sig.type.vector? && sig.type.base.vector? then
-                    HDLRuby::Low::VERILOG_REGS << sig.to_verilog
-                end
-            end
+            # Actual NOT...
+            # # And the array types signals.
+            # self.each_signal do |sig|
+            #     if sig.type.vector? && sig.type.base.vector? then
+            #         HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            #     end
+            # end
+            # self.each_inner do |sig|
+            #     if sig.type.vector? && sig.type.base.vector? then
+            #         HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            #     end
+            # end
 
             # Code generation
             inputs = 0
@@ -2077,7 +2152,6 @@ module HDLRuby::Low
             # Spelling necessary for simulation.
             code = "`timescale 1ps/1ps\n\n"
 
-            vname = name_to_verilog(self.name)
             # self.properties[:verilog_name] = vname
             # Output the module name.
             code << "module #{vname}("
@@ -2315,7 +2389,7 @@ module HDLRuby::Low
                     codeC << "   initial "
                 else
                     # Generate a standard process.
-                    codeC << "   always @( "
+                    codeC << "\n   always @( "
                     # If there is no "always" condition, it is always @("*").
                     if behavior.each_event.to_a.empty? then
                         codeC << "*"

data/lib/HDLRuby/hruby_verilog_name.rb

@@ -8,26 +8,11 @@ module HDLRuby::Verilog
   # puts n            
   # name = n.split("")
 
-  @@hdr2verilog = {}
+  @@hdr2verilog = { "buf" => "_v0_buf", "table" => "_v1_table", "time" => "_v2_time" }
 
   # Since it is possible to use $ and numbers other than the beginning of the character string, it is divided.
   def name_to_verilog(name)
-      # name = name.to_s
-      # # Convert special characters.
-      # name = name.each_char.map do |c|
-      #     if c=~ /[a-z0-9]/ then
-      #         c
-      #     elsif c == "_" then
-      #         "__"
-      #     else
-      #         "_" + c.ord.to_s
-      #     end
-      # end.join
-      # # First character: only letter is possible.
-      # unless name[0] =~ /[a-z_]/ then
-      #     name = "_" + name
-      # end
-      # return name
+      # puts "name_to_verilog with name=#{name}"
       name = name.to_s
       vname = @@hdr2verilog[name]
       unless vname then
@@ -41,6 +26,7 @@ module HDLRuby::Verilog
           end
           @@hdr2verilog[name] = vname
       end
+      # puts "result vname=#{vname}"
       return vname
   end