HDLRuby 2.11.11 → 3.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.html +3274 -0
- data/README.md +608 -99
- data/ext/hruby_sim/hruby_rcsim_build.c +27 -0
- data/ext/hruby_sim/hruby_sim.h +3 -0
- data/ext/hruby_sim/hruby_sim_calc.c +2 -0
- data/ext/hruby_sim/hruby_sim_core.c +17 -5
- data/ext/hruby_sim/hruby_sim_stack_calc.c +1 -1
- data/ext/hruby_sim/hruby_sim_tree_calc.c +8 -1
- data/ext/hruby_sim/hruby_sim_vcd.c +24 -7
- data/ext/hruby_sim/hruby_sim_vizualize.c +9 -1
- data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
- data/lib/HDLRuby/hdr_samples/constant_in_function.rb +3 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +3 -1
- data/lib/HDLRuby/hdr_samples/huge_rom.rb +1 -1
- data/lib/HDLRuby/hdr_samples/mei8.rb +11 -11
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +12 -12
- data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +4 -4
- data/lib/HDLRuby/hdr_samples/rom_nest.rb +1 -1
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +4 -4
- data/lib/HDLRuby/hdr_samples/struct.rb +44 -10
- data/lib/HDLRuby/hdr_samples/with_bram.rb +45 -0
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_casts.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_concat.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -2
- data/lib/HDLRuby/hdr_samples/with_def.rb +10 -3
- data/lib/HDLRuby/hdr_samples/with_define_operator.rb +44 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -12
- data/lib/HDLRuby/hdr_samples/with_init.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_leftright.rb +21 -0
- data/lib/HDLRuby/hdr_samples/with_reduce.rb +13 -13
- data/lib/HDLRuby/hdr_samples/with_ref_array.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
- data/lib/HDLRuby/hdr_samples/with_subsums.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_terminate.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_to_a.rb +10 -10
- data/lib/HDLRuby/hdr_samples/with_values.rb +3 -3
- data/lib/HDLRuby/hdrcc.rb +29 -3
- data/lib/HDLRuby/hdrlib.rb +1 -1
- data/lib/HDLRuby/hruby_bstr.rb +10 -5
- data/lib/HDLRuby/hruby_db.rb +2 -2
- data/lib/HDLRuby/hruby_high.rb +152 -47
- data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +189 -18
- data/lib/HDLRuby/hruby_low2c.rb +129 -54
- data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
- data/lib/HDLRuby/hruby_low2high.rb +86 -44
- data/lib/HDLRuby/hruby_low2seq.rb +26 -18
- data/lib/HDLRuby/hruby_low2sym.rb +14 -13
- data/lib/HDLRuby/hruby_low2vhd.rb +80 -44
- data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
- data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
- data/lib/HDLRuby/hruby_low_fix_types.rb +65 -32
- data/lib/HDLRuby/hruby_low_mutable.rb +83 -119
- data/lib/HDLRuby/hruby_low_resolve.rb +38 -30
- data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
- data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
- data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
- data/lib/HDLRuby/hruby_low_without_concat.rb +45 -19
- data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +32 -16
- data/lib/HDLRuby/hruby_low_without_select.rb +37 -24
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +280 -0
- data/lib/HDLRuby/hruby_rcsim.rb +158 -134
- data/lib/HDLRuby/hruby_rsim.rb +194 -20
- data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
- data/lib/HDLRuby/hruby_rsim_vcd.rb +125 -50
- data/lib/HDLRuby/hruby_values.rb +48 -33
- data/lib/HDLRuby/hruby_verilog.rb +90 -48
- data/lib/HDLRuby/soft/stacks.rb +219 -0
- data/lib/HDLRuby/std/bram.rb +26 -0
- data/lib/HDLRuby/std/clocks.rb +1 -1
- data/lib/HDLRuby/std/fixpoint.rb +2 -2
- data/lib/HDLRuby/std/fsm.rb +48 -11
- data/lib/HDLRuby/std/function_generator.rb +2 -2
- data/lib/HDLRuby/std/sequencer.rb +1857 -0
- data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
- data/lib/HDLRuby/std/std.rb +12 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/tuto/adder_sat_flags_vcd.png +0 -0
- data/tuto/addsub_vcd.png +0 -0
- data/tuto/alu_vcd.png +0 -0
- data/tuto/bit_pong_vcd.png +0 -0
- data/tuto/checksum_vcd.png +0 -0
- data/tuto/circuit_hdr.odg +0 -0
- data/tuto/circuit_hdr.png +0 -0
- data/tuto/circuit_hie.odg +0 -0
- data/tuto/circuit_hie.png +0 -0
- data/tuto/circuit_view.odg +0 -0
- data/tuto/circuit_view.png +0 -0
- data/tuto/clock_counter_vcd.png +0 -0
- data/tuto/counter_ext_vcd.png +0 -0
- data/tuto/fact_vcd.png +0 -0
- data/tuto/hw_flow.odg +0 -0
- data/tuto/hw_flow.png +0 -0
- data/tuto/maxxer_vcd.png +0 -0
- data/tuto/pingpong0_vcd.png +0 -0
- data/tuto/pingpong1_vcd.png +0 -0
- data/tuto/pingpong2_vcd.png +0 -0
- data/tuto/ram_vcd.png +0 -0
- data/tuto/serializer_vcd.png +0 -0
- data/tuto/sw_flow.odg +0 -0
- data/tuto/sw_flow.png +0 -0
- data/tuto/the_counter_vcd.png +0 -0
- data/tuto/tutorial_sw.html +2359 -0
- data/tuto/tutorial_sw.md +2684 -0
- data/tuto/tutorial_sw.pdf +0 -0
- data/tuto/tutorial_sw_jp.md +417 -0
- metadata +49 -3
- data/lib/HDLRuby/hdr_samples/sumprod.rb +0 -29
@@ -0,0 +1,89 @@
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require 'std/sequencer.rb'
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include HDLRuby::High::Std
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# Checking the creation of sequencers enumerators.
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# - The first sequencer checks enumerators on signals.
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# - The second sequencer checks enumerators on ranges.
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# - The third sequencer checks enumerators on arrays.
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# - The fourth sequencer checks custom enumerators.
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system :my_seqencer do
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inner :clk,:rst
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bit[8][-8].inner vals: [ _h01, _h02, _h03, _h04, _h10, _h20, _h30, _h40 ]
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[8].inner :res0, :res1
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sequencer(clk.posedge,rst) do
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hprint("#0\n")
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res0 <= 0
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res1 <= 0
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res0 <= vals.ssum
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res1 <= res0.ssum(_h00)
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hprint("#1 res0=",res0," res1=",res1,"\n")
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end
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[8].inner :res2, :res3
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sequencer(clk.posedge,rst) do
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hprint("$0\n")
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res2 <= 0
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res3 <= 0
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res2 <= (1..5).sum
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res3 <= (res3..res2).ssum
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hprint("$1 res2=",res2," res3=",res3,"\n")
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end
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[8].inner :res4, :res5
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sequencer(clk.posedge,rst) do
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hprint("!0\n")
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res4 <= 0
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res5 <= 0
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res4 <= [_h01,_h02,_h03,_h04].ssum
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res5 <= [1,2,3,4,5].ssum
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hprint("!1 res4=",res4," res5=",res5,"\n")
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end
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bit[8][-8].inner mem: [ _h01, _h02, _h03, _h04, _h30, _h30, _h30, _h30 ]
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[8].inner :res6, :addr, :data
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data <= mem[addr]
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mem_enum = senumerator(bit[8],8) do |i|
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addr <= i
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step
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data
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end
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sequencer(clk.posedge,rst) do
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hprint("~0\n")
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res6 <= 0
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res6 <= mem_enum.ssum
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hprint("~1 res6=",res6,"\n")
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end
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timed do
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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repeat(100) do
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!10.ns
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clk <= ~clk
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end
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end
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end
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require 'std/sequencer_sync.rb'
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include HDLRuby::High::Std
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# Checking the usage of sequencers with synchronizarion.
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system :my_seqencer do
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inner :clk,:rst
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[8].inner :res0, :res1
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[8].shared(x0: _hFF,x1: _hFF)
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arbiter(:arbiter0).(x1)
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par(clk.posedge) do
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x0.select <= x0.select + 1
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end
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sequencer(clk.posedge,rst) do
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sloop do
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res0 <= x0 * 2
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res1 <= x1 * 2
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end
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end
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sequencer(clk.posedge,rst) do
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10.stimes do |i|
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x0 <= i
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x1 <= i
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arbiter0 <= 1
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end
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arbiter0 <= 0
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end
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sequencer(clk.posedge,rst) do
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10.stimes do |i|
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x0 <= 10-i
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x1 <= 10-i
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arbiter0 <= 1
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step
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end
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arbiter0 <= 0
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end
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sequencer(clk.posedge,rst) do
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10.stimes do |i|
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step
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arbiter0 <= 1
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x0 <= 128+i
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x1 <= 128+i
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step
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arbiter0 <= 0
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end
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end
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[8].inner :res2, :res20, :res21, :res22
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[8].shared x2: _hFF
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monitor(:monitor0).(x2)
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sequencer(clk.posedge,rst) do
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sloop do
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res2 <= x2 * 2
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end
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end
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sequencer(clk.posedge,rst) do
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x2 <= 0
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monitor0.lock
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4.stimes do |i|
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res20 <= res2
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x2 <= i + 1
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end
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res20 <= res2
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monitor0.unlock
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end
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sequencer(clk.posedge,rst) do
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5.stimes do |i|
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x2 <= 16 + i
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monitor0.lock
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res21 <= res2
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monitor0.unlock
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end
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end
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sequencer(clk.posedge,rst) do
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5.stimes do |i|
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x2 <= 32 + i
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monitor0.lock
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res22 <= res2
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step
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monitor0.unlock
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end
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end
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timed do
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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repeat(100) do
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!10.ns
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clk <= ~clk
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end
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end
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end
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val6 <= bs.reduce(:+)
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timed do
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val0 <=
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val0 <= _b1111000011110000
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count <= 0
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!10.ns
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val0 <=
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val0 <= _b0000111100001111
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count <= 1
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!10.ns
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val0 <=
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val0 <= _b1010101010101010
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count <= 2
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!10.ns
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end
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# A benchmark for testing the terminate statement.
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system :with_terminate do
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[8].constant cst0: 127
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constant cst1:
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[8].inner sig0:
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inner sig1:
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constant cst1: _b1
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[8].inner sig0: _b10000000
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inner sig1: _b1
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[8].inner :sig2
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[8].inner count: 0
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four2sixfour(:my_four2sixfour).(four,*(sixfour.to_a.reverse))
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timed do
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val <=
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val <= _b01101010
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res <= vals.reverse
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!10.ns
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val64 <=
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val64 <= _b0110101001101010011010100110101001101010011010100110101001101010
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res64 <= val64s.reverse
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!10.ns
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val <=
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val64 <=
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val <= _b00000000
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val64 <= _b0000000000000000000000000000000000000000000000000000000000000000
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!10.ns
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vals.each.with_index do |v,i|
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v <= (i/2) &
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v <= (i/2) & _b1
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end
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res <= val
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!10.ns
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val64s.each.with_index do |v,i|
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v <= (i/2) &
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v <= (i/2) & _b1
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end
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res64 <= val64
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!10.ns
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val <=
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val <= _b01010011
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!10.ns
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8.times do |i|
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val64s[i] <= val[i]
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end
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res64 <= val64
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!10.ns
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four <=
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four <= _b0000
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!10.ns
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four <=
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four <= _b0001
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!10.ns
|
87
|
-
four <=
|
87
|
+
four <= _b1100
|
88
88
|
!10.ns
|
89
89
|
end
|
90
90
|
end
|
@@ -11,7 +11,7 @@ system :with_values do
|
|
11
11
|
|
12
12
|
|
13
13
|
timed do
|
14
|
-
v1 <=
|
14
|
+
v1 <= _b0
|
15
15
|
v8 <= 0
|
16
16
|
v16 <= 0
|
17
17
|
v32 <= 0
|
@@ -19,7 +19,7 @@ system :with_values do
|
|
19
19
|
v64 <= 0
|
20
20
|
v96 <= 0
|
21
21
|
!10.ns
|
22
|
-
v1 <=
|
22
|
+
v1 <= _b1
|
23
23
|
v8 <= 1
|
24
24
|
v16 <= 1
|
25
25
|
v32 <= 1
|
@@ -27,7 +27,7 @@ system :with_values do
|
|
27
27
|
v64 <= 1
|
28
28
|
v96 <= 1
|
29
29
|
!10.ns
|
30
|
-
v1 <=
|
30
|
+
v1 <= _b1010[2]
|
31
31
|
v8 <= _uhFF00[12..4]
|
32
32
|
!10.ns
|
33
33
|
v8 <= 128
|
data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -60,6 +60,7 @@ require 'HDLRuby/hruby_check.rb'
|
|
60
60
|
require 'HDLRuby/hruby_low2hdr'
|
61
61
|
require 'HDLRuby/hruby_low2c'
|
62
62
|
require 'HDLRuby/hruby_low2vhd'
|
63
|
+
require 'HDLRuby/hruby_low_without_subsignals'
|
63
64
|
require 'HDLRuby/hruby_low_fix_types'
|
64
65
|
# require 'HDLRuby/hruby_low_expand_types' # For now dormant
|
65
66
|
require 'HDLRuby/hruby_low_without_outread'
|
@@ -262,6 +263,9 @@ module HDLRuby
|
|
262
263
|
# Initialize the environment for processing the hdr file.
|
263
264
|
bind = TOPLEVEL_BINDING.clone
|
264
265
|
eval("require 'HDLRuby'\n\nconfigure_high\n\n",bind)
|
266
|
+
if $options[:std] then
|
267
|
+
eval("require 'std/std.rb'\n\ninclude HDLRuby::High::Std\n\n",bind)
|
268
|
+
end
|
265
269
|
# Process it.
|
266
270
|
eval(@texts[0],bind,@top_file_name,1)
|
267
271
|
# Get the resulting instance
|
@@ -279,8 +283,8 @@ module HDLRuby
|
|
279
283
|
end
|
280
284
|
|
281
285
|
|
282
|
-
# Extend the Code class with generation of file for the content.
|
283
286
|
class HDLRuby::Low::Code
|
287
|
+
## Extends the Code class with generation of file for the content.
|
284
288
|
|
285
289
|
## Creates a file in +path+ containing the content of the code.
|
286
290
|
def to_file(path = "")
|
@@ -336,6 +340,9 @@ end
|
|
336
340
|
require 'optparse'
|
337
341
|
# Process the command line options
|
338
342
|
$options = {}
|
343
|
+
# By default the std libraries are loaded.
|
344
|
+
$options[:std] = true
|
345
|
+
# Parse the options
|
339
346
|
$optparse = OptionParser.new do |opts|
|
340
347
|
opts.banner = "Usage: hdrcc.rb [options] <input file> [<output directory or file>]"
|
341
348
|
|
@@ -434,6 +441,9 @@ $optparse = OptionParser.new do |opts|
|
|
434
441
|
opts.on("--testall","Compile all the available unit tests.") do |t|
|
435
442
|
$options[:testall] = t
|
436
443
|
end
|
444
|
+
opts.on("--no-std", "Compile without the standard library.") do |t|
|
445
|
+
$options[:std] = false
|
446
|
+
end
|
437
447
|
opts.on("-t", "--top system", "Specify the top system to process") do|t|
|
438
448
|
$options[:top] = t
|
439
449
|
end
|
@@ -444,7 +454,11 @@ $optparse = OptionParser.new do |opts|
|
|
444
454
|
$options[:dump] = v
|
445
455
|
$options[:multiple] = v
|
446
456
|
end
|
447
|
-
opts.on("--
|
457
|
+
opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one, the exit") do
|
458
|
+
FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples","./hdr_samples")
|
459
|
+
exit
|
460
|
+
end
|
461
|
+
opts.on("--version", "Show the version of HDLRuby, then exit") do |v|
|
448
462
|
puts VERSION
|
449
463
|
exit
|
450
464
|
end
|
@@ -641,8 +655,12 @@ elsif $options[:clang] then
|
|
641
655
|
# top_system = $top_system
|
642
656
|
# Preprocess the HW description for valid C generation.
|
643
657
|
$top_system.each_systemT_deep do |systemT|
|
658
|
+
HDLRuby.show? "signal2subs step..."
|
659
|
+
# Ensure there is not implicit assign to sub signals.
|
660
|
+
systemT.signal2subs!
|
661
|
+
HDLRuby.show? "#{Time.now}#{show_mem}"
|
644
662
|
HDLRuby.show? "seq2seq step..."
|
645
|
-
#
|
663
|
+
# Converts the par blocks in seq blocks to seq blocks to match
|
646
664
|
# the simulation engine.
|
647
665
|
systemT.par_in_seq2seq!
|
648
666
|
HDLRuby.show? "#{Time.now}#{show_mem}"
|
@@ -801,6 +819,9 @@ elsif $options[:verilog] then
|
|
801
819
|
# top_system = $top_system
|
802
820
|
# Make description compatible with verilog generation.
|
803
821
|
$top_system.each_systemT_deep do |systemT|
|
822
|
+
HDLRuby.show? "signal2subs step..."
|
823
|
+
# Ensure there is not implicit assign to sub signals.
|
824
|
+
systemT.signal2subs!
|
804
825
|
# HDLRuby.show "casts_without_expression! step..."
|
805
826
|
# systemT.casts_without_expression!
|
806
827
|
# HDLRuby.show Time.now
|
@@ -889,6 +910,8 @@ elsif $options[:rcsim] then
|
|
889
910
|
require 'HDLRuby/hruby_rcsim.rb'
|
890
911
|
# Merge the included from the top system.
|
891
912
|
$top_system.merge_included!
|
913
|
+
# Process par in seq.
|
914
|
+
$top_system.par_in_seq2seq!
|
892
915
|
# Generate the C data structures.
|
893
916
|
$top_system.to_rcsim
|
894
917
|
HDLRuby.show "Executing the hybrid C-Ruby-level simulator..."
|
@@ -902,6 +925,9 @@ elsif $options[:vhdl] then
|
|
902
925
|
# top_system = $top_system
|
903
926
|
# Make description compatible with vhdl generation.
|
904
927
|
$top_system.each_systemT_deep do |systemT|
|
928
|
+
HDLRuby.show? "signal2subs step..."
|
929
|
+
# Ensure there is not implicit assign to sub signals.
|
930
|
+
systemT.signal2subs!
|
905
931
|
systemT.outread2inner! unless $options[:vhdl08] || $options[:alliance]
|
906
932
|
systemT.with_boolean!
|
907
933
|
systemT.boolean_in_assign2select! unless $options[:alliance]
|
data/lib/HDLRuby/hdrlib.rb
CHANGED
@@ -226,8 +226,8 @@ module HDLRuby
|
|
226
226
|
end
|
227
227
|
|
228
228
|
|
229
|
-
# Extend the Code class with generation of file for the content.
|
230
229
|
class HDLRuby::Low::Code
|
230
|
+
## Extends the Code class with generation of file for the content.
|
231
231
|
|
232
232
|
## Creates a file in +path+ containing the content of the code.
|
233
233
|
def to_file(path = "")
|
data/lib/HDLRuby/hruby_bstr.rb
CHANGED
@@ -225,6 +225,7 @@ module HDLRuby
|
|
225
225
|
# * when index is larger than the bit width, the bit string is
|
226
226
|
# X extended accordingly.
|
227
227
|
def []=(index,value)
|
228
|
+
# puts "first @content=#{@content}"
|
228
229
|
# Change inside the bit string, it is not know any longer if it
|
229
230
|
# is specified or not
|
230
231
|
@specified = nil
|
@@ -250,8 +251,8 @@ module HDLRuby
|
|
250
251
|
sign = @content[-1]
|
251
252
|
@content.concat([sign] * (right-@content.size+1))
|
252
253
|
end
|
254
|
+
# puts "left=#{left} right=#{right} sign=#{sign} @content=#{@content}"
|
253
255
|
if right >= left then
|
254
|
-
# puts "left=#{left} right=#{right} value=#{value} (#{value.class})"
|
255
256
|
# Sets the value to a copy of the bit string.
|
256
257
|
@content[left..right] = value.is_a?(BitString) ?
|
257
258
|
value.raw_content[0..right-left] :
|
@@ -412,10 +413,14 @@ module HDLRuby
|
|
412
413
|
return @specified
|
413
414
|
end
|
414
415
|
|
415
|
-
#
|
416
|
-
|
417
|
-
|
418
|
-
|
416
|
+
# Coerces.
|
417
|
+
def coerce(other)
|
418
|
+
if other.is_a?(Numeric) && self.specified? then
|
419
|
+
return [other,self.to_i]
|
420
|
+
else
|
421
|
+
return [BitString.new(other),self]
|
422
|
+
end
|
423
|
+
end
|
419
424
|
|
420
425
|
# String conversion table.
|
421
426
|
B2S_T = [ "0", "1", "z", "x" ]
|
data/lib/HDLRuby/hruby_db.rb
CHANGED
@@ -9,7 +9,7 @@ warn "hruby_db.rb (former hruby_low.rb) is deprecated."
|
|
9
9
|
##
|
10
10
|
# Low-level libraries for describing digital hardware.
|
11
11
|
#######################################################
|
12
|
-
module HDLRuby::
|
12
|
+
module HDLRuby::LowDB
|
13
13
|
|
14
14
|
Base = HDLRuby::Base
|
15
15
|
|
@@ -151,7 +151,7 @@ module HDLRuby::Low
|
|
151
151
|
end
|
152
152
|
|
153
153
|
##
|
154
|
-
# Describes
|
154
|
+
# Describes an unsigned integer data type.
|
155
155
|
class TypeUnsigned < Base::TypeUnsigned
|
156
156
|
include Ltype
|
157
157
|
end
|