HDLRuby 2.11.11 → 3.0.0

data/lib/HDLRuby/hruby_rsim.rb

@@ -12,13 +12,17 @@ module HDLRuby::High
 #
 ########################################################################
 
-    ##
-    # Enhance a system type with Ruby simulation.
+
+
     class SystemT
+        ## Enhance a system type with Ruby simulation.
 
         # Tell if the simulation is in multithread mode or not.
         attr_reader :multithread
 
+        # The current global time.
+        attr_reader :time
+
         ## Add untimed objet +obj+
         def add_untimed(obj)
             @untimeds << obj
@@ -66,7 +70,7 @@ module HDLRuby::High
                 @sig_active.each do |sig|
                     next if (sig.c_value.eql?(sig.f_value))
                     # next if (sig.c_value.to_vstr == sig.f_value.to_vstr)
-                    # puts "sig.c_value: #{sig.c_value.to_vstr}, sig.f_value=#{sig.f_value.to_vstr}"
+                    # puts "for sig=#{sig.fullname}"
                     sig.each_anyedge { |beh| @sig_exec << beh }
                     if (sig.c_value.zero?) then
                         # puts "sig.c_value=#{sig.c_value.content}"
@@ -79,6 +83,7 @@ module HDLRuby::High
                 @sig_active.each { |sig| sig.c_value = sig.f_value }
                 # puts "first @sig_exec.size=#{@sig_exec.size}"
                 @sig_exec.uniq! {|beh| beh.object_id }
+                # puts "now @sig_exec.size=#{@sig_exec.size}"
                 # Display the activated signals.
                 @sig_active.each do |sig|
                     if !shown_values[sig].eql?(sig.f_value) then
@@ -94,9 +99,10 @@ module HDLRuby::High
                 @sig_exec.clear
                 @sig_active.uniq! {|sig| sig.object_id }
                 # puts "@sig_active.size=#{@sig_active.size}"
-                # Advance time.
+                # Compute the nearest next time stamp.
                 @time = (@timed_behaviors.min {|b0,b1|  b0.time <=> b1.time }).time
             end
+            # puts "@time=#{@time}"
             # Display the time
             self.show_time
         end
@@ -108,6 +114,8 @@ module HDLRuby::High
             HDLRuby.show "#{Time.now}#{show_mem}"
             # Merge the included.
             self.merge_included!
+            # Process par in seq.
+            self.par_in_seq2seq!
             # Initializes the time.
             @time = 0
             # Initializes the time and signals execution buffers.
@@ -131,6 +139,9 @@ module HDLRuby::High
             self.init_untimeds
             # puts "End of init_untimed."
 
+            # Maybe there is nothing to execute.
+            return if @total_timed_behaviors == 0
+
             # Is there more than one timed behavior.
             if @total_timed_behaviors <= 1 then
                 # No, no need of multithreading.
@@ -318,9 +329,8 @@ module HDLRuby::High
     end
 
 
-    ## 
-    # Describes scopes of system types.
     class Scope
+        ## Enhance a scope with Ruby simulation.
         
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
@@ -331,7 +341,26 @@ module HDLRuby::High
             # Recurse on the systemI.
             self.each_systemI { |sys| sys.init_sim(systemT) }
             # Recurse on the connections.
-            self.each_connection { |cnx| cnx.init_sim(systemT) }
+            # self.each_connection { |cnx| cnx.init_sim(systemT) }
+            self.each_connection do |cnx|
+                # Connection to a real expression?
+                if !cnx.right.is_a?(RefObject) then
+                    # Yes.
+                    cnx.init_sim(systemT)
+                else
+                    # No, maybe the reverse connection is also required.
+                    # puts "cnx.left.object=#{cnx.left.object.fullname} cnx.right.object=#{cnx.right.object.fullname}"
+                    cnx.init_sim(systemT)
+                    if cnx.left.is_a?(RefObject) then
+                        sigL = cnx.left.object
+                        prtL = sigL.parent
+                        if prtL.is_a?(SystemT) and prtL.each_inout.any?{|e| e.object_id == sigL.object_id} then
+                            # puts "write to right with sigL=#{sigL.fullname}."
+                            Connection.new(cnx.right.clone,cnx.left.clone).init_sim(systemT)
+                        end
+                    end
+                end
+            end
             # Recurse on the sub scopes.
             self.each_scope { |sco| sco.init_sim(systemT) }
         end
@@ -389,9 +418,21 @@ module HDLRuby::High
                 # Keep only one ref per signal.
                 refs.uniq! { |node| node.fullname }
                 # puts "refs=#{refs.map {|node| node.fullname}}"
+                # The get the left references: the will be removed from the
+                # events.
+                left_refs = self.block.each_node_deep.select do |node|
+                    node.is_a?(RefObject) && node.leftvalue? && 
+                        !node.parent.is_a?(RefObject) 
+                end.to_a
+                # Keep only one left ref per signal.
+                left_refs.uniq! { |node| node.fullname }
                 # Remove the inner signals from the list.
                 self.block.each_inner do |inner|
-                    refs.delete_if {|r| r.name == inner.name }
+                    refs.delete_if {|r| r.fullname == inner.fullname }
+                end
+                # Remove the left refs.
+                left_refs.each do |l| 
+                    refs.delete_if {|r| r.fullname == l.fullname }
                 end
                 # Generate the event.
                 events = refs.map {|ref| Event.new(:anyedge,ref.clone) }
@@ -490,6 +531,15 @@ module HDLRuby::High
 
         ## Initialize the simulation for +systemT+
         def init_sim(systemT)
+            # Initialize the local time to -1
+            @time = -1
+            @sim = systemT
+            # Recurse on the sub signals if any.
+            if self.each_signal.any? then
+                self.each_signal {|sig| sig.init_sim(systemT) }
+                return
+            end
+            # No sub signal, really initialize the current signal.
             if self.value then
                 @c_value = self.value.execute(:par).to_value
                 @f_value = @c_value.to_value
@@ -506,18 +556,27 @@ module HDLRuby::High
 
         ## Adds behavior +beh+ activated on a positive edge of the signal.
         def add_posedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_posedge(beh) }
+            # Apply on current signal.
             @posedge_behaviors ||= []
             @posedge_behaviors << beh
         end
 
         ## Adds behavior +beh+ activated on a negative edge of the signal.
         def add_negedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_negedge(beh) }
+            # Apply on current signal.
             @negedge_behaviors ||= []
             @negedge_behaviors << beh
         end
 
         ## Adds behavior +beh+ activated on a any edge of the signal.
         def add_anyedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_anyedge(beh) }
+            # Apply on current signal.
             @anyedge_behaviors ||= []
             @anyedge_behaviors << beh
         end
@@ -543,19 +602,23 @@ module HDLRuby::High
 
         ## Execute the expression.
         def execute(mode)
-            # puts "Executing signal=#{self.fullname}"
-            # return mode == :par ? self.c_value : self.f_value
+            # puts "Executing signal=#{self.fullname} in mode=#{mode}  with c_value=#{self.c_value} and f_value=#{self.f_value}"
             return @mode == :seq ? self.f_value : self.c_value
+            # return @mode == :seq || mode == :seq ? self.f_value : self.c_value
         end
 
         ## Assigns +value+ the the reference.
         def assign(mode,value)
-            # Set the next value.
-            @f_value = value
+            # # Set the next value.
+            # @f_value = value
             # Set the mode.
             @mode = mode
-            # puts "assign #{value.content} (#{value.content.class}) with self.type.width=#{self.type.width} while value.type.width=#{value.type.width}" if self.name.to_s.include?("xnor")
-            @f_value = value.cast(self.type) # Cast not always inserted by HDLRuby normally
+            # @f_value = value.cast(self.type) # Cast not always inserted by HDLRuby normally
+            if @sim.time > @time or !value.impedence? then
+                # puts "assign #{value.content} to #{self.fullname}"
+                @f_value = value.cast(self.type) # Cast not always inserted by HDLRuby normally
+                @time = @sim.time
+            end
         end
 
         ## Assigns +value+ at +index+ (integer or range).
@@ -649,10 +712,12 @@ module HDLRuby::High
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
             self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
         end
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute Transmit in mode=#{mode} for left=#{self.left.object.fullname}" if left.is_a?(RefObject)
             self.left.assign(mode,self.right.execute(mode))
         end
     end
@@ -664,12 +729,17 @@ module HDLRuby::High
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
             self.yes.init_sim(systemT)
-            self.each_noif { |cond,stmnt| stmnt.init_sim(systemT) } 
+            # self.each_noif { |cond,stmnt| stmnt.init_sim(systemT) } 
+            self.each_noif do |cond,stmnt| 
+                cond.init_sim(systemT)
+                stmnt.init_sim(systemT)
+            end
             self.no.init_sim(systemT) if self.no
         end
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute hif with mode=#{mode}"
             # Check the main condition.
             if !(self.condition.execute(mode).zero?) then
                 self.yes.execute(mode)
@@ -848,6 +918,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute block of mode=#{self.mode}"
             self.each_statement { |stmnt| stmnt.execute(self.mode) }
         end
 
@@ -858,6 +929,27 @@ module HDLRuby::High
         end
     end
 
+    class If
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
+    class When
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
+    class Case
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
     # Describes a timed block.
     #
     # NOTE: 
@@ -889,8 +981,9 @@ module HDLRuby::High
         def init_sim(systemT)
             # Add the connection to the list of untimed objets.
             systemT.add_untimed(self)
-            # Recurse on the left.
+            # Recurse on the left and right.
             self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
             # Process the sensitivity list.
             # Is it a clocked behavior?
             events = []
@@ -914,8 +1007,9 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
-            # puts "connection = #{self}" if self.left.is_a?(RefObject) && self.left.object.name.to_s.include?("xnor")
-            self.left.assign(mode,self.right.execute(mode))
+            # puts "connection left=#{left.object.fullname}"
+            # self.left.assign(mode,self.right.execute(mode))
+            self.left.assign(:seq,self.right.execute(mode))
         end
     end
 
@@ -926,6 +1020,11 @@ module HDLRuby::High
     #
     # NOTE: this is an abstract class which is not to be used directly.
     class Expression
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # By default: do nothing.
+        end
+
         ## Executes the expression in +mode+ (:blocking or :nonblocking)
         #  NOTE: to be overrided.
         def execute(mode)
@@ -937,6 +1036,11 @@ module HDLRuby::High
     ##
     # Describes a value.
     class Value
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Nothing to do.
+        end
+
         # include Vprocess
 
         ## Executes the expression.
@@ -949,10 +1053,16 @@ module HDLRuby::High
     ##
     # Describes a cast.
     class Cast
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the child.
+            self.child.init_sim(systemT)
+        end
+
         ## Executes the expression.
         def execute(mode)
-            # Recurse on the child.
-            # res = tocast.execute(mode)
+            # puts "child=#{self.child}"
+            # puts "child object=#{self.child.object}(#{self.child.object.name})" if self.child.is_a?(RefObject)
             # Shall we reverse the content of a concat.
             if self.child.is_a?(Concat) && 
                     self.type.direction != self.child.type.direction then
@@ -961,6 +1071,7 @@ module HDLRuby::High
             else
                 res = self.child.execute(mode)
             end
+            # puts "res=#{res}"
             # Cast it.
             res = res.cast(self.type,true)
             # Returns the result.
@@ -981,6 +1092,12 @@ module HDLRuby::High
     ## 
     # Describes an unary operation.
     class Unary
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the child.
+            self.child.init_sim(systemT)
+        end
+
         ## Execute the expression.
         def execute(mode)
             # puts "Unary with operator=#{self.operator}"
@@ -996,6 +1113,13 @@ module HDLRuby::High
     ##
     # Describes an binary operation.
     class Binary
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
+        end
+
         ## Execute the expression.
         def execute(mode)
             # Recurse on the children.
@@ -1012,6 +1136,13 @@ module HDLRuby::High
     #
     # NOTE: choice is using the value of +select+ as an index.
     class Select
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.select.init_sim(systemT)
+            self.each_choice { |choice| choice.init_sim(systemT) }
+        end
+
         ## Execute the expression.
         def execute(mode)
             unless @mask then
@@ -1033,6 +1164,12 @@ module HDLRuby::High
     ## 
     # Describes a concatenation expression.
     class Concat
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.each_expression { |expr| expr.init_sim(systemT) }
+        end
+
         ## Execute the expression.
         def execute(mode, reverse=false)
             # Recurse on the children.
@@ -1218,7 +1355,44 @@ module HDLRuby::High
     class RefObject
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
+            # puts "init_sim for RefObject=#{self}"
             @sim = systemT
+
+            # Modify the exectute and assign methods if the object has
+            # sub signals (for faster execution).
+            if self.object.each_signal.any? then
+                ## Execute the expression.
+                self.define_singleton_method(:execute) do |mode|
+                    # Recurse on the children.
+                    iter = self.object.each_signal
+                    iter = iter.reverse_each unless self.object.type.direction == :big
+                    tmpe = iter.map {|sig| sig.execute(mode) }
+                    # Concatenate the result.
+                    # return tmpe.reduce(:concat)
+                    return Vprocess.concat(*tmpe)
+                end
+                ## Assigns +value+ the the reference.
+                self.define_singleton_method(:assign) do |mode,value|
+                    # puts "RefObject #{self} assign with object=#{self.object}"
+                    # Flatten the value type.
+                    value.type = [value.type.width].to_type
+                    pos = 0
+                    width = 0
+                    # Recurse on the children.
+                    iter = self.object.each_signal
+                    iter = iter.reverse_each unless self.object.type.direction == :big
+                    iter.each do |sig|
+                        width = sig.type.width
+                        sig.assign(mode,value[(pos+width-1).to_expr..pos.to_expr])
+                        # Tell the signal changed.
+                        if !(sig.c_value.eql?(sig.f_value)) then
+                            @sim.add_sig_active(sig)
+                        end
+                        # Prepare for the next reference.
+                        pos += width
+                    end
+                end
+            end
         end
 
         ## Execute the expression.

data/lib/HDLRuby/hruby_rsim_mute.rb

@@ -1,14 +1,13 @@
 require "HDLRuby/hruby_rsim"
 
 ##
-# Library for enhancing the Ruby simulator with VCD support
+# Library for enhancing the Ruby simulator with muted output support
 #
 ########################################################################
 module HDLRuby::High
 
-    ##
-    # Enhance the system type class with VCD support.
     class SystemT
+        # Enhance the system type class with mute support.
 
         ## Initializes the displayer for generating a vcd on +vcdout+
         def show_init(vcdout)