HDLRuby 2.11.11 → 3.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.html +3274 -0
- data/README.md +608 -99
- data/ext/hruby_sim/hruby_rcsim_build.c +27 -0
- data/ext/hruby_sim/hruby_sim.h +3 -0
- data/ext/hruby_sim/hruby_sim_calc.c +2 -0
- data/ext/hruby_sim/hruby_sim_core.c +17 -5
- data/ext/hruby_sim/hruby_sim_stack_calc.c +1 -1
- data/ext/hruby_sim/hruby_sim_tree_calc.c +8 -1
- data/ext/hruby_sim/hruby_sim_vcd.c +24 -7
- data/ext/hruby_sim/hruby_sim_vizualize.c +9 -1
- data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
- data/lib/HDLRuby/hdr_samples/constant_in_function.rb +3 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +3 -1
- data/lib/HDLRuby/hdr_samples/huge_rom.rb +1 -1
- data/lib/HDLRuby/hdr_samples/mei8.rb +11 -11
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +12 -12
- data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +4 -4
- data/lib/HDLRuby/hdr_samples/rom_nest.rb +1 -1
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +4 -4
- data/lib/HDLRuby/hdr_samples/struct.rb +44 -10
- data/lib/HDLRuby/hdr_samples/with_bram.rb +45 -0
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_casts.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_concat.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -2
- data/lib/HDLRuby/hdr_samples/with_def.rb +10 -3
- data/lib/HDLRuby/hdr_samples/with_define_operator.rb +44 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -12
- data/lib/HDLRuby/hdr_samples/with_init.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_leftright.rb +21 -0
- data/lib/HDLRuby/hdr_samples/with_reduce.rb +13 -13
- data/lib/HDLRuby/hdr_samples/with_ref_array.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
- data/lib/HDLRuby/hdr_samples/with_subsums.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_terminate.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_to_a.rb +10 -10
- data/lib/HDLRuby/hdr_samples/with_values.rb +3 -3
- data/lib/HDLRuby/hdrcc.rb +29 -3
- data/lib/HDLRuby/hdrlib.rb +1 -1
- data/lib/HDLRuby/hruby_bstr.rb +10 -5
- data/lib/HDLRuby/hruby_db.rb +2 -2
- data/lib/HDLRuby/hruby_high.rb +152 -47
- data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +189 -18
- data/lib/HDLRuby/hruby_low2c.rb +129 -54
- data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
- data/lib/HDLRuby/hruby_low2high.rb +86 -44
- data/lib/HDLRuby/hruby_low2seq.rb +26 -18
- data/lib/HDLRuby/hruby_low2sym.rb +14 -13
- data/lib/HDLRuby/hruby_low2vhd.rb +80 -44
- data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
- data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
- data/lib/HDLRuby/hruby_low_fix_types.rb +65 -32
- data/lib/HDLRuby/hruby_low_mutable.rb +83 -119
- data/lib/HDLRuby/hruby_low_resolve.rb +38 -30
- data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
- data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
- data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
- data/lib/HDLRuby/hruby_low_without_concat.rb +45 -19
- data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +32 -16
- data/lib/HDLRuby/hruby_low_without_select.rb +37 -24
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +280 -0
- data/lib/HDLRuby/hruby_rcsim.rb +158 -134
- data/lib/HDLRuby/hruby_rsim.rb +194 -20
- data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
- data/lib/HDLRuby/hruby_rsim_vcd.rb +125 -50
- data/lib/HDLRuby/hruby_values.rb +48 -33
- data/lib/HDLRuby/hruby_verilog.rb +90 -48
- data/lib/HDLRuby/soft/stacks.rb +219 -0
- data/lib/HDLRuby/std/bram.rb +26 -0
- data/lib/HDLRuby/std/clocks.rb +1 -1
- data/lib/HDLRuby/std/fixpoint.rb +2 -2
- data/lib/HDLRuby/std/fsm.rb +48 -11
- data/lib/HDLRuby/std/function_generator.rb +2 -2
- data/lib/HDLRuby/std/sequencer.rb +1857 -0
- data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
- data/lib/HDLRuby/std/std.rb +12 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/tuto/adder_sat_flags_vcd.png +0 -0
- data/tuto/addsub_vcd.png +0 -0
- data/tuto/alu_vcd.png +0 -0
- data/tuto/bit_pong_vcd.png +0 -0
- data/tuto/checksum_vcd.png +0 -0
- data/tuto/circuit_hdr.odg +0 -0
- data/tuto/circuit_hdr.png +0 -0
- data/tuto/circuit_hie.odg +0 -0
- data/tuto/circuit_hie.png +0 -0
- data/tuto/circuit_view.odg +0 -0
- data/tuto/circuit_view.png +0 -0
- data/tuto/clock_counter_vcd.png +0 -0
- data/tuto/counter_ext_vcd.png +0 -0
- data/tuto/fact_vcd.png +0 -0
- data/tuto/hw_flow.odg +0 -0
- data/tuto/hw_flow.png +0 -0
- data/tuto/maxxer_vcd.png +0 -0
- data/tuto/pingpong0_vcd.png +0 -0
- data/tuto/pingpong1_vcd.png +0 -0
- data/tuto/pingpong2_vcd.png +0 -0
- data/tuto/ram_vcd.png +0 -0
- data/tuto/serializer_vcd.png +0 -0
- data/tuto/sw_flow.odg +0 -0
- data/tuto/sw_flow.png +0 -0
- data/tuto/the_counter_vcd.png +0 -0
- data/tuto/tutorial_sw.html +2359 -0
- data/tuto/tutorial_sw.md +2684 -0
- data/tuto/tutorial_sw.pdf +0 -0
- data/tuto/tutorial_sw_jp.md +417 -0
- metadata +49 -3
- data/lib/HDLRuby/hdr_samples/sumprod.rb +0 -29
data/lib/HDLRuby/std/fsm.rb
CHANGED
@@ -31,14 +31,18 @@ module HDLRuby::High::Std
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# Creates a new fsm type with +name+.
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# +options+ allows to specify the type of fsm:
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-
# synchronous (default)
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#
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+
# - :sync, :synchronous : synchronous (default)
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# - :async, :asynchronous : asynchronous
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# - :dual : dual front
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# - :seq, :blocking : use blocking assignments
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def initialize(name,*options)
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# Check and set the name
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@name = name.to_sym
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# Check and set the type of fsm depending of the options.
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@dual = false
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@type = :sync
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@type = :sync # By default, the FSM is synchronous.
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@sequential = true # By default, the default next state is the next one in the list.
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@blocking = false # By default, use non-blocking assignments (par)
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options.each do |opt|
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case opt
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when :sync,:synchronous then
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@@ -47,10 +51,25 @@ module HDLRuby::High::Std
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@type = :async
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when :dual then
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@dual = true
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when :static then
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@sequential = false
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when :seq then
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@blocking = true
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when :blocking then
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@blocking = true
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else
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raise AnyError, "Invalid option for a fsm: :#{type}"
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end
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end
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if @blocking then
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define_singleton_method(:fsm_block) do |*args,&ruby_block|
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send(:seq,*args,&ruby_block)
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end
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else
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define_singleton_method(:fsm_block) do |*args,&ruby_block|
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send(:par,*args,&ruby_block)
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end
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end
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# Initialize the internals of the FSM.
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@@ -112,6 +131,7 @@ module HDLRuby::High::Std
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mk_rst = @mk_rst
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type = @type
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dual = @dual
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sequential = @sequential
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extra_syncs = @extra_syncs
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extra_asyncs = @extra_asyncs
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default_codes = @default_codes
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@@ -123,7 +143,8 @@ module HDLRuby::High::Std
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# sub do
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HDLRuby::High.space_push(namespace)
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# Execute the instantiation block
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return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
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# return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
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return_value = HDLRuby::High.top_user.instance_exec(&ruby_block) if ruby_block
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# Expands the extra state processing so that al all the
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# parts of the state machine are in par (clear synthesis).
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# Create the fsm code
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# Control part: update of the state.
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par(mk_ev.call) do
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# par(mk_ev.call) do
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fsm_block(mk_ev.call) do
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hif(mk_rst.call) do
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# Reset: current state is to put to 0.
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this.cur_state_sig <= 0
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@@ -190,7 +212,8 @@ module HDLRuby::High::Std
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event = []
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end
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# The process
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par(*event) do
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# par(*event) do
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fsm_block(*event) do
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# The operative code.
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oper_code = proc do
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# The default code.
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st.gotos.each(&:call)
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else
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# No gotos, by default the next step is
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-
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-
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-
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if sequential then
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this.next_state_sig <= this.cur_state_sig + 1
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end
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end
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end
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end
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# By default set the next state to 0.
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helse do
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# hprint("Unknow state case: ",this.cur_state_sig,"\n")
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this.next_state_sig <= 0
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end
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@@ -254,7 +278,8 @@ module HDLRuby::High::Std
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event = mk_ev.call
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event = event.invert if @dual
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# The extra code.
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par(*event) do
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# par(*event) do
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fsm_block(*event) do
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# Build the extra synchronous part.
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sync_code = proc do
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hcase(this.cur_state_sig)
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# Extra asynchronous operative part.
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if extra_asyncs.any? then
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par do
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# par do
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fsm_block do
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# Build the extra synchronous part.
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async_code = proc do
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hcase(this.cur_state_sig)
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@@ -406,6 +432,17 @@ module HDLRuby::High::Std
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return result
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end
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# Get a state by +name+.
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def get_state(name)
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name = name.to_sym
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(@states.detect { |st| st.name == name }).value
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end
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# Sets the next state by +name+.
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def next_state(name)
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@next_state_sig <= get_state(name)
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end
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# Sets the next state. Arguments can be:
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#
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# +name+: the name of the next state.
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@@ -75,7 +75,7 @@ module HDLRuby::High::Std
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base <= lut[address]
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# Assign the next_data discrete value.
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next_data <= lut[address+
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next_data <= lut[address+_b1.as(address.type)]
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end
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@@ -107,7 +107,7 @@ module HDLRuby::High::Std
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end
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# Make the interpolation.
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seq do
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diff <= (next_data-base).as(diff.type) * remaining
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if(otyp.signed?) then
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interpolated_value <= base +
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