HDLRuby 2.11.11 → 3.0.0

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Files changed (119) hide show
  1. checksums.yaml +4 -4
  2. data/README.html +3274 -0
  3. data/README.md +608 -99
  4. data/ext/hruby_sim/hruby_rcsim_build.c +27 -0
  5. data/ext/hruby_sim/hruby_sim.h +3 -0
  6. data/ext/hruby_sim/hruby_sim_calc.c +2 -0
  7. data/ext/hruby_sim/hruby_sim_core.c +17 -5
  8. data/ext/hruby_sim/hruby_sim_stack_calc.c +1 -1
  9. data/ext/hruby_sim/hruby_sim_tree_calc.c +8 -1
  10. data/ext/hruby_sim/hruby_sim_vcd.c +24 -7
  11. data/ext/hruby_sim/hruby_sim_vizualize.c +9 -1
  12. data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
  13. data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
  14. data/lib/HDLRuby/hdr_samples/constant_in_function.rb +3 -1
  15. data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +3 -1
  16. data/lib/HDLRuby/hdr_samples/huge_rom.rb +1 -1
  17. data/lib/HDLRuby/hdr_samples/mei8.rb +11 -11
  18. data/lib/HDLRuby/hdr_samples/mei8_bench.rb +12 -12
  19. data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +4 -4
  20. data/lib/HDLRuby/hdr_samples/rom_nest.rb +1 -1
  21. data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +4 -4
  22. data/lib/HDLRuby/hdr_samples/struct.rb +44 -10
  23. data/lib/HDLRuby/hdr_samples/with_bram.rb +45 -0
  24. data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
  25. data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
  26. data/lib/HDLRuby/hdr_samples/with_casts.rb +3 -3
  27. data/lib/HDLRuby/hdr_samples/with_concat.rb +6 -6
  28. data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -2
  29. data/lib/HDLRuby/hdr_samples/with_def.rb +10 -3
  30. data/lib/HDLRuby/hdr_samples/with_define_operator.rb +44 -0
  31. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -12
  32. data/lib/HDLRuby/hdr_samples/with_init.rb +3 -3
  33. data/lib/HDLRuby/hdr_samples/with_leftright.rb +21 -0
  34. data/lib/HDLRuby/hdr_samples/with_reduce.rb +13 -13
  35. data/lib/HDLRuby/hdr_samples/with_ref_array.rb +6 -6
  36. data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
  37. data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
  38. data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
  39. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
  40. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
  41. data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
  42. data/lib/HDLRuby/hdr_samples/with_subsums.rb +3 -3
  43. data/lib/HDLRuby/hdr_samples/with_terminate.rb +3 -3
  44. data/lib/HDLRuby/hdr_samples/with_to_a.rb +10 -10
  45. data/lib/HDLRuby/hdr_samples/with_values.rb +3 -3
  46. data/lib/HDLRuby/hdrcc.rb +29 -3
  47. data/lib/HDLRuby/hdrlib.rb +1 -1
  48. data/lib/HDLRuby/hruby_bstr.rb +10 -5
  49. data/lib/HDLRuby/hruby_db.rb +2 -2
  50. data/lib/HDLRuby/hruby_high.rb +152 -47
  51. data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
  52. data/lib/HDLRuby/hruby_low.rb +189 -18
  53. data/lib/HDLRuby/hruby_low2c.rb +129 -54
  54. data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
  55. data/lib/HDLRuby/hruby_low2high.rb +86 -44
  56. data/lib/HDLRuby/hruby_low2seq.rb +26 -18
  57. data/lib/HDLRuby/hruby_low2sym.rb +14 -13
  58. data/lib/HDLRuby/hruby_low2vhd.rb +80 -44
  59. data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
  60. data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
  61. data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
  62. data/lib/HDLRuby/hruby_low_fix_types.rb +65 -32
  63. data/lib/HDLRuby/hruby_low_mutable.rb +83 -119
  64. data/lib/HDLRuby/hruby_low_resolve.rb +38 -30
  65. data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
  66. data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
  67. data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
  68. data/lib/HDLRuby/hruby_low_without_concat.rb +45 -19
  69. data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
  70. data/lib/HDLRuby/hruby_low_without_parinseq.rb +32 -16
  71. data/lib/HDLRuby/hruby_low_without_select.rb +37 -24
  72. data/lib/HDLRuby/hruby_low_without_subsignals.rb +280 -0
  73. data/lib/HDLRuby/hruby_rcsim.rb +158 -134
  74. data/lib/HDLRuby/hruby_rsim.rb +194 -20
  75. data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
  76. data/lib/HDLRuby/hruby_rsim_vcd.rb +125 -50
  77. data/lib/HDLRuby/hruby_values.rb +48 -33
  78. data/lib/HDLRuby/hruby_verilog.rb +90 -48
  79. data/lib/HDLRuby/soft/stacks.rb +219 -0
  80. data/lib/HDLRuby/std/bram.rb +26 -0
  81. data/lib/HDLRuby/std/clocks.rb +1 -1
  82. data/lib/HDLRuby/std/fixpoint.rb +2 -2
  83. data/lib/HDLRuby/std/fsm.rb +48 -11
  84. data/lib/HDLRuby/std/function_generator.rb +2 -2
  85. data/lib/HDLRuby/std/sequencer.rb +1857 -0
  86. data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
  87. data/lib/HDLRuby/std/std.rb +12 -0
  88. data/lib/HDLRuby/version.rb +1 -1
  89. data/tuto/adder_sat_flags_vcd.png +0 -0
  90. data/tuto/addsub_vcd.png +0 -0
  91. data/tuto/alu_vcd.png +0 -0
  92. data/tuto/bit_pong_vcd.png +0 -0
  93. data/tuto/checksum_vcd.png +0 -0
  94. data/tuto/circuit_hdr.odg +0 -0
  95. data/tuto/circuit_hdr.png +0 -0
  96. data/tuto/circuit_hie.odg +0 -0
  97. data/tuto/circuit_hie.png +0 -0
  98. data/tuto/circuit_view.odg +0 -0
  99. data/tuto/circuit_view.png +0 -0
  100. data/tuto/clock_counter_vcd.png +0 -0
  101. data/tuto/counter_ext_vcd.png +0 -0
  102. data/tuto/fact_vcd.png +0 -0
  103. data/tuto/hw_flow.odg +0 -0
  104. data/tuto/hw_flow.png +0 -0
  105. data/tuto/maxxer_vcd.png +0 -0
  106. data/tuto/pingpong0_vcd.png +0 -0
  107. data/tuto/pingpong1_vcd.png +0 -0
  108. data/tuto/pingpong2_vcd.png +0 -0
  109. data/tuto/ram_vcd.png +0 -0
  110. data/tuto/serializer_vcd.png +0 -0
  111. data/tuto/sw_flow.odg +0 -0
  112. data/tuto/sw_flow.png +0 -0
  113. data/tuto/the_counter_vcd.png +0 -0
  114. data/tuto/tutorial_sw.html +2359 -0
  115. data/tuto/tutorial_sw.md +2684 -0
  116. data/tuto/tutorial_sw.pdf +0 -0
  117. data/tuto/tutorial_sw_jp.md +417 -0
  118. metadata +49 -3
  119. data/lib/HDLRuby/hdr_samples/sumprod.rb +0 -29
@@ -31,14 +31,18 @@ module HDLRuby::High::Std
31
31
 
32
32
  # Creates a new fsm type with +name+.
33
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  # +options+ allows to specify the type of fsm:
34
- # synchronous (default) / asynchronous and
35
- # mono-front(default) / dual front
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+ # - :sync, :synchronous : synchronous (default)
35
+ # - :async, :asynchronous : asynchronous
36
+ # - :dual : dual front
37
+ # - :seq, :blocking : use blocking assignments
36
38
  def initialize(name,*options)
37
39
  # Check and set the name
38
40
  @name = name.to_sym
39
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  # Check and set the type of fsm depending of the options.
40
42
  @dual = false
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- @type = :sync
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+ @type = :sync # By default, the FSM is synchronous.
44
+ @sequential = true # By default, the default next state is the next one in the list.
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+ @blocking = false # By default, use non-blocking assignments (par)
42
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  options.each do |opt|
43
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  case opt
44
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  when :sync,:synchronous then
@@ -47,10 +51,25 @@ module HDLRuby::High::Std
47
51
  @type = :async
48
52
  when :dual then
49
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  @dual = true
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+ when :static then
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+ @sequential = false
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+ when :seq then
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+ @blocking = true
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+ when :blocking then
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+ @blocking = true
50
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  else
51
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  raise AnyError, "Invalid option for a fsm: :#{type}"
52
62
  end
53
63
  end
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+ if @blocking then
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+ define_singleton_method(:fsm_block) do |*args,&ruby_block|
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+ send(:seq,*args,&ruby_block)
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+ end
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+ else
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+ define_singleton_method(:fsm_block) do |*args,&ruby_block|
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+ send(:par,*args,&ruby_block)
71
+ end
72
+ end
54
73
 
55
74
  # Initialize the internals of the FSM.
56
75
 
@@ -112,6 +131,7 @@ module HDLRuby::High::Std
112
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  mk_rst = @mk_rst
113
132
  type = @type
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133
  dual = @dual
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+ sequential = @sequential
115
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  extra_syncs = @extra_syncs
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136
  extra_asyncs = @extra_asyncs
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137
  default_codes = @default_codes
@@ -123,7 +143,8 @@ module HDLRuby::High::Std
123
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  # sub do
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  HDLRuby::High.space_push(namespace)
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  # Execute the instantiation block
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- return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
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+ # return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
147
+ return_value = HDLRuby::High.top_user.instance_exec(&ruby_block) if ruby_block
127
148
 
128
149
  # Expands the extra state processing so that al all the
129
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  # parts of the state machine are in par (clear synthesis).
@@ -167,7 +188,8 @@ module HDLRuby::High::Std
167
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  # Create the fsm code
168
189
 
169
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  # Control part: update of the state.
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- par(mk_ev.call) do
191
+ # par(mk_ev.call) do
192
+ fsm_block(mk_ev.call) do
171
193
  hif(mk_rst.call) do
172
194
  # Reset: current state is to put to 0.
173
195
  this.cur_state_sig <= 0
@@ -190,7 +212,8 @@ module HDLRuby::High::Std
190
212
  event = []
191
213
  end
192
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  # The process
193
- par(*event) do
215
+ # par(*event) do
216
+ fsm_block(*event) do
194
217
  # The operative code.
195
218
  oper_code = proc do
196
219
  # The default code.
@@ -237,14 +260,15 @@ module HDLRuby::High::Std
237
260
  st.gotos.each(&:call)
238
261
  else
239
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  # No gotos, by default the next step is
240
- # current + 1
241
- # this.next_state_sig <= mux(mk_rst.call , 0, this.cur_state_sig + 1)
242
- this.next_state_sig <= this.cur_state_sig + 1
263
+ if sequential then
264
+ this.next_state_sig <= this.cur_state_sig + 1
265
+ end
243
266
  end
244
267
  end
245
268
  end
246
269
  # By default set the next state to 0.
247
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  helse do
271
+ # hprint("Unknow state case: ",this.cur_state_sig,"\n")
248
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  this.next_state_sig <= 0
249
273
  end
250
274
 
@@ -254,7 +278,8 @@ module HDLRuby::High::Std
254
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  event = mk_ev.call
255
279
  event = event.invert if @dual
256
280
  # The extra code.
257
- par(*event) do
281
+ # par(*event) do
282
+ fsm_block(*event) do
258
283
  # Build the extra synchronous part.
259
284
  sync_code = proc do
260
285
  hcase(this.cur_state_sig)
@@ -283,7 +308,8 @@ module HDLRuby::High::Std
283
308
 
284
309
  # Extra asynchronous operative part.
285
310
  if extra_asyncs.any? then
286
- par do
311
+ # par do
312
+ fsm_block do
287
313
  # Build the extra synchronous part.
288
314
  async_code = proc do
289
315
  hcase(this.cur_state_sig)
@@ -406,6 +432,17 @@ module HDLRuby::High::Std
406
432
  return result
407
433
  end
408
434
 
435
+ # Get a state by +name+.
436
+ def get_state(name)
437
+ name = name.to_sym
438
+ (@states.detect { |st| st.name == name }).value
439
+ end
440
+
441
+ # Sets the next state by +name+.
442
+ def next_state(name)
443
+ @next_state_sig <= get_state(name)
444
+ end
445
+
409
446
  # Sets the next state. Arguments can be:
410
447
  #
411
448
  # +name+: the name of the next state.
@@ -75,7 +75,7 @@ module HDLRuby::High::Std
75
75
  base <= lut[address]
76
76
 
77
77
  # Assign the next_data discrete value.
78
- next_data <= lut[address+1]
78
+ next_data <= lut[address+_b1.as(address.type)]
79
79
  end
80
80
 
81
81
 
@@ -107,7 +107,7 @@ module HDLRuby::High::Std
107
107
  end
108
108
 
109
109
  # Make the interpolation.
110
- par do
110
+ seq do
111
111
  diff <= (next_data-base).as(diff.type) * remaining
112
112
  if(otyp.signed?) then
113
113
  interpolated_value <= base +