HDLRuby 2.11.11 → 3.0.0

data/lib/HDLRuby/hruby_verilog.rb

@@ -4,10 +4,8 @@ require "HDLRuby/hruby_verilog_name.rb"
 require 'HDLRuby/hruby_low_mutable'
 
 
-# module HDLRuby::Verilog
 include HDLRuby::Verilog
 
-#include HDLRuby::Low
 module HDLRuby::Low
 
 
@@ -38,12 +36,16 @@ module HDLRuby::Low
     $vector_reg = ""   # For storing signal type at structure declaration. (temporary)
     $vector_cnt = 0    # For allocating numbers at structure declaration.  (temporary)
 
+    
     class ::Integer
+        ## Extends the Integer class with generation of verilog text.
+
         def to_verilog
             to_s
         end
     end
 
+    
     # Class summarizing "hash" used for "par" or "seq" conversion.
     class Fm
         attr_reader :fm_seq, :fm_par, :rep, :rep_sharp
@@ -115,8 +117,9 @@ module HDLRuby::Low
     TruncersI = Truncers.new
 
 
-    # A class that translates the left-hand side, operator, and right-hand side into form of expression.
     class Binary
+        ## Enhances Binary with verilog generation.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "(#{self.left.to_verilog} #{self.operator} #{self.right.to_verilog})"
@@ -158,9 +161,10 @@ module HDLRuby::Low
         end
     end
 
-    # class of Represent blocking substitution or nonblocking assignment.
-    # Enhance Transmit with generation of verilog code.
+
     class Transmit
+        ## Enhances Transmit with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog(spc = 3)
             # Determine blocking assignment or nonblocking substitution from mode and return it.
@@ -169,8 +173,10 @@ module HDLRuby::Low
         end
     end
 
-    # Enhance Print with generation of verilog code.
+
     class Print
+        ## Enhances Print with generation of verilog code.
+
         # Converts the print to Verilog code.
         def to_verilog(spc = 3)
             code = "#{" " * spc}$write(#{self.each_arg.map do |arg|
@@ -180,17 +186,20 @@ module HDLRuby::Low
         end
     end
 
-    # Enhance TimeTerminate with generation of verilog code.
+
     class TimeTerminate
+        ## Enhances TimeTerminate with generation of verilog code.
+
         # Converts the terminate to Verilog code.
         def to_verilog(spc = 3)
             return "#{" " * spc}$finish;"
         end
     end
 
-    # To scheduling to the Block.
-    # Enhance Block with generation of verilog code.
+
     class Block
+        ## Enhances Block with generation of verilog code.
+        # To scheduling to the Block.
 
         # Converts the system to Verilog code adding 'spc' spaces at the begining
         # of each line.
@@ -1439,9 +1448,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to display variable names.
-    # Enhance RefName with generation of verilog code.
+
     class RefName
+        ## Enhances RefName with generation of verilog code.
+
         # Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
         def to_verilog
             vname = name_to_verilog(self.name)
@@ -1463,9 +1473,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to convert an array.
-    # Enhance RefIndex with generation of verilog code.
+    
     class RefIndex
+        ## Enhances RefIndex with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
@@ -1473,9 +1484,9 @@ module HDLRuby::Low
     end
 
 
-    # Used to indicate the number of bits.
-    # Enhance TypeVector with generation of verilog code.
     class TypeVector
+        ## Enhances TypeVector with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # if self.base.name.to_s != "bit"
@@ -1486,16 +1497,22 @@ module HDLRuby::Low
         end
     end
 
-    # Necessary for displaying bit width (eg, specify and assign).
+
     class RefRange
+        ## Enhances RefRange with generation of verilog code.
+
+        # Necessary for displaying bit width (eg, specify and assign).
+
         # Converts the system to Verilog code.
         def to_verilog(unknown = false)
             return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
         end
     end
 
-    # Use it when collecting references.
+
     class RefConcat
+        ## Enhances RefConcat with generation of verilog code.
+
         def to_verilog    
             ref = self.each_ref.to_a
 
@@ -1509,18 +1526,20 @@ module HDLRuby::Low
         end
     end
 
-    # Used to output bitstring.
-    # Enhance HDLRuby with generation of verilog code.
+
     class HDLRuby::BitString
+        ## Enhances BitString with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.to_s}"
         end
     end
 
-    # Used for connection using choice.
-    # Enhance Select with generation of verilog code.
+
     class Select
+        ## Enhances Select with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # Outputs the first and second choices (choice (0) and choice (1)).
@@ -1535,9 +1554,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to output numbers.
-    # Enhance Value with generation of verilog code.
+
     class Value
+        ## Enhances Value with generation of verilog code.
+
         # Converts the system to Verilog code.
         # If it is bit, it is b, and if it is int, it is represented by d. (Example: 4'b0000, 32'd1)
         def to_verilog(unknown = nil)
@@ -1579,9 +1599,9 @@ module HDLRuby::Low
     end
 
 
-    # Used to transrate if.
-    # Enhance If with generation of verilog code.
     class If
+        ## Enhances If with generation of verilog code.
+
         # # Converts the system to Verilog code.
         # def to_verilog(mode = nil)
         # Converts to Verilog code, checking adding 'spc' spaces at the begining
@@ -1617,10 +1637,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to translate case
+
     class Case
-        # def to_verilog(mode = nil)
-        #
+        ## Enhances Case with generation of verilog code.
+
         # Converts to Verilog code, checking if variables are register
         # or wire adding 'spc' spaces at the begining of each line.
         def to_verilog(spc = 3)
@@ -1656,9 +1676,10 @@ module HDLRuby::Low
         end
     end
 
-    # Translate expression of combination circuit.
-    # Enhance Connection with generation of verilog code.
+    
     class Connection
+        ## Enhances Connection with generation of verilog code.
+
         # Converts the system to Verilog code.
 
         # Method used for array.
@@ -1715,23 +1736,29 @@ module HDLRuby::Low
         end
     end
 
-    # It could be used for instantiation.
+    
     class RefThis
+        ## Enhances RefThis with generation of verilog code.
+
         def to_another_verilog
             return ""
         end
     end
 
-    # Used when using "~" for expressions.
+    
     class Unary
+        ## Enhances Unary with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.operator[0]}#{self.child.to_verilog}"
         end
     end
 
-    # Used when casting expressions.
+    
     class Cast
+        ## Enhances Cast with generation of verilog code.
+
         # Converts the system to Verilog code.
         # NOTE: the cast is rounded up size bit-width cast is not supported
         #       by traditional verilog.
@@ -1773,9 +1800,10 @@ module HDLRuby::Low
         end
     end
 
-    # For declaring variables.
-    # Enhance SignalI with generation of verilog code.
+
     class SignalI
+        ## Enhances SignalI with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # Convert unusable characters and return them.
@@ -1785,25 +1813,30 @@ module HDLRuby::Low
         end
     end
 
-    # If it is signed, it outputs signed.
-    # Enhance Type with generation of verilog code.
+    
     class Type
+        ## Enhances Type with generation of verilog code.
+
         # Converts the type to Verilog code.
         def to_verilog
             return self.name == :signed ? "#{self.name.to_s} " : ""
         end
     end
 
-    # Replace type by refered type.
+    
     class TypeDef
+        ## Enhances TypeDef with generation of verilog code.
+
         # Converts the type to verilog code.
         def to_verilog
             return self.def.to_verilog
         end
     end
 
-    # Use it when collecting.
+    
     class Concat
+        ## Enhances Concat with generation of verilog code.
+
         def to_verilog    
             expression = self.each_expression.to_a
 
@@ -1817,14 +1850,19 @@ module HDLRuby::Low
         end
     end
 
-    # Look at the unit of time, convert the time to ps and output it.
-    # One of two people, TimeWait and Delay.
+    
     class TimeWait
+        ## Enhances TimeWait with generation of verilog code.
+
         def to_verilog(spc = 3)
             return (" " * spc) + self.delay.to_verilog + "\n"
         end
     end
+
+
     class Delay
+        ## Enhances Delay with generation of verilog code.
+
         def to_verilog
             time = self.value.to_s
             if(self.unit.to_s == "ps") then
@@ -1842,8 +1880,9 @@ module HDLRuby::Low
     end
 
 
-    # Generate verilog code for the TimeRepeat.
     class TimeRepeat
+        ## Enhances TimeRepeat with generation of verilog code.
+
         def to_verilog(spc = 3)
             result = (" " * spc) + "repeat(#{self.number})" + "\n"
             result << self.statement.to_verilog(spc+3)
@@ -1855,8 +1894,9 @@ module HDLRuby::Low
     #class TypeTuple
     #class Event
 
-    # Enhance SystemT with generation of verilog code.
+    
     class SystemT
+        ## Enhances SystemT with generation of verilog code.
 
         ## Tells if a connection is actually a port connection.
         def port_output_connection?(connection)
@@ -2163,9 +2203,10 @@ module HDLRuby::Low
                         codeC << "),"
                     end
                 end
-                # Remove the last "," for conforming with Verilog syntax.
-                # and close the port connection.
-                codeC[-1] = ");\n"
+                # Remove the last "," if any for conforming with Verilog syntax.
+                codeC.chop! if codeC[-1] == ","
+                # And close the port connection.
+                codeC << ");\n"
             end
 
 
@@ -2254,8 +2295,9 @@ module HDLRuby::Low
     end
 
 
-    # Enhance StringE with generation of verilog code.
     class StringE
+        ## Enhances stringE with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog(spc = 3)
             code = "\"#{Low.v_string(self.content)}" +
@@ -2270,8 +2312,8 @@ end
 
 
 
-## Extends the Numeric class with generation of verilog text.
 class ::Numeric
+## Extends the Numeric class with generation of verilog text.
 
     # Generates the text of the equivalent verilog code.
     # +level+ is the hierachical level of the object.

data/lib/HDLRuby/soft/stacks.rb

@@ -0,0 +1,219 @@
+require 'std/bram'
+
+module HDLRuby::High::Soft
+
+
+    # Declare the possible commands for the stack.
+    PUSH  = 0   # Pushes the value of input din into the stack.
+    POP   = 1   # Pops din values for the stack. If din is negative, allocates din elements on the stack.
+    READ  = 2   # Read the value address din and output it on dout.
+    WRITE = 3   # Write the value at the top of the stack at address din.
+
+
+
+
+
+    # Describe a stack based on a BRAM (compatible with FPGA's)
+    # - 'widthD': data bit width
+    # - 'size'  : the size of the stack
+    system :bram_stack do |widthD, size|
+        # Compute the address width.
+        widthA = (size-1).width
+
+        # Compute the bit width of the stack pointer register.
+        widthS = (size+1).width
+
+        # Declare the inputs and outputs.
+        input :clk, :rst, :ce
+        input :cmd
+        [widthD].input  :din
+        [widthD].output :dout
+        output  :empty, :full
+
+        # Declare the BRAM containing the stack data.
+        inner rwb: 1
+        [widthA].inner :addr
+        [widthD].inner :brin, :brout
+        bram(widthA,widthD).(:bramI).(clk,rwb,addr,brin,brout)
+
+        # Declare the stack pointer register and the top of stack value.
+        [widthS].inner sp: size
+        [widthD].inner :top
+
+        # Tells if the stack is empty or full.
+        empty <= (sp == size)
+        full  <= (sp == 0)
+
+        # The output bus is the top of the stack.
+        dout <= top
+
+        # The clock process handling the access.
+        seq(clk.posedge) do
+            # By default, read before the top of the memory.
+            rwb <= 1
+            hif(rst) do
+                # sp is set to size (stack empty).
+                sp <= size
+                top <= 0
+            end
+            helsif(ce) do
+                # Now depending on the command.
+                hcase(cmd)
+                hwhen(PUSH) do
+                    # Is the stack full?
+                    hif(~full) do
+                        # No, can push onto the stack.
+                        # Update the top register.
+                        top <= din
+                        # Update the bram.
+                        brin <= din
+                        rwb  <= 0
+                        # Finally, decrease sp.
+                        sp <= sp - 1
+                        # The address is the top of the stack
+                        addr <= sp
+                    end
+                end
+                hwhen(POP) do
+                    # Is the stack empty?
+                    hif(~empty) do
+                        # No, can pop from the stack.
+                        # Update the top register.
+                        top <= brout
+                        # Finally, increase sp.
+                        sp <= sp + 1
+                    end
+                end
+            end
+            hif(~ce | cmd != PUSH) do
+                # By default the address is the top of the stack + 1
+                addr <= sp + 1
+            end
+        end
+        
+    end
+
+
+    # Describe a frame stack based on a BRAM (compatible with FPGA's)
+    # - 'widthD': data bit width
+    # - 'size'  : the size of the stack
+    # - 'depth' : the maximum number of frames.
+    system :bram_frame_stack do |widthD, size, depth|
+        # Compute the address width.
+        widthA = (size-1).width
+
+        # Compute the bit width of the frame pointers.
+        widthF = (size+1).width
+
+        # compute the bit width of the frame stack pointer.
+        widthS = (depth+1).width
+
+        # Create the type used for accessing the frame stack.
+        typedef(:locT) { { frame: bit[widthS], offset: bit[widthF] } }
+
+        # Declare the inputs and outputs.
+        input :clk, :rst, :ce
+        [2].input :cmd
+        locT.input :loc
+        [widthD].input  :din
+        [widthD].output :dout
+        output  :empty, :full
+
+        # Declare the frame index stac pointer.
+        [widthS].inner :sp
+
+        # Declare the frame index table.
+        bit[widthF][-depth].inner :indexes
+
+        # Declare the BRAM containing the frames data.
+        inner rwb: 1
+        [widthA].inner :addr
+        [widthD].inner :brin, :brout
+        bram(widthA,widthD).(:bramI).(clk,rwb,addr,brin,brout)
+
+        # Tells if the stack is empty or full.
+        empty <= (sp == depth)
+        full  <= (sp == 0)
+
+        # The input data is always the input of the bram.
+        brin <= din
+
+        # The output is always the output of the bram.
+        dout <= brout
+
+        # The clock process handling the access.
+        seq(clk.posedge) do
+            # By default, read before the top of the memory.
+            rwb <= 1
+            hif(rst) do
+                # sp is set to depth (stack empty).
+                sp <= depth
+            end
+            helsif(ce) do
+                # Now depending on the command.
+                hcase(cmd)
+                hwhen(PUSH) do
+                    # Is the stack full or is the frame to push empty? 
+                    hif(~(full | loc.offset == 0)) do
+                        # No, we can proceed.
+                        # Decrease sp.
+                        sp <= sp - 1
+                        # Adds the frame.
+                        hif(~empty) do
+                            indexes[sp] <= loc.offset + indexes[sp+1]
+                        end
+                        helse do
+                            indexes[sp] <= loc.offset
+                        end
+                    end
+                end
+                hwhen(POP) do
+                    # Is the stack empty?
+                    hif(~empty) do
+                        # No, can pop a frame from the stack.
+                        # Increase sp.
+                        sp <= sp + 1
+                    end
+                end
+                hwhen(READ) do
+                    # Read access, is the frame valid?
+                    cur_frame = sp+loc.frame
+                    hif (~(empty | cur_frame >= depth)) do
+                        # The frame is valid. Is the offset valid?
+                        addr_calc = indexes[cur_frame] - loc.offset - 1
+                        hif ((cur_frame < depth-1) & 
+                             (addr_calc > indexes[cur_frame+1])) do
+                            # Not the first frame and the address is valid.
+                            addr <= addr_calc
+                        end
+                        helsif ((cur_frame == depth-1) &
+                            (addr_calc + 1 > 0)) do
+                            # The first frame and the address is valid.
+                            addr <= addr_calc
+                        end
+                    end
+                end
+                hwhen(WRITE) do
+                    # Write access, is the frame valid?
+                    cur_frame = sp+loc.frame
+                    hif (~(empty | cur_frame >= depth)) do
+                        # The frame is valid. Is the offset valid?
+                        addr_calc = indexes[cur_frame] - loc.offset - 1
+                        hif ((cur_frame < depth-1) & 
+                             (addr_calc > indexes[cur_frame+1])) do
+                            # Not the first frame and the address is valid.
+                            addr <= addr_calc
+                            rwb  <= 0
+                        end
+                        helsif ((cur_frame == depth-1) &
+                            (addr_calc + 1 > 0)) do
+                            # The first frame and the address is valid.
+                            addr <= addr_calc
+                            rwb  <= 0
+                        end
+                    end
+                end
+            end
+        end
+    end
+end

data/lib/HDLRuby/std/bram.rb

@@ -0,0 +1,26 @@
+module HDLRuby::High::Std
+
+    # Describe a RAM compatibile with BRAM of FPGAs.
+    # - 'widthA': address bit width
+    # - 'widthD': data bit width
+    # - 'size':   the size of the memory.
+    system :bram do |widthA, widthD, size = nil|
+        # Process size if required.
+        size = 2**widthA unless size
+        # puts "widthA=#{widthA} widthD=#{widthD} size=#{size}"
+
+        # Declares the io of the ram.
+        input :clk, :rwb
+        [widthA].input :addr
+        [widthD].input :din
+        [widthD].output :dout
+
+        bit[widthD][-size].inner mem: [ :"_b#{"0"*widthD}".to_value ] * size
+
+        par(clk.negedge) do
+            hif(rwb == 0) { mem[addr] <= din }
+            dout <= mem[addr]
+        end
+    end
+
+end

data/lib/HDLRuby/std/clocks.rb

@@ -135,8 +135,8 @@ module HDLRuby::High::Std
 end
 
 
-# Enhnace the events with multiply operator.
 class HDLRuby::High::Event
+    # Enhance the events with multiply operator.
 
     # Creates a new event activated every +times+ occurences of the 
     # current event.

data/lib/HDLRuby/std/fixpoint.rb

@@ -55,14 +55,14 @@ module HDLRuby::High::Std
                             if (typ.signed?) then
                                 (left.as(signed[isize+fsize*2])*right) >> fsize
                             else
-                                (left.as([isize+fsize*2])*right) >> fsize
+                                (left.as(bit[isize+fsize*2])*right) >> fsize
                             end
                         end
                         typ.define_operator(:/) do |left,right|
                             if (typ.signed?) then
                                 (left.as(signed[isize+fsize*2]) << fsize) / right
                             else
-                                (left.as([isize+fsize*2]) << fsize) / right
+                                (left.as(bit[isize+fsize*2]) << fsize) / right
                             end
                         end
                         # Define the removal of the point.