HDLRuby 2.11.11 → 3.0.0

Sign up to get free protection for your applications and to get access to all the features.
Files changed (119) hide show
  1. checksums.yaml +4 -4
  2. data/README.html +3274 -0
  3. data/README.md +608 -99
  4. data/ext/hruby_sim/hruby_rcsim_build.c +27 -0
  5. data/ext/hruby_sim/hruby_sim.h +3 -0
  6. data/ext/hruby_sim/hruby_sim_calc.c +2 -0
  7. data/ext/hruby_sim/hruby_sim_core.c +17 -5
  8. data/ext/hruby_sim/hruby_sim_stack_calc.c +1 -1
  9. data/ext/hruby_sim/hruby_sim_tree_calc.c +8 -1
  10. data/ext/hruby_sim/hruby_sim_vcd.c +24 -7
  11. data/ext/hruby_sim/hruby_sim_vizualize.c +9 -1
  12. data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
  13. data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
  14. data/lib/HDLRuby/hdr_samples/constant_in_function.rb +3 -1
  15. data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +3 -1
  16. data/lib/HDLRuby/hdr_samples/huge_rom.rb +1 -1
  17. data/lib/HDLRuby/hdr_samples/mei8.rb +11 -11
  18. data/lib/HDLRuby/hdr_samples/mei8_bench.rb +12 -12
  19. data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +4 -4
  20. data/lib/HDLRuby/hdr_samples/rom_nest.rb +1 -1
  21. data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +4 -4
  22. data/lib/HDLRuby/hdr_samples/struct.rb +44 -10
  23. data/lib/HDLRuby/hdr_samples/with_bram.rb +45 -0
  24. data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
  25. data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
  26. data/lib/HDLRuby/hdr_samples/with_casts.rb +3 -3
  27. data/lib/HDLRuby/hdr_samples/with_concat.rb +6 -6
  28. data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -2
  29. data/lib/HDLRuby/hdr_samples/with_def.rb +10 -3
  30. data/lib/HDLRuby/hdr_samples/with_define_operator.rb +44 -0
  31. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -12
  32. data/lib/HDLRuby/hdr_samples/with_init.rb +3 -3
  33. data/lib/HDLRuby/hdr_samples/with_leftright.rb +21 -0
  34. data/lib/HDLRuby/hdr_samples/with_reduce.rb +13 -13
  35. data/lib/HDLRuby/hdr_samples/with_ref_array.rb +6 -6
  36. data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
  37. data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
  38. data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
  39. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
  40. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
  41. data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
  42. data/lib/HDLRuby/hdr_samples/with_subsums.rb +3 -3
  43. data/lib/HDLRuby/hdr_samples/with_terminate.rb +3 -3
  44. data/lib/HDLRuby/hdr_samples/with_to_a.rb +10 -10
  45. data/lib/HDLRuby/hdr_samples/with_values.rb +3 -3
  46. data/lib/HDLRuby/hdrcc.rb +29 -3
  47. data/lib/HDLRuby/hdrlib.rb +1 -1
  48. data/lib/HDLRuby/hruby_bstr.rb +10 -5
  49. data/lib/HDLRuby/hruby_db.rb +2 -2
  50. data/lib/HDLRuby/hruby_high.rb +152 -47
  51. data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
  52. data/lib/HDLRuby/hruby_low.rb +189 -18
  53. data/lib/HDLRuby/hruby_low2c.rb +129 -54
  54. data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
  55. data/lib/HDLRuby/hruby_low2high.rb +86 -44
  56. data/lib/HDLRuby/hruby_low2seq.rb +26 -18
  57. data/lib/HDLRuby/hruby_low2sym.rb +14 -13
  58. data/lib/HDLRuby/hruby_low2vhd.rb +80 -44
  59. data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
  60. data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
  61. data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
  62. data/lib/HDLRuby/hruby_low_fix_types.rb +65 -32
  63. data/lib/HDLRuby/hruby_low_mutable.rb +83 -119
  64. data/lib/HDLRuby/hruby_low_resolve.rb +38 -30
  65. data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
  66. data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
  67. data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
  68. data/lib/HDLRuby/hruby_low_without_concat.rb +45 -19
  69. data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
  70. data/lib/HDLRuby/hruby_low_without_parinseq.rb +32 -16
  71. data/lib/HDLRuby/hruby_low_without_select.rb +37 -24
  72. data/lib/HDLRuby/hruby_low_without_subsignals.rb +280 -0
  73. data/lib/HDLRuby/hruby_rcsim.rb +158 -134
  74. data/lib/HDLRuby/hruby_rsim.rb +194 -20
  75. data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
  76. data/lib/HDLRuby/hruby_rsim_vcd.rb +125 -50
  77. data/lib/HDLRuby/hruby_values.rb +48 -33
  78. data/lib/HDLRuby/hruby_verilog.rb +90 -48
  79. data/lib/HDLRuby/soft/stacks.rb +219 -0
  80. data/lib/HDLRuby/std/bram.rb +26 -0
  81. data/lib/HDLRuby/std/clocks.rb +1 -1
  82. data/lib/HDLRuby/std/fixpoint.rb +2 -2
  83. data/lib/HDLRuby/std/fsm.rb +48 -11
  84. data/lib/HDLRuby/std/function_generator.rb +2 -2
  85. data/lib/HDLRuby/std/sequencer.rb +1857 -0
  86. data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
  87. data/lib/HDLRuby/std/std.rb +12 -0
  88. data/lib/HDLRuby/version.rb +1 -1
  89. data/tuto/adder_sat_flags_vcd.png +0 -0
  90. data/tuto/addsub_vcd.png +0 -0
  91. data/tuto/alu_vcd.png +0 -0
  92. data/tuto/bit_pong_vcd.png +0 -0
  93. data/tuto/checksum_vcd.png +0 -0
  94. data/tuto/circuit_hdr.odg +0 -0
  95. data/tuto/circuit_hdr.png +0 -0
  96. data/tuto/circuit_hie.odg +0 -0
  97. data/tuto/circuit_hie.png +0 -0
  98. data/tuto/circuit_view.odg +0 -0
  99. data/tuto/circuit_view.png +0 -0
  100. data/tuto/clock_counter_vcd.png +0 -0
  101. data/tuto/counter_ext_vcd.png +0 -0
  102. data/tuto/fact_vcd.png +0 -0
  103. data/tuto/hw_flow.odg +0 -0
  104. data/tuto/hw_flow.png +0 -0
  105. data/tuto/maxxer_vcd.png +0 -0
  106. data/tuto/pingpong0_vcd.png +0 -0
  107. data/tuto/pingpong1_vcd.png +0 -0
  108. data/tuto/pingpong2_vcd.png +0 -0
  109. data/tuto/ram_vcd.png +0 -0
  110. data/tuto/serializer_vcd.png +0 -0
  111. data/tuto/sw_flow.odg +0 -0
  112. data/tuto/sw_flow.png +0 -0
  113. data/tuto/the_counter_vcd.png +0 -0
  114. data/tuto/tutorial_sw.html +2359 -0
  115. data/tuto/tutorial_sw.md +2684 -0
  116. data/tuto/tutorial_sw.pdf +0 -0
  117. data/tuto/tutorial_sw_jp.md +417 -0
  118. metadata +49 -3
  119. data/lib/HDLRuby/hdr_samples/sumprod.rb +0 -29
@@ -40,9 +40,9 @@ module HDLRuby::High
40
40
  return idstr
41
41
  end
42
42
 
43
- ##
44
- # Enhance the system type class with VCD support.
43
+
45
44
  class SystemT
45
+ # Enhance the system type class with VCD support.
46
46
 
47
47
  ## Initializes the displayer for generating a vcd on +vcdout+
48
48
  def show_init(vcdout)
@@ -94,9 +94,10 @@ module HDLRuby::High
94
94
 
95
95
  ## Gets the VCD variables with their long name.
96
96
  def get_vars_with_fullname(vars_with_fullname = {})
97
- # Adds the signals of the interface of the system.
97
+ # Recurse on the signals.
98
98
  self.each_signal do |sig|
99
- vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
99
+ sig.get_vars_with_fullname(vars_with_fullname)
100
+ # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
100
101
  end
101
102
  # Recurse on the scope.
102
103
  return self.scope.get_vars_with_fullname(vars_with_fullname)
@@ -104,9 +105,13 @@ module HDLRuby::High
104
105
 
105
106
  ## Gets the VCD variables with their id string.
106
107
  def get_vars_with_idstr(vars_with_idstr = {})
107
- # Adds the signals of the interface of the system.
108
+ # # Adds the signals of the interface of the system.
109
+ # self.each_signal do |sig|
110
+ # vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
111
+ # end
112
+ # Recurse on the signals.
108
113
  self.each_signal do |sig|
109
- vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
114
+ sig.get_vars_with_idstr(vars_with_idstr)
110
115
  end
111
116
  # Recurse on the scope.
112
117
  return self.scope.get_vars_with_idstr(vars_with_idstr)
@@ -119,11 +124,11 @@ module HDLRuby::High
119
124
  vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
120
125
  # Shows the interface signals.
121
126
  self.each_signal do |sig|
122
- # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
123
- vcdout << "$var wire #{sig.type.width} "
124
- # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
125
- vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
126
- vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
127
+ sig.show_hierarchy(vcdout)
128
+ # # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
129
+ # vcdout << "$var wire #{sig.type.width} "
130
+ # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
131
+ # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
127
132
  end
128
133
  # Recurse on the scope.
129
134
  self.scope.show_hierarchy(vcdout)
@@ -156,9 +161,9 @@ module HDLRuby::High
156
161
  end
157
162
 
158
163
 
159
- ##
160
- # Enhance the scope class with VCD support.
161
164
  class Scope
165
+ # Enhance the scope class with VCD support.
166
+
162
167
  ## Shows the hierarchy of the variables.
163
168
  def show_hierarchy(vcdout)
164
169
  # puts "show_hierarchy for scope=#{self}"
@@ -170,11 +175,12 @@ module HDLRuby::High
170
175
  end
171
176
  # Shows the inner signals.
172
177
  self.each_inner do |sig|
173
- # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
174
- vcdout << "$var wire #{sig.type.width} "
175
- # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
176
- vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
177
- vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
178
+ sig.show_hierarchy(vcdout)
179
+ # # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
180
+ # vcdout << "$var wire #{sig.type.width} "
181
+ # # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
182
+ # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
183
+ # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
178
184
  end
179
185
  # Recurse on the behaviors' blocks
180
186
  self.each_behavior do |beh|
@@ -196,9 +202,14 @@ module HDLRuby::High
196
202
 
197
203
  ## Gets the VCD variables with their long name.
198
204
  def get_vars_with_fullname(vars_with_fullname = {})
199
- # Adds the inner signals.
205
+ # # Adds the inner signals.
206
+ # self.each_inner do |sig|
207
+ # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
208
+ # end
209
+ # Recurse on the inner signals.
200
210
  self.each_inner do |sig|
201
- vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
211
+ sig.get_vars_with_fullname(vars_with_fullname)
212
+ # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
202
213
  end
203
214
  # Recurse on the behaviors' blocks
204
215
  self.each_behavior do |beh|
@@ -217,9 +228,13 @@ module HDLRuby::High
217
228
 
218
229
  ## Gets the VCD variables with their id string.
219
230
  def get_vars_with_idstr(vars_with_idstr = {})
220
- # Adds the inner signals.
231
+ # # Adds the inner signals.
232
+ # self.each_inner do |sig|
233
+ # vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
234
+ # end
235
+ # Recurse on the inner signals.
221
236
  self.each_inner do |sig|
222
- vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
237
+ sig.get_vars_with_idstr(vars_with_idstr)
223
238
  end
224
239
  # Recurse on the behaviors' blocks
225
240
  self.each_behavior do |beh|
@@ -238,9 +253,58 @@ module HDLRuby::High
238
253
  end
239
254
 
240
255
 
241
- ##
242
- # Enhance the Transmit class with VCD support.
256
+ module SimSignal
257
+ # Enhance the signals class with VCD support.
258
+
259
+ ## Shows the hierarchy of the variables.
260
+ def show_hierarchy(vcdout)
261
+ # puts "show_hierarcy for signal=#{self.name}"
262
+ if self.each_signal.any? then
263
+ # The signal is hierarchical, recurse on the sub signals.
264
+ vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
265
+ self.each_signal { |sig| sig.show_hierarchy(vcdout) }
266
+ vcdout << "$upscope $end\n"
267
+ else
268
+ # This is a signal to show.
269
+ vcdout << "$var wire #{self.type.width} "
270
+ vcdout << "#{HDLRuby::High.vcd_idstr(self)} "
271
+ vcdout << "#{HDLRuby::High.vcd_name(self.name)} $end\n"
272
+ end
273
+ end
274
+
275
+ ## Gets the VCD variables with their long name.
276
+ def get_vars_with_fullname(vars_with_fullname = {})
277
+ if self.each_signal.any? then
278
+ # There are sub signals, recurse on them.
279
+ self.each_signal do |sig|
280
+ sig.get_vars_with_fullname(vars_with_fullname)
281
+ end
282
+ else
283
+ # No add the current signal.
284
+ vars_with_fullname[self] = HDLRuby::High.vcd_name(self.fullname)
285
+ end
286
+ return vars_with_full_name
287
+ end
288
+
289
+ ## Gets the VCD variables with their id string.
290
+ def get_vars_with_idstr(vars_with_idstr = {})
291
+ if self.each_signal.any? then
292
+ # There are sub signals, recurse on them.
293
+ self.each_signal do |sig|
294
+ sig.get_vars_with_idstr(vars_with_idstr)
295
+ end
296
+ else
297
+ # No add the current signal.
298
+ vars_with_idstr[self] = HDLRuby::High.vcd_idstr(self)
299
+ end
300
+ return vars_with_idstr
301
+ end
302
+ end
303
+
304
+
243
305
  class Transmit
306
+ # Enhance the Transmit class with VCD support.
307
+
244
308
  ## Shows the hierarchy of the variables.
245
309
  def show_hierarchy(vcdout)
246
310
  # By default: nothing to do.
@@ -257,9 +321,10 @@ module HDLRuby::High
257
321
  end
258
322
  end
259
323
 
260
- ##
261
- # Enhance the TimeRepeat class with VCD support.
324
+
262
325
  class TimeRepeat
326
+ # Enhance the TimeRepeat class with VCD support.
327
+
263
328
  ## Shows the hierarchy of the variables.
264
329
  def show_hierarchy(vcdout)
265
330
  # Recurse on the statement.
@@ -277,9 +342,10 @@ module HDLRuby::High
277
342
  end
278
343
  end
279
344
 
280
- ##
281
- # Enhance the TimeWait class with VCD support.
345
+
282
346
  class TimeWait
347
+ # Enhance the TimeWait class with VCD support.
348
+
283
349
  ## Shows the hierarchy of the variables.
284
350
  def show_hierarchy(vcdout)
285
351
  # By default: nothing to do.
@@ -296,9 +362,10 @@ module HDLRuby::High
296
362
  end
297
363
  end
298
364
 
299
- ##
300
- # Enhance the Print class with VCD support.
365
+
301
366
  class Print
367
+ # Enhance the Print class with VCD support.
368
+
302
369
  ## Shows the hierarchy of the variables.
303
370
  def show_hierarchy(vcdout)
304
371
  # By default: nothing to do.
@@ -316,7 +383,7 @@ module HDLRuby::High
316
383
  end
317
384
 
318
385
 
319
- ## Module adding show_hierarchyto block objects.
386
+ ## Module adding show_hierarchy to block objects.
320
387
  module BlockHierarchy
321
388
  ## Shows the hierarchy of the variables.
322
389
  def show_hierarchy(vcdout)
@@ -329,11 +396,12 @@ module HDLRuby::High
329
396
  end
330
397
  # Shows the inner signals.
331
398
  self.each_inner do |sig|
332
- # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
333
- vcdout << "$var wire #{sig.type.width} "
334
- # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
335
- vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
336
- vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
399
+ sig.show_hierarchy(vcdout)
400
+ # # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
401
+ # vcdout << "$var wire #{sig.type.width} "
402
+ # # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
403
+ # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
404
+ # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
337
405
  end
338
406
  # Recurse on the statements
339
407
  self.each_statement do |stmnt|
@@ -347,9 +415,14 @@ module HDLRuby::High
347
415
 
348
416
  ## Gets the VCD variables with their long name.
349
417
  def get_vars_with_fullname(vars_with_fullname = {})
350
- # Adds the inner signals.
418
+ # # Adds the inner signals.
419
+ # self.each_inner do |sig|
420
+ # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
421
+ # end
422
+ # Recurse on the inner signals.
351
423
  self.each_inner do |sig|
352
- vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
424
+ sig.get_vars_with_fullname(vars_with_fullname)
425
+ # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
353
426
  end
354
427
  # Recurse on the statements.
355
428
  self.each_statement do |stmnt|
@@ -360,9 +433,13 @@ module HDLRuby::High
360
433
 
361
434
  ## Gets the VCD variables with their id string.
362
435
  def get_vars_with_idstr(vars_with_idstr = {})
363
- # Adds the inner signals.
436
+ # # Adds the inner signals.
437
+ # self.each_inner do |sig|
438
+ # vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
439
+ # end
440
+ # Recurse on the inner signals.
364
441
  self.each_inner do |sig|
365
- vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
442
+ sif.get_vars_with_idstr(vars_with_idstr)
366
443
  end
367
444
  # Recurse on the statements.
368
445
  self.each_statement do |stmnt|
@@ -373,23 +450,20 @@ module HDLRuby::High
373
450
  end
374
451
 
375
452
 
376
- ##
377
- # Enhance the block class with VCD support.
378
453
  class Block
454
+ # Enhance the block class with VCD support.
379
455
  include HDLRuby::High::BlockHierarchy
380
456
  end
381
457
 
382
458
 
383
- ##
384
- # Enhance the block class with VCD support.
385
459
  class TimeBlock
460
+ # Enhance the block class with VCD support.
386
461
  include HDLRuby::High::BlockHierarchy
387
462
  end
388
463
 
389
464
 
390
- ##
391
- # Enhance the if class with VCD support.
392
465
  class If
466
+ # Enhance the if class with VCD support.
393
467
  ## Shows the hierarchy of the variables.
394
468
  def show_hierarchy(vcdout)
395
469
  # Recurse on the yes.
@@ -430,9 +504,9 @@ module HDLRuby::High
430
504
  end
431
505
 
432
506
 
433
- ##
434
- # Enhance the Case class with VCD support.
435
507
  class Case
508
+ # Enhance the Case class with VCD support.
509
+
436
510
  ## Shows the hierarchy of the variables.
437
511
  def show_hierarchy(vcdout)
438
512
  # Recurse on each when.
@@ -466,9 +540,10 @@ module HDLRuby::High
466
540
  end
467
541
  end
468
542
 
469
- ##
470
- # Enhance the TimeRepeat class with VCD support.
543
+
471
544
  class TimeRepeat
545
+ # Enhance the TimeRepeat class with VCD support.
546
+
472
547
  ## Shows the hierarchy of the variables.
473
548
  def show_hierarchy(vcdout)
474
549
  # Recurse on the statement.
@@ -13,6 +13,9 @@ module HDLRuby
13
13
 
14
14
  # Truncs integer +val+ to +width+
15
15
  def trunc(val,width)
16
+ if val.is_a?(BitString) then
17
+ return val[(width-1)..0]
18
+ end
16
19
  if val.bit_length > width then
17
20
  if val >= 0 then
18
21
  # return val & (2**width-1)
@@ -38,8 +41,9 @@ module HDLRuby
38
41
  unless val.to_value? then
39
42
  # Not computable, use the former method that generates
40
43
  # HDLRuby code.
41
- return self.send(orig_operator(op),value)
44
+ return self.send(orig_operator(op),val)
42
45
  end
46
+ val = val.to_value unless val.is_a?(Value)
43
47
  # Handle Numeric op BitString case.
44
48
  if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
45
49
  if val.content.specified? then
@@ -52,7 +56,7 @@ module HDLRuby
52
56
  else
53
57
  # Generate the resulting content.
54
58
  res_content = self.content.send(op,val.content)
55
- # puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})" if op == :^
59
+ # puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})"
56
60
  end
57
61
  res_type = self.type.resolve(val.type)
58
62
  # # Adjust the result content size.
@@ -80,27 +84,29 @@ module HDLRuby
80
84
  return self.send(orig_operator(op),val)
81
85
  end
82
86
  # Process left.
83
- # unless left.is_a?(Numeric) || left.is_a?(BitString) then
84
- # left = left.to_value.content
85
- # end
86
- left = left.content
87
- if left.is_a?(BitString) && !left.specified? then
88
- return self.class.new(self.type.base,
89
- BitString::UNKNOWN.clone)
87
+ if left.is_a?(Value) then
88
+ left = left.content
89
+ if left.is_a?(BitString) && !left.specified? then
90
+ return self.class.new(self.type.base,
91
+ BitString::UNKNOWN.clone)
92
+ end
93
+ # left = left.to_i
94
+ left = self.trunc(left.to_i,val.first.type.width)
95
+ else
96
+ left = left.to_i
90
97
  end
91
- # left = left.to_i
92
- left = self.trunc(left.to_i,val.first.type.width)
93
98
  # Process right.
94
- # unless right.is_a?(Numeric) || right.is_a?(BitString) then
95
- # right = right.to_value.content
96
- # end
97
- right = right.content
98
- if right.is_a?(BitString) && !right.specified? then
99
- return self.class.new(self.type.base,
100
- BitString::UNKNOWN.clone)
99
+ if right.is_a?(Value) then
100
+ right = right.content
101
+ if right.is_a?(BitString) && !right.specified? then
102
+ return self.class.new(self.type.base,
103
+ BitString::UNKNOWN.clone)
104
+ end
105
+ # right = right.to_i
106
+ right = self.trunc(right.to_i,val.last.type.width)
107
+ else
108
+ right = right.to_i
101
109
  end
102
- # right = right.to_i
103
- right = self.trunc(right.to_i,val.last.type.width)
104
110
  # Generate the resulting type.
105
111
  res_type = self.type.base[(left-right+1).abs]
106
112
  # Generate the resulting value.
@@ -124,18 +130,16 @@ module HDLRuby
124
130
  return self.send(orig_operator(op),val)
125
131
  end
126
132
  # Process val.
127
- index = val.content
128
- if index.is_a?(BitString) && !index.specified? then
129
- return self.class.new(self.type.base,
130
- BitString::UNKNOWN.clone)
133
+ if val.is_a?(Value) then
134
+ index = val.content
135
+ if index.is_a?(BitString) && !index.specified? then
136
+ return self.class.new(self.type.base,
137
+ BitString::UNKNOWN.clone)
138
+ end
139
+ index = self.trunc(index.to_i,val.type.width)
140
+ else
141
+ index = val.to_i
131
142
  end
132
- index = self.trunc(index.to_i,val.type.width)
133
- # index = index.to_i
134
- # if index >= self.type.size then
135
- # # puts "index=#{index}"
136
- # index %= self.type.size
137
- # # puts "now index=#{index}"
138
- # end
139
143
  # Generate the resulting type.
140
144
  res_type = self.type.base
141
145
  # Generate the resulting value.
@@ -144,9 +148,11 @@ module HDLRuby
144
148
  if self.content.is_a?(BitString) then
145
149
  res_content = self.content[index*width..(index+1)*width-1]
146
150
  else
151
+ # puts "self.content=#{self.content} index=#{index}"
147
152
  sh = index*width
148
153
  mask = (-1 << sh) & ~(-1 << (index+1)*width)
149
154
  res_content = (self.content & mask) >> sh
155
+ # puts "res_content=#{res_content}"
150
156
  end
151
157
  # Return the resulting value.
152
158
  return self.class.new(res_type,res_content)
@@ -236,7 +242,7 @@ module HDLRuby
236
242
  # Generate the resulting type.
237
243
  res_type = self.type
238
244
  # Generate the resulting content.
239
- # puts "op=#{op} content=#{content.to_s}"
245
+ # puts "op=#{op} content=#{content.to_s} width=#{res_type.width}"
240
246
  res_content = self.content.send(op)
241
247
  # puts "res_content=#{res_content}"
242
248
  # Return the resulting value.
@@ -275,6 +281,9 @@ module HDLRuby
275
281
  res_content.positive!
276
282
  end
277
283
  end
284
+ if type.signed && res_content.is_a?(Numeric) && res_content >= (1 << (type.width-1)) then
285
+ res_content = (-1 << type.width) + res_content
286
+ end
278
287
  # # truncs to the right size if necessary.
279
288
  # if res_content.is_a?(BitString) then
280
289
  # res_content.trunc!(type.width)
@@ -308,7 +317,7 @@ module HDLRuby
308
317
  break if count == width
309
318
  end
310
319
  if count < width then
311
- res_content.concat(res_content[-1] * (width-count))
320
+ res_content.concat([res_content[-1]] * (width-count))
312
321
  end
313
322
  else
314
323
  width.times do |p|
@@ -401,6 +410,12 @@ module HDLRuby
401
410
  end
402
411
  end
403
412
 
413
+ # Tell if the value is high impedance.
414
+ def impedence?
415
+ return false unless @content.is_a?(BitString)
416
+ return @content.raw_content.include?(2)
417
+ end
418
+
404
419
  ## Converts the value to a string of the right size.
405
420
  def to_vstr
406
421
  if self.content.is_a?(Numeric) then