HDLRuby 2.11.11 → 3.0.0
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- checksums.yaml +4 -4
- data/README.html +3274 -0
- data/README.md +608 -99
- data/ext/hruby_sim/hruby_rcsim_build.c +27 -0
- data/ext/hruby_sim/hruby_sim.h +3 -0
- data/ext/hruby_sim/hruby_sim_calc.c +2 -0
- data/ext/hruby_sim/hruby_sim_core.c +17 -5
- data/ext/hruby_sim/hruby_sim_stack_calc.c +1 -1
- data/ext/hruby_sim/hruby_sim_tree_calc.c +8 -1
- data/ext/hruby_sim/hruby_sim_vcd.c +24 -7
- data/ext/hruby_sim/hruby_sim_vizualize.c +9 -1
- data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
- data/lib/HDLRuby/hdr_samples/constant_in_function.rb +3 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +3 -1
- data/lib/HDLRuby/hdr_samples/huge_rom.rb +1 -1
- data/lib/HDLRuby/hdr_samples/mei8.rb +11 -11
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +12 -12
- data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +4 -4
- data/lib/HDLRuby/hdr_samples/rom_nest.rb +1 -1
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +4 -4
- data/lib/HDLRuby/hdr_samples/struct.rb +44 -10
- data/lib/HDLRuby/hdr_samples/with_bram.rb +45 -0
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_casts.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_concat.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -2
- data/lib/HDLRuby/hdr_samples/with_def.rb +10 -3
- data/lib/HDLRuby/hdr_samples/with_define_operator.rb +44 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -12
- data/lib/HDLRuby/hdr_samples/with_init.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_leftright.rb +21 -0
- data/lib/HDLRuby/hdr_samples/with_reduce.rb +13 -13
- data/lib/HDLRuby/hdr_samples/with_ref_array.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
- data/lib/HDLRuby/hdr_samples/with_subsums.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_terminate.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_to_a.rb +10 -10
- data/lib/HDLRuby/hdr_samples/with_values.rb +3 -3
- data/lib/HDLRuby/hdrcc.rb +29 -3
- data/lib/HDLRuby/hdrlib.rb +1 -1
- data/lib/HDLRuby/hruby_bstr.rb +10 -5
- data/lib/HDLRuby/hruby_db.rb +2 -2
- data/lib/HDLRuby/hruby_high.rb +152 -47
- data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +189 -18
- data/lib/HDLRuby/hruby_low2c.rb +129 -54
- data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
- data/lib/HDLRuby/hruby_low2high.rb +86 -44
- data/lib/HDLRuby/hruby_low2seq.rb +26 -18
- data/lib/HDLRuby/hruby_low2sym.rb +14 -13
- data/lib/HDLRuby/hruby_low2vhd.rb +80 -44
- data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
- data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
- data/lib/HDLRuby/hruby_low_fix_types.rb +65 -32
- data/lib/HDLRuby/hruby_low_mutable.rb +83 -119
- data/lib/HDLRuby/hruby_low_resolve.rb +38 -30
- data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
- data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
- data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
- data/lib/HDLRuby/hruby_low_without_concat.rb +45 -19
- data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +32 -16
- data/lib/HDLRuby/hruby_low_without_select.rb +37 -24
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +280 -0
- data/lib/HDLRuby/hruby_rcsim.rb +158 -134
- data/lib/HDLRuby/hruby_rsim.rb +194 -20
- data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
- data/lib/HDLRuby/hruby_rsim_vcd.rb +125 -50
- data/lib/HDLRuby/hruby_values.rb +48 -33
- data/lib/HDLRuby/hruby_verilog.rb +90 -48
- data/lib/HDLRuby/soft/stacks.rb +219 -0
- data/lib/HDLRuby/std/bram.rb +26 -0
- data/lib/HDLRuby/std/clocks.rb +1 -1
- data/lib/HDLRuby/std/fixpoint.rb +2 -2
- data/lib/HDLRuby/std/fsm.rb +48 -11
- data/lib/HDLRuby/std/function_generator.rb +2 -2
- data/lib/HDLRuby/std/sequencer.rb +1857 -0
- data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
- data/lib/HDLRuby/std/std.rb +12 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/tuto/adder_sat_flags_vcd.png +0 -0
- data/tuto/addsub_vcd.png +0 -0
- data/tuto/alu_vcd.png +0 -0
- data/tuto/bit_pong_vcd.png +0 -0
- data/tuto/checksum_vcd.png +0 -0
- data/tuto/circuit_hdr.odg +0 -0
- data/tuto/circuit_hdr.png +0 -0
- data/tuto/circuit_hie.odg +0 -0
- data/tuto/circuit_hie.png +0 -0
- data/tuto/circuit_view.odg +0 -0
- data/tuto/circuit_view.png +0 -0
- data/tuto/clock_counter_vcd.png +0 -0
- data/tuto/counter_ext_vcd.png +0 -0
- data/tuto/fact_vcd.png +0 -0
- data/tuto/hw_flow.odg +0 -0
- data/tuto/hw_flow.png +0 -0
- data/tuto/maxxer_vcd.png +0 -0
- data/tuto/pingpong0_vcd.png +0 -0
- data/tuto/pingpong1_vcd.png +0 -0
- data/tuto/pingpong2_vcd.png +0 -0
- data/tuto/ram_vcd.png +0 -0
- data/tuto/serializer_vcd.png +0 -0
- data/tuto/sw_flow.odg +0 -0
- data/tuto/sw_flow.png +0 -0
- data/tuto/the_counter_vcd.png +0 -0
- data/tuto/tutorial_sw.html +2359 -0
- data/tuto/tutorial_sw.md +2684 -0
- data/tuto/tutorial_sw.pdf +0 -0
- data/tuto/tutorial_sw_jp.md +417 -0
- metadata +49 -3
- data/lib/HDLRuby/hdr_samples/sumprod.rb +0 -29
@@ -40,9 +40,9 @@ module HDLRuby::High
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return idstr
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end
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# Enhance the system type class with VCD support.
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class SystemT
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# Enhance the system type class with VCD support.
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## Initializes the displayer for generating a vcd on +vcdout+
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def show_init(vcdout)
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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#
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# Recurse on the signals.
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self.each_signal do |sig|
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sig.get_vars_with_fullname(vars_with_fullname)
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# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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end
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return self.scope.get_vars_with_fullname(vars_with_fullname)
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## Gets the VCD variables with their id string.
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def get_vars_with_idstr(vars_with_idstr = {})
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# Adds the signals of the interface of the system.
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# # Adds the signals of the interface of the system.
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# self.each_signal do |sig|
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# vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
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# end
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sig.get_vars_with_idstr(vars_with_idstr)
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end
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# Recurse on the scope.
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return self.scope.get_vars_with_idstr(vars_with_idstr)
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vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
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# Shows the interface signals.
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self.each_signal do |sig|
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# vcdout << "#{
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vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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sig.show_hierarchy(vcdout)
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# # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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# vcdout << "$var wire #{sig.type.width} "
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# vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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# vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the scope.
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self.scope.show_hierarchy(vcdout)
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end
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##
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# Enhance the scope class with VCD support.
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class Scope
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# Enhance the scope class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# puts "show_hierarchy for scope=#{self}"
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end
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# Shows the inner signals.
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self.each_inner do |sig|
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vcdout << "#{HDLRuby::High.
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vcdout << "#{HDLRuby::High.
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sig.show_hierarchy(vcdout)
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# # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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# vcdout << "$var wire #{sig.type.width} "
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# # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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# vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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# vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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# Recurse on the behaviors' blocks
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# Adds the inner signals.
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# # Adds the inner signals.
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# self.each_inner do |sig|
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# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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# end
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# Recurse on the inner signals.
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sig.get_vars_with_fullname(vars_with_fullname)
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# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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## Gets the VCD variables with their id string.
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def get_vars_with_idstr(vars_with_idstr = {})
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# # Adds the inner signals.
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# self.each_inner do |sig|
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# vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
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# end
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self.each_inner do |sig|
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sig.get_vars_with_idstr(vars_with_idstr)
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end
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module SimSignal
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# Enhance the signals class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# puts "show_hierarcy for signal=#{self.name}"
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if self.each_signal.any? then
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# The signal is hierarchical, recurse on the sub signals.
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vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
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self.each_signal { |sig| sig.show_hierarchy(vcdout) }
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vcdout << "$upscope $end\n"
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else
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# This is a signal to show.
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vcdout << "$var wire #{self.type.width} "
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vcdout << "#{HDLRuby::High.vcd_idstr(self)} "
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vcdout << "#{HDLRuby::High.vcd_name(self.name)} $end\n"
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end
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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if self.each_signal.any? then
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# There are sub signals, recurse on them.
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self.each_signal do |sig|
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sig.get_vars_with_fullname(vars_with_fullname)
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end
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else
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# No add the current signal.
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vars_with_fullname[self] = HDLRuby::High.vcd_name(self.fullname)
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end
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return vars_with_full_name
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end
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## Gets the VCD variables with their id string.
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def get_vars_with_idstr(vars_with_idstr = {})
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if self.each_signal.any? then
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# There are sub signals, recurse on them.
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self.each_signal do |sig|
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sig.get_vars_with_idstr(vars_with_idstr)
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end
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else
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# No add the current signal.
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vars_with_idstr[self] = HDLRuby::High.vcd_idstr(self)
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end
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return vars_with_idstr
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end
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end
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class Transmit
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# Enhance the Transmit class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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end
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end
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# Enhance the TimeRepeat class with VCD support.
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class TimeRepeat
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# Enhance the TimeRepeat class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# Recurse on the statement.
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end
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end
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# Enhance the TimeWait class with VCD support.
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class TimeWait
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# Enhance the TimeWait class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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end
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end
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# Enhance the Print class with VCD support.
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class Print
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# Enhance the Print class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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end
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## Module adding
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## Module adding show_hierarchy to block objects.
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module BlockHierarchy
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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end
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# Shows the inner signals.
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self.each_inner do |sig|
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# vcdout << "#{
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vcdout << "#{HDLRuby::High.
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vcdout << "#{HDLRuby::High.
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sig.show_hierarchy(vcdout)
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# # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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# vcdout << "$var wire #{sig.type.width} "
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# # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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# vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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# vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the statements
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self.each_statement do |stmnt|
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@@ -347,9 +415,14 @@ module HDLRuby::High
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347
415
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348
416
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## Gets the VCD variables with their long name.
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349
417
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def get_vars_with_fullname(vars_with_fullname = {})
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350
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-
# Adds the inner signals.
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418
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+
# # Adds the inner signals.
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419
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+
# self.each_inner do |sig|
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420
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+
# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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421
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+
# end
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422
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+
# Recurse on the inner signals.
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351
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self.each_inner do |sig|
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352
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-
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424
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+
sig.get_vars_with_fullname(vars_with_fullname)
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425
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+
# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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353
426
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end
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354
427
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# Recurse on the statements.
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self.each_statement do |stmnt|
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@@ -360,9 +433,13 @@ module HDLRuby::High
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360
433
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434
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## Gets the VCD variables with their id string.
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362
435
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def get_vars_with_idstr(vars_with_idstr = {})
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363
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-
# Adds the inner signals.
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436
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+
# # Adds the inner signals.
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437
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+
# self.each_inner do |sig|
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438
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+
# vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
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439
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+
# end
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440
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+
# Recurse on the inner signals.
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self.each_inner do |sig|
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365
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-
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442
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sif.get_vars_with_idstr(vars_with_idstr)
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443
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end
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444
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# Recurse on the statements.
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self.each_statement do |stmnt|
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@@ -373,23 +450,20 @@ module HDLRuby::High
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373
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end
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374
451
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375
452
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376
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-
##
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377
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-
# Enhance the block class with VCD support.
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378
453
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class Block
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454
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+
# Enhance the block class with VCD support.
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379
455
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include HDLRuby::High::BlockHierarchy
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380
456
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end
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381
457
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382
458
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383
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-
##
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384
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-
# Enhance the block class with VCD support.
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385
459
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class TimeBlock
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460
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+
# Enhance the block class with VCD support.
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include HDLRuby::High::BlockHierarchy
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end
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388
463
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389
464
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390
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-
##
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391
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-
# Enhance the if class with VCD support.
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392
465
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class If
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466
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+
# Enhance the if class with VCD support.
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393
467
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## Shows the hierarchy of the variables.
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394
468
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def show_hierarchy(vcdout)
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# Recurse on the yes.
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@@ -430,9 +504,9 @@ module HDLRuby::High
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end
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433
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-
##
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434
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-
# Enhance the Case class with VCD support.
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435
507
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class Case
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508
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+
# Enhance the Case class with VCD support.
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509
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+
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436
510
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## Shows the hierarchy of the variables.
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437
511
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def show_hierarchy(vcdout)
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438
512
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# Recurse on each when.
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@@ -466,9 +540,10 @@ module HDLRuby::High
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466
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end
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467
541
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end
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468
542
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469
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-
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470
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-
# Enhance the TimeRepeat class with VCD support.
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543
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+
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471
544
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class TimeRepeat
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545
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+
# Enhance the TimeRepeat class with VCD support.
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546
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+
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472
547
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## Shows the hierarchy of the variables.
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473
548
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def show_hierarchy(vcdout)
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474
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# Recurse on the statement.
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data/lib/HDLRuby/hruby_values.rb
CHANGED
@@ -13,6 +13,9 @@ module HDLRuby
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13
13
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14
14
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# Truncs integer +val+ to +width+
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15
15
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def trunc(val,width)
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16
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if val.is_a?(BitString) then
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17
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return val[(width-1)..0]
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18
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end
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16
19
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if val.bit_length > width then
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17
20
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if val >= 0 then
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18
21
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# return val & (2**width-1)
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@@ -38,8 +41,9 @@ module HDLRuby
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38
41
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unless val.to_value? then
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39
42
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# Not computable, use the former method that generates
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40
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# HDLRuby code.
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41
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-
return self.send(orig_operator(op),
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44
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+
return self.send(orig_operator(op),val)
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42
45
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end
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46
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+
val = val.to_value unless val.is_a?(Value)
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43
47
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# Handle Numeric op BitString case.
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44
48
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if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
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45
49
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if val.content.specified? then
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@@ -52,7 +56,7 @@ module HDLRuby
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52
56
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else
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53
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# Generate the resulting content.
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54
58
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res_content = self.content.send(op,val.content)
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55
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-
# puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})"
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59
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+
# puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})"
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56
60
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end
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57
61
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res_type = self.type.resolve(val.type)
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58
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# # Adjust the result content size.
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@@ -80,27 +84,29 @@ module HDLRuby
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80
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return self.send(orig_operator(op),val)
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81
85
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end
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82
86
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# Process left.
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83
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-
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-
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85
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-
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-
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87
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-
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-
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89
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-
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87
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+
if left.is_a?(Value) then
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88
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left = left.content
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89
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+
if left.is_a?(BitString) && !left.specified? then
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90
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return self.class.new(self.type.base,
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91
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BitString::UNKNOWN.clone)
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92
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end
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93
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# left = left.to_i
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94
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left = self.trunc(left.to_i,val.first.type.width)
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95
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else
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96
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left = left.to_i
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90
97
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end
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91
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-
# left = left.to_i
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92
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-
left = self.trunc(left.to_i,val.first.type.width)
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93
98
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# Process right.
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94
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-
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-
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96
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-
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97
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-
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98
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-
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99
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-
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100
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-
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99
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+
if right.is_a?(Value) then
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100
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+
right = right.content
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101
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+
if right.is_a?(BitString) && !right.specified? then
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102
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return self.class.new(self.type.base,
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BitString::UNKNOWN.clone)
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104
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+
end
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105
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+
# right = right.to_i
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106
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+
right = self.trunc(right.to_i,val.last.type.width)
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107
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else
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108
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+
right = right.to_i
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101
109
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end
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102
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-
# right = right.to_i
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103
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-
right = self.trunc(right.to_i,val.last.type.width)
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# Generate the resulting type.
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105
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res_type = self.type.base[(left-right+1).abs]
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# Generate the resulting value.
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@@ -124,18 +130,16 @@ module HDLRuby
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124
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return self.send(orig_operator(op),val)
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end
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# Process val.
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-
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-
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-
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-
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133
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+
if val.is_a?(Value) then
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134
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+
index = val.content
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135
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+
if index.is_a?(BitString) && !index.specified? then
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136
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+
return self.class.new(self.type.base,
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137
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+
BitString::UNKNOWN.clone)
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138
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+
end
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139
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+
index = self.trunc(index.to_i,val.type.width)
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+
else
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141
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+
index = val.to_i
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end
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132
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-
index = self.trunc(index.to_i,val.type.width)
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-
# index = index.to_i
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-
# if index >= self.type.size then
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135
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-
# # puts "index=#{index}"
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-
# index %= self.type.size
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-
# # puts "now index=#{index}"
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138
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-
# end
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139
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# Generate the resulting type.
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140
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res_type = self.type.base
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# Generate the resulting value.
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@@ -144,9 +148,11 @@ module HDLRuby
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144
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if self.content.is_a?(BitString) then
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145
149
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res_content = self.content[index*width..(index+1)*width-1]
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146
150
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else
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151
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+
# puts "self.content=#{self.content} index=#{index}"
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147
152
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sh = index*width
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148
153
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mask = (-1 << sh) & ~(-1 << (index+1)*width)
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149
154
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res_content = (self.content & mask) >> sh
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155
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+
# puts "res_content=#{res_content}"
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150
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end
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# Return the resulting value.
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152
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return self.class.new(res_type,res_content)
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@@ -236,7 +242,7 @@ module HDLRuby
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236
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# Generate the resulting type.
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237
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res_type = self.type
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238
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# Generate the resulting content.
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239
|
-
# puts "op=#{op} content=#{content.to_s}"
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245
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+
# puts "op=#{op} content=#{content.to_s} width=#{res_type.width}"
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240
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res_content = self.content.send(op)
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241
247
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# puts "res_content=#{res_content}"
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242
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# Return the resulting value.
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@@ -275,6 +281,9 @@ module HDLRuby
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275
281
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res_content.positive!
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276
282
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end
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277
283
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end
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284
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+
if type.signed && res_content.is_a?(Numeric) && res_content >= (1 << (type.width-1)) then
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285
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+
res_content = (-1 << type.width) + res_content
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286
|
+
end
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278
287
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# # truncs to the right size if necessary.
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279
288
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# if res_content.is_a?(BitString) then
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280
289
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# res_content.trunc!(type.width)
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@@ -308,7 +317,7 @@ module HDLRuby
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308
317
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break if count == width
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309
318
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end
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310
319
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if count < width then
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311
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-
res_content.concat(res_content[-1] * (width-count))
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320
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+
res_content.concat([res_content[-1]] * (width-count))
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312
321
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end
|
313
322
|
else
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314
323
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width.times do |p|
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@@ -401,6 +410,12 @@ module HDLRuby
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|
401
410
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end
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402
411
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end
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403
412
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|
413
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+
# Tell if the value is high impedance.
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414
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+
def impedence?
|
415
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+
return false unless @content.is_a?(BitString)
|
416
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+
return @content.raw_content.include?(2)
|
417
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+
end
|
418
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+
|
404
419
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## Converts the value to a string of the right size.
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405
420
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def to_vstr
|
406
421
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if self.content.is_a?(Numeric) then
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