HDLRuby 2.11.11 → 3.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.html +3274 -0
- data/README.md +608 -99
- data/ext/hruby_sim/hruby_rcsim_build.c +27 -0
- data/ext/hruby_sim/hruby_sim.h +3 -0
- data/ext/hruby_sim/hruby_sim_calc.c +2 -0
- data/ext/hruby_sim/hruby_sim_core.c +17 -5
- data/ext/hruby_sim/hruby_sim_stack_calc.c +1 -1
- data/ext/hruby_sim/hruby_sim_tree_calc.c +8 -1
- data/ext/hruby_sim/hruby_sim_vcd.c +24 -7
- data/ext/hruby_sim/hruby_sim_vizualize.c +9 -1
- data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
- data/lib/HDLRuby/hdr_samples/constant_in_function.rb +3 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +3 -1
- data/lib/HDLRuby/hdr_samples/huge_rom.rb +1 -1
- data/lib/HDLRuby/hdr_samples/mei8.rb +11 -11
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +12 -12
- data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +4 -4
- data/lib/HDLRuby/hdr_samples/rom_nest.rb +1 -1
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +4 -4
- data/lib/HDLRuby/hdr_samples/struct.rb +44 -10
- data/lib/HDLRuby/hdr_samples/with_bram.rb +45 -0
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_casts.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_concat.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -2
- data/lib/HDLRuby/hdr_samples/with_def.rb +10 -3
- data/lib/HDLRuby/hdr_samples/with_define_operator.rb +44 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -12
- data/lib/HDLRuby/hdr_samples/with_init.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_leftright.rb +21 -0
- data/lib/HDLRuby/hdr_samples/with_reduce.rb +13 -13
- data/lib/HDLRuby/hdr_samples/with_ref_array.rb +6 -6
- data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
- data/lib/HDLRuby/hdr_samples/with_subsums.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_terminate.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_to_a.rb +10 -10
- data/lib/HDLRuby/hdr_samples/with_values.rb +3 -3
- data/lib/HDLRuby/hdrcc.rb +29 -3
- data/lib/HDLRuby/hdrlib.rb +1 -1
- data/lib/HDLRuby/hruby_bstr.rb +10 -5
- data/lib/HDLRuby/hruby_db.rb +2 -2
- data/lib/HDLRuby/hruby_high.rb +152 -47
- data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +189 -18
- data/lib/HDLRuby/hruby_low2c.rb +129 -54
- data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
- data/lib/HDLRuby/hruby_low2high.rb +86 -44
- data/lib/HDLRuby/hruby_low2seq.rb +26 -18
- data/lib/HDLRuby/hruby_low2sym.rb +14 -13
- data/lib/HDLRuby/hruby_low2vhd.rb +80 -44
- data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
- data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
- data/lib/HDLRuby/hruby_low_fix_types.rb +65 -32
- data/lib/HDLRuby/hruby_low_mutable.rb +83 -119
- data/lib/HDLRuby/hruby_low_resolve.rb +38 -30
- data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
- data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
- data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
- data/lib/HDLRuby/hruby_low_without_concat.rb +45 -19
- data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +32 -16
- data/lib/HDLRuby/hruby_low_without_select.rb +37 -24
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +280 -0
- data/lib/HDLRuby/hruby_rcsim.rb +158 -134
- data/lib/HDLRuby/hruby_rsim.rb +194 -20
- data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
- data/lib/HDLRuby/hruby_rsim_vcd.rb +125 -50
- data/lib/HDLRuby/hruby_values.rb +48 -33
- data/lib/HDLRuby/hruby_verilog.rb +90 -48
- data/lib/HDLRuby/soft/stacks.rb +219 -0
- data/lib/HDLRuby/std/bram.rb +26 -0
- data/lib/HDLRuby/std/clocks.rb +1 -1
- data/lib/HDLRuby/std/fixpoint.rb +2 -2
- data/lib/HDLRuby/std/fsm.rb +48 -11
- data/lib/HDLRuby/std/function_generator.rb +2 -2
- data/lib/HDLRuby/std/sequencer.rb +1857 -0
- data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
- data/lib/HDLRuby/std/std.rb +12 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/tuto/adder_sat_flags_vcd.png +0 -0
- data/tuto/addsub_vcd.png +0 -0
- data/tuto/alu_vcd.png +0 -0
- data/tuto/bit_pong_vcd.png +0 -0
- data/tuto/checksum_vcd.png +0 -0
- data/tuto/circuit_hdr.odg +0 -0
- data/tuto/circuit_hdr.png +0 -0
- data/tuto/circuit_hie.odg +0 -0
- data/tuto/circuit_hie.png +0 -0
- data/tuto/circuit_view.odg +0 -0
- data/tuto/circuit_view.png +0 -0
- data/tuto/clock_counter_vcd.png +0 -0
- data/tuto/counter_ext_vcd.png +0 -0
- data/tuto/fact_vcd.png +0 -0
- data/tuto/hw_flow.odg +0 -0
- data/tuto/hw_flow.png +0 -0
- data/tuto/maxxer_vcd.png +0 -0
- data/tuto/pingpong0_vcd.png +0 -0
- data/tuto/pingpong1_vcd.png +0 -0
- data/tuto/pingpong2_vcd.png +0 -0
- data/tuto/ram_vcd.png +0 -0
- data/tuto/serializer_vcd.png +0 -0
- data/tuto/sw_flow.odg +0 -0
- data/tuto/sw_flow.png +0 -0
- data/tuto/the_counter_vcd.png +0 -0
- data/tuto/tutorial_sw.html +2359 -0
- data/tuto/tutorial_sw.md +2684 -0
- data/tuto/tutorial_sw.pdf +0 -0
- data/tuto/tutorial_sw_jp.md +417 -0
- metadata +49 -3
- data/lib/HDLRuby/hdr_samples/sumprod.rb +0 -29
@@ -40,9 +40,9 @@ module HDLRuby::High
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return idstr
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end
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# Enhance the system type class with VCD support.
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class SystemT
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# Enhance the system type class with VCD support.
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## Initializes the displayer for generating a vcd on +vcdout+
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def show_init(vcdout)
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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#
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# Recurse on the signals.
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self.each_signal do |sig|
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sig.get_vars_with_fullname(vars_with_fullname)
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# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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end
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# Recurse on the scope.
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return self.scope.get_vars_with_fullname(vars_with_fullname)
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## Gets the VCD variables with their id string.
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def get_vars_with_idstr(vars_with_idstr = {})
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# Adds the signals of the interface of the system.
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# # Adds the signals of the interface of the system.
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# self.each_signal do |sig|
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# vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
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# end
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# Recurse on the signals.
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self.each_signal do |sig|
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sig.get_vars_with_idstr(vars_with_idstr)
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end
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# Recurse on the scope.
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return self.scope.get_vars_with_idstr(vars_with_idstr)
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vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
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# Shows the interface signals.
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self.each_signal do |sig|
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# vcdout << "#{
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vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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sig.show_hierarchy(vcdout)
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# # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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# vcdout << "$var wire #{sig.type.width} "
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# vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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# vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the scope.
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self.scope.show_hierarchy(vcdout)
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end
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##
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# Enhance the scope class with VCD support.
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class Scope
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# Enhance the scope class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# puts "show_hierarchy for scope=#{self}"
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end
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# Shows the inner signals.
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self.each_inner do |sig|
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# vcdout << "#{
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vcdout << "#{HDLRuby::High.
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vcdout << "#{HDLRuby::High.
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sig.show_hierarchy(vcdout)
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# # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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# vcdout << "$var wire #{sig.type.width} "
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# # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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# vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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# vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the behaviors' blocks
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self.each_behavior do |beh|
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# Adds the inner signals.
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# # Adds the inner signals.
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# self.each_inner do |sig|
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# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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# end
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# Recurse on the inner signals.
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self.each_inner do |sig|
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sig.get_vars_with_fullname(vars_with_fullname)
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# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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end
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self.each_behavior do |beh|
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## Gets the VCD variables with their id string.
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def get_vars_with_idstr(vars_with_idstr = {})
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# Adds the inner signals.
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# # Adds the inner signals.
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# self.each_inner do |sig|
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# vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
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# end
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self.each_inner do |sig|
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sig.get_vars_with_idstr(vars_with_idstr)
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end
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self.each_behavior do |beh|
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end
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module SimSignal
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# Enhance the signals class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# puts "show_hierarcy for signal=#{self.name}"
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if self.each_signal.any? then
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# The signal is hierarchical, recurse on the sub signals.
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vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
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self.each_signal { |sig| sig.show_hierarchy(vcdout) }
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vcdout << "$upscope $end\n"
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else
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# This is a signal to show.
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vcdout << "$var wire #{self.type.width} "
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vcdout << "#{HDLRuby::High.vcd_idstr(self)} "
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vcdout << "#{HDLRuby::High.vcd_name(self.name)} $end\n"
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end
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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if self.each_signal.any? then
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# There are sub signals, recurse on them.
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self.each_signal do |sig|
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sig.get_vars_with_fullname(vars_with_fullname)
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end
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else
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# No add the current signal.
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vars_with_fullname[self] = HDLRuby::High.vcd_name(self.fullname)
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end
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return vars_with_full_name
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end
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## Gets the VCD variables with their id string.
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def get_vars_with_idstr(vars_with_idstr = {})
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if self.each_signal.any? then
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# There are sub signals, recurse on them.
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self.each_signal do |sig|
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sig.get_vars_with_idstr(vars_with_idstr)
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end
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else
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vars_with_idstr[self] = HDLRuby::High.vcd_idstr(self)
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end
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return vars_with_idstr
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end
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end
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class Transmit
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# Enhance the Transmit class with VCD support.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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class TimeRepeat
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def show_hierarchy(vcdout)
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# Recurse on the statement.
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class TimeWait
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class Print
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# Enhance the Print class with VCD support.
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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## Module adding
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module BlockHierarchy
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def show_hierarchy(vcdout)
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self.each_inner do |sig|
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# # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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# # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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# vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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# vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the statements
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self.each_statement do |stmnt|
|
@@ -347,9 +415,14 @@ module HDLRuby::High
|
|
347
415
|
|
348
416
|
## Gets the VCD variables with their long name.
|
349
417
|
def get_vars_with_fullname(vars_with_fullname = {})
|
350
|
-
# Adds the inner signals.
|
418
|
+
# # Adds the inner signals.
|
419
|
+
# self.each_inner do |sig|
|
420
|
+
# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
|
421
|
+
# end
|
422
|
+
# Recurse on the inner signals.
|
351
423
|
self.each_inner do |sig|
|
352
|
-
|
424
|
+
sig.get_vars_with_fullname(vars_with_fullname)
|
425
|
+
# vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
|
353
426
|
end
|
354
427
|
# Recurse on the statements.
|
355
428
|
self.each_statement do |stmnt|
|
@@ -360,9 +433,13 @@ module HDLRuby::High
|
|
360
433
|
|
361
434
|
## Gets the VCD variables with their id string.
|
362
435
|
def get_vars_with_idstr(vars_with_idstr = {})
|
363
|
-
# Adds the inner signals.
|
436
|
+
# # Adds the inner signals.
|
437
|
+
# self.each_inner do |sig|
|
438
|
+
# vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
|
439
|
+
# end
|
440
|
+
# Recurse on the inner signals.
|
364
441
|
self.each_inner do |sig|
|
365
|
-
|
442
|
+
sif.get_vars_with_idstr(vars_with_idstr)
|
366
443
|
end
|
367
444
|
# Recurse on the statements.
|
368
445
|
self.each_statement do |stmnt|
|
@@ -373,23 +450,20 @@ module HDLRuby::High
|
|
373
450
|
end
|
374
451
|
|
375
452
|
|
376
|
-
##
|
377
|
-
# Enhance the block class with VCD support.
|
378
453
|
class Block
|
454
|
+
# Enhance the block class with VCD support.
|
379
455
|
include HDLRuby::High::BlockHierarchy
|
380
456
|
end
|
381
457
|
|
382
458
|
|
383
|
-
##
|
384
|
-
# Enhance the block class with VCD support.
|
385
459
|
class TimeBlock
|
460
|
+
# Enhance the block class with VCD support.
|
386
461
|
include HDLRuby::High::BlockHierarchy
|
387
462
|
end
|
388
463
|
|
389
464
|
|
390
|
-
##
|
391
|
-
# Enhance the if class with VCD support.
|
392
465
|
class If
|
466
|
+
# Enhance the if class with VCD support.
|
393
467
|
## Shows the hierarchy of the variables.
|
394
468
|
def show_hierarchy(vcdout)
|
395
469
|
# Recurse on the yes.
|
@@ -430,9 +504,9 @@ module HDLRuby::High
|
|
430
504
|
end
|
431
505
|
|
432
506
|
|
433
|
-
##
|
434
|
-
# Enhance the Case class with VCD support.
|
435
507
|
class Case
|
508
|
+
# Enhance the Case class with VCD support.
|
509
|
+
|
436
510
|
## Shows the hierarchy of the variables.
|
437
511
|
def show_hierarchy(vcdout)
|
438
512
|
# Recurse on each when.
|
@@ -466,9 +540,10 @@ module HDLRuby::High
|
|
466
540
|
end
|
467
541
|
end
|
468
542
|
|
469
|
-
|
470
|
-
# Enhance the TimeRepeat class with VCD support.
|
543
|
+
|
471
544
|
class TimeRepeat
|
545
|
+
# Enhance the TimeRepeat class with VCD support.
|
546
|
+
|
472
547
|
## Shows the hierarchy of the variables.
|
473
548
|
def show_hierarchy(vcdout)
|
474
549
|
# Recurse on the statement.
|
data/lib/HDLRuby/hruby_values.rb
CHANGED
@@ -13,6 +13,9 @@ module HDLRuby
|
|
13
13
|
|
14
14
|
# Truncs integer +val+ to +width+
|
15
15
|
def trunc(val,width)
|
16
|
+
if val.is_a?(BitString) then
|
17
|
+
return val[(width-1)..0]
|
18
|
+
end
|
16
19
|
if val.bit_length > width then
|
17
20
|
if val >= 0 then
|
18
21
|
# return val & (2**width-1)
|
@@ -38,8 +41,9 @@ module HDLRuby
|
|
38
41
|
unless val.to_value? then
|
39
42
|
# Not computable, use the former method that generates
|
40
43
|
# HDLRuby code.
|
41
|
-
return self.send(orig_operator(op),
|
44
|
+
return self.send(orig_operator(op),val)
|
42
45
|
end
|
46
|
+
val = val.to_value unless val.is_a?(Value)
|
43
47
|
# Handle Numeric op BitString case.
|
44
48
|
if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
|
45
49
|
if val.content.specified? then
|
@@ -52,7 +56,7 @@ module HDLRuby
|
|
52
56
|
else
|
53
57
|
# Generate the resulting content.
|
54
58
|
res_content = self.content.send(op,val.content)
|
55
|
-
# puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})"
|
59
|
+
# puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})"
|
56
60
|
end
|
57
61
|
res_type = self.type.resolve(val.type)
|
58
62
|
# # Adjust the result content size.
|
@@ -80,27 +84,29 @@ module HDLRuby
|
|
80
84
|
return self.send(orig_operator(op),val)
|
81
85
|
end
|
82
86
|
# Process left.
|
83
|
-
|
84
|
-
|
85
|
-
|
86
|
-
|
87
|
-
|
88
|
-
|
89
|
-
|
87
|
+
if left.is_a?(Value) then
|
88
|
+
left = left.content
|
89
|
+
if left.is_a?(BitString) && !left.specified? then
|
90
|
+
return self.class.new(self.type.base,
|
91
|
+
BitString::UNKNOWN.clone)
|
92
|
+
end
|
93
|
+
# left = left.to_i
|
94
|
+
left = self.trunc(left.to_i,val.first.type.width)
|
95
|
+
else
|
96
|
+
left = left.to_i
|
90
97
|
end
|
91
|
-
# left = left.to_i
|
92
|
-
left = self.trunc(left.to_i,val.first.type.width)
|
93
98
|
# Process right.
|
94
|
-
|
95
|
-
|
96
|
-
|
97
|
-
|
98
|
-
|
99
|
-
|
100
|
-
|
99
|
+
if right.is_a?(Value) then
|
100
|
+
right = right.content
|
101
|
+
if right.is_a?(BitString) && !right.specified? then
|
102
|
+
return self.class.new(self.type.base,
|
103
|
+
BitString::UNKNOWN.clone)
|
104
|
+
end
|
105
|
+
# right = right.to_i
|
106
|
+
right = self.trunc(right.to_i,val.last.type.width)
|
107
|
+
else
|
108
|
+
right = right.to_i
|
101
109
|
end
|
102
|
-
# right = right.to_i
|
103
|
-
right = self.trunc(right.to_i,val.last.type.width)
|
104
110
|
# Generate the resulting type.
|
105
111
|
res_type = self.type.base[(left-right+1).abs]
|
106
112
|
# Generate the resulting value.
|
@@ -124,18 +130,16 @@ module HDLRuby
|
|
124
130
|
return self.send(orig_operator(op),val)
|
125
131
|
end
|
126
132
|
# Process val.
|
127
|
-
|
128
|
-
|
129
|
-
|
130
|
-
|
133
|
+
if val.is_a?(Value) then
|
134
|
+
index = val.content
|
135
|
+
if index.is_a?(BitString) && !index.specified? then
|
136
|
+
return self.class.new(self.type.base,
|
137
|
+
BitString::UNKNOWN.clone)
|
138
|
+
end
|
139
|
+
index = self.trunc(index.to_i,val.type.width)
|
140
|
+
else
|
141
|
+
index = val.to_i
|
131
142
|
end
|
132
|
-
index = self.trunc(index.to_i,val.type.width)
|
133
|
-
# index = index.to_i
|
134
|
-
# if index >= self.type.size then
|
135
|
-
# # puts "index=#{index}"
|
136
|
-
# index %= self.type.size
|
137
|
-
# # puts "now index=#{index}"
|
138
|
-
# end
|
139
143
|
# Generate the resulting type.
|
140
144
|
res_type = self.type.base
|
141
145
|
# Generate the resulting value.
|
@@ -144,9 +148,11 @@ module HDLRuby
|
|
144
148
|
if self.content.is_a?(BitString) then
|
145
149
|
res_content = self.content[index*width..(index+1)*width-1]
|
146
150
|
else
|
151
|
+
# puts "self.content=#{self.content} index=#{index}"
|
147
152
|
sh = index*width
|
148
153
|
mask = (-1 << sh) & ~(-1 << (index+1)*width)
|
149
154
|
res_content = (self.content & mask) >> sh
|
155
|
+
# puts "res_content=#{res_content}"
|
150
156
|
end
|
151
157
|
# Return the resulting value.
|
152
158
|
return self.class.new(res_type,res_content)
|
@@ -236,7 +242,7 @@ module HDLRuby
|
|
236
242
|
# Generate the resulting type.
|
237
243
|
res_type = self.type
|
238
244
|
# Generate the resulting content.
|
239
|
-
# puts "op=#{op} content=#{content.to_s}"
|
245
|
+
# puts "op=#{op} content=#{content.to_s} width=#{res_type.width}"
|
240
246
|
res_content = self.content.send(op)
|
241
247
|
# puts "res_content=#{res_content}"
|
242
248
|
# Return the resulting value.
|
@@ -275,6 +281,9 @@ module HDLRuby
|
|
275
281
|
res_content.positive!
|
276
282
|
end
|
277
283
|
end
|
284
|
+
if type.signed && res_content.is_a?(Numeric) && res_content >= (1 << (type.width-1)) then
|
285
|
+
res_content = (-1 << type.width) + res_content
|
286
|
+
end
|
278
287
|
# # truncs to the right size if necessary.
|
279
288
|
# if res_content.is_a?(BitString) then
|
280
289
|
# res_content.trunc!(type.width)
|
@@ -308,7 +317,7 @@ module HDLRuby
|
|
308
317
|
break if count == width
|
309
318
|
end
|
310
319
|
if count < width then
|
311
|
-
res_content.concat(res_content[-1] * (width-count))
|
320
|
+
res_content.concat([res_content[-1]] * (width-count))
|
312
321
|
end
|
313
322
|
else
|
314
323
|
width.times do |p|
|
@@ -401,6 +410,12 @@ module HDLRuby
|
|
401
410
|
end
|
402
411
|
end
|
403
412
|
|
413
|
+
# Tell if the value is high impedance.
|
414
|
+
def impedence?
|
415
|
+
return false unless @content.is_a?(BitString)
|
416
|
+
return @content.raw_content.include?(2)
|
417
|
+
end
|
418
|
+
|
404
419
|
## Converts the value to a string of the right size.
|
405
420
|
def to_vstr
|
406
421
|
if self.content.is_a?(Numeric) then
|