HDLRuby 2.11.11 → 3.0.0

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Files changed (119) hide show
  1. checksums.yaml +4 -4
  2. data/README.html +3274 -0
  3. data/README.md +608 -99
  4. data/ext/hruby_sim/hruby_rcsim_build.c +27 -0
  5. data/ext/hruby_sim/hruby_sim.h +3 -0
  6. data/ext/hruby_sim/hruby_sim_calc.c +2 -0
  7. data/ext/hruby_sim/hruby_sim_core.c +17 -5
  8. data/ext/hruby_sim/hruby_sim_stack_calc.c +1 -1
  9. data/ext/hruby_sim/hruby_sim_tree_calc.c +8 -1
  10. data/ext/hruby_sim/hruby_sim_vcd.c +24 -7
  11. data/ext/hruby_sim/hruby_sim_vizualize.c +9 -1
  12. data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
  13. data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
  14. data/lib/HDLRuby/hdr_samples/constant_in_function.rb +3 -1
  15. data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +3 -1
  16. data/lib/HDLRuby/hdr_samples/huge_rom.rb +1 -1
  17. data/lib/HDLRuby/hdr_samples/mei8.rb +11 -11
  18. data/lib/HDLRuby/hdr_samples/mei8_bench.rb +12 -12
  19. data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +4 -4
  20. data/lib/HDLRuby/hdr_samples/rom_nest.rb +1 -1
  21. data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +4 -4
  22. data/lib/HDLRuby/hdr_samples/struct.rb +44 -10
  23. data/lib/HDLRuby/hdr_samples/with_bram.rb +45 -0
  24. data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
  25. data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
  26. data/lib/HDLRuby/hdr_samples/with_casts.rb +3 -3
  27. data/lib/HDLRuby/hdr_samples/with_concat.rb +6 -6
  28. data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +2 -2
  29. data/lib/HDLRuby/hdr_samples/with_def.rb +10 -3
  30. data/lib/HDLRuby/hdr_samples/with_define_operator.rb +44 -0
  31. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -12
  32. data/lib/HDLRuby/hdr_samples/with_init.rb +3 -3
  33. data/lib/HDLRuby/hdr_samples/with_leftright.rb +21 -0
  34. data/lib/HDLRuby/hdr_samples/with_reduce.rb +13 -13
  35. data/lib/HDLRuby/hdr_samples/with_ref_array.rb +6 -6
  36. data/lib/HDLRuby/hdr_samples/with_register_stack.rb +150 -0
  37. data/lib/HDLRuby/hdr_samples/with_sequencer.rb +190 -0
  38. data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
  39. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +405 -0
  40. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
  41. data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
  42. data/lib/HDLRuby/hdr_samples/with_subsums.rb +3 -3
  43. data/lib/HDLRuby/hdr_samples/with_terminate.rb +3 -3
  44. data/lib/HDLRuby/hdr_samples/with_to_a.rb +10 -10
  45. data/lib/HDLRuby/hdr_samples/with_values.rb +3 -3
  46. data/lib/HDLRuby/hdrcc.rb +29 -3
  47. data/lib/HDLRuby/hdrlib.rb +1 -1
  48. data/lib/HDLRuby/hruby_bstr.rb +10 -5
  49. data/lib/HDLRuby/hruby_db.rb +2 -2
  50. data/lib/HDLRuby/hruby_high.rb +152 -47
  51. data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
  52. data/lib/HDLRuby/hruby_low.rb +189 -18
  53. data/lib/HDLRuby/hruby_low2c.rb +129 -54
  54. data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
  55. data/lib/HDLRuby/hruby_low2high.rb +86 -44
  56. data/lib/HDLRuby/hruby_low2seq.rb +26 -18
  57. data/lib/HDLRuby/hruby_low2sym.rb +14 -13
  58. data/lib/HDLRuby/hruby_low2vhd.rb +80 -44
  59. data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
  60. data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
  61. data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
  62. data/lib/HDLRuby/hruby_low_fix_types.rb +65 -32
  63. data/lib/HDLRuby/hruby_low_mutable.rb +83 -119
  64. data/lib/HDLRuby/hruby_low_resolve.rb +38 -30
  65. data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
  66. data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
  67. data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
  68. data/lib/HDLRuby/hruby_low_without_concat.rb +45 -19
  69. data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
  70. data/lib/HDLRuby/hruby_low_without_parinseq.rb +32 -16
  71. data/lib/HDLRuby/hruby_low_without_select.rb +37 -24
  72. data/lib/HDLRuby/hruby_low_without_subsignals.rb +280 -0
  73. data/lib/HDLRuby/hruby_rcsim.rb +158 -134
  74. data/lib/HDLRuby/hruby_rsim.rb +194 -20
  75. data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
  76. data/lib/HDLRuby/hruby_rsim_vcd.rb +125 -50
  77. data/lib/HDLRuby/hruby_values.rb +48 -33
  78. data/lib/HDLRuby/hruby_verilog.rb +90 -48
  79. data/lib/HDLRuby/soft/stacks.rb +219 -0
  80. data/lib/HDLRuby/std/bram.rb +26 -0
  81. data/lib/HDLRuby/std/clocks.rb +1 -1
  82. data/lib/HDLRuby/std/fixpoint.rb +2 -2
  83. data/lib/HDLRuby/std/fsm.rb +48 -11
  84. data/lib/HDLRuby/std/function_generator.rb +2 -2
  85. data/lib/HDLRuby/std/sequencer.rb +1857 -0
  86. data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
  87. data/lib/HDLRuby/std/std.rb +12 -0
  88. data/lib/HDLRuby/version.rb +1 -1
  89. data/tuto/adder_sat_flags_vcd.png +0 -0
  90. data/tuto/addsub_vcd.png +0 -0
  91. data/tuto/alu_vcd.png +0 -0
  92. data/tuto/bit_pong_vcd.png +0 -0
  93. data/tuto/checksum_vcd.png +0 -0
  94. data/tuto/circuit_hdr.odg +0 -0
  95. data/tuto/circuit_hdr.png +0 -0
  96. data/tuto/circuit_hie.odg +0 -0
  97. data/tuto/circuit_hie.png +0 -0
  98. data/tuto/circuit_view.odg +0 -0
  99. data/tuto/circuit_view.png +0 -0
  100. data/tuto/clock_counter_vcd.png +0 -0
  101. data/tuto/counter_ext_vcd.png +0 -0
  102. data/tuto/fact_vcd.png +0 -0
  103. data/tuto/hw_flow.odg +0 -0
  104. data/tuto/hw_flow.png +0 -0
  105. data/tuto/maxxer_vcd.png +0 -0
  106. data/tuto/pingpong0_vcd.png +0 -0
  107. data/tuto/pingpong1_vcd.png +0 -0
  108. data/tuto/pingpong2_vcd.png +0 -0
  109. data/tuto/ram_vcd.png +0 -0
  110. data/tuto/serializer_vcd.png +0 -0
  111. data/tuto/sw_flow.odg +0 -0
  112. data/tuto/sw_flow.png +0 -0
  113. data/tuto/the_counter_vcd.png +0 -0
  114. data/tuto/tutorial_sw.html +2359 -0
  115. data/tuto/tutorial_sw.md +2684 -0
  116. data/tuto/tutorial_sw.pdf +0 -0
  117. data/tuto/tutorial_sw_jp.md +417 -0
  118. metadata +49 -3
  119. data/lib/HDLRuby/hdr_samples/sumprod.rb +0 -29
@@ -0,0 +1,400 @@
1
+ require 'std/sequencer'
2
+
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+ module HDLRuby::High::Std
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+
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+ ##
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+ # Standard HDLRuby::High library: sequencer synchronizer generator.
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+ # The idea is to be able to write sw-like sequential code.
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+ #
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+ ########################################################################
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+
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+
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+
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+ # Describes a signal with shared write.
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+ class SharedSignalI
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+
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+ # Create a new shared signal of type +typ+.
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+ # NOTE: for now the arbitration is the priority in order of write access
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+ # declaration.
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+ def initialize(typ, name, default_value = 0)
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+ # Process the arguments.
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+ typ = typ.to_type
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+ @type = typ
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+ name = name.to_sym
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+ @name = name
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+ @default_value = default_value
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+ # Create the name of the access process.
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+ @name_sub = HDLRuby.uniq_name(:"#{name}_sub")
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+ this = self
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+ # Register the shared signal.
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+ HDLRuby::High.space_reg(name) { this }
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+ # Create the output value and selection of the signal.
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+ value_out = nil
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+ select = nil
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+ HDLRuby::High.cur_system.open do
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+ value_out = typ.inner(HDLRuby.uniq_name(:"#{name}_out"))
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+ select = [1].inner(HDLRuby.uniq_name(:"#{name}_select") => 0)
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+ end
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+ @value_out = value_out
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+ @select = select
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+ # First no access point.
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+ @size = 0
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+ # Create the input values.
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+ values_in = nil
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+ HDLRuby::High.cur_system.open do
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+ values_in = typ[-1].inner(HDLRuby.uniq_name(:"#{name}_in"))
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+ end
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+ @values_in = values_in
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+ # The set of access points by sequencer.
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+ @points = { }
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+ end
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+
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+ # Adds an access point.
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+ def add_point
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+ # Maybe a point already exist for current sequencer.
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+ sequ = SequencerT.current
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+ point = @points[sequ]
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+ return @values_in[point] if point # Yes, return it.
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+ # No, do create a new one.
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+ point = @points[sequ] = @size
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+ # Resize the flag and value vectors.
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+ @size += 1
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+ size = @size
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+ @values_in.type.instance_variable_set(:@range,0..size-1)
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+ @select.type.instance_variable_set(:@range,(size-1).width-1..0)
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+ # (Re)Generate the access arbitrer.
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+ name_sub = @name_sub
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+ values_in = @values_in
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+ value_out = @value_out
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+ select = @select
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+ default_value = @default_value
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+ # The access arbitrer.
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+ HDLRuby::High.cur_system.open do
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+ sub(name_sub) do
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+ par do
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+ hcase(select)
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+ size.times do |i|
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+ hwhen(i) { value_out <= values_in[i] }
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+ end
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+ helse { value_out <= default_value }
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+ end
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+ end
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+ end
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+ # Return the current access point.
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+ return values_in[size-1]
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+ end
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+
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+ # Write access code generation.
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+ def <=(expr)
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+ # Create a new access point.
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+ value_in = self.add_point
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+ # Actually implement the access.
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+ value_in <= expr.to_expr
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+ return self
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+ end
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+
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+ # Read access code generation:
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+ # actually hidden in the conversion to expression.
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+ def to_expr
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+ # Return the resulting value.
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+ @value_out
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+ end
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+
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+ # Selection of the output value code generation.
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+ # +arg+ can be the index or directly the selected sequencer.
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+ # If no arg is given, return access to the selection signal direction.
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+ def select(arg = nil)
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+ return @select unless arg
108
+ if arg.is_a?(SequencerT) then
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+ pt = @points[arg]
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+ @select <= @points[arg] if pt
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+ else
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+ @select <= arg
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+ end
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+ end
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+
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+ # For to_expr an all the other methods.
117
+ def method_missing(m, *args, &ruby_block)
118
+ self.to_expr.send(m,*args,&ruby_block)
119
+ end
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+
121
+ end
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+
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+
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+ # Describes an arbiter for a shared signal.
125
+ class ArbiterT
126
+
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+ # Create a new arbitrer named +name+ for shared signals +sigs+.
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+ def initialize(name,*sigs)
129
+ # Sets the name.
130
+ name = name.to_sym
131
+ @name = name
132
+ # Register the signals.
133
+ @signals = []
134
+ # Adds the signals.
135
+ self.(*sigs)
136
+ # Create the set of access points.
137
+ @size = 0
138
+ @points = {}
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+ # Create the acquire/release bit vector.
140
+ acquires = nil
141
+ HDLRuby::High.cur_system.open do
142
+ acquires = [1].inner(HDLRuby.uniq_name(:"#{name}_acq") => 0)
143
+ end
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+ @acquires = acquires
145
+ # Register the arbiter.
146
+ this = self
147
+ HDLRuby::High.space_reg(name) { this }
148
+ end
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+
150
+ # Adds the signals.
151
+ def call(*sigs)
152
+ sigs.each do |sig|
153
+ unless sig.is_a?(SharedSignalI) then
154
+ raise "An arbitrer only works on a shared signal, not a #{sig.class}"
155
+ end
156
+ @signals << sig
157
+ end
158
+ end
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+
160
+ # Adds an access point.
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+ def add_point
162
+ # Maybe a point already exist for current sequencer.
163
+ sequ = SequencerT.current
164
+ point = @points[sequ]
165
+ return point if point
166
+ # No add it.
167
+ point = @size
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+ @points[sequ] = point
169
+ @size += 1
170
+ # Resize the acquire vector according to the new point.
171
+ @acquires.type.instance_variable_set(:@range,0..point)
172
+ return point
173
+ end
174
+
175
+ # Shared signal selection code generation.
176
+ def select(point)
177
+ @signals.each do |signal|
178
+ signal.select(@points.key(point))
179
+ end
180
+ end
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+
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+ # Arbiter access code generation: 1 for acquire and 0 for release.
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+ def <=(val)
184
+ # Add an access point if required.
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+ point = self.add_point
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+ # Do the access.
187
+ @acquires[point] <= val
188
+ end
189
+ end
190
+
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+
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+ # Describes a priority-based arbiter.
193
+ class PriorityArbiterT < ArbiterT
194
+
195
+ # Create a new priority-based arbiter named +name+ with priority table
196
+ # +tbl+ or priority algorithm +ruby_block+ for shared signals +sigs+.
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+ def initialize(name, tbl = nil, *sigs, &ruby_block)
198
+ super(name,*sigs)
199
+ # Set the priority policy.
200
+ self.policy(tbl,&ruby_block)
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+ # Create the name of the access procedure sub.
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+ @name_sub = HDLRuby.uniq_name(:"#{name}_sub")
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+ end
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+
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+ # Set the policy either using a priority table +tbl+ by directly
206
+ # providing the priority algorithm through +ruby_block+
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+ def policy(tbl = nil, &ruby_block)
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+ # By default the priority table is the points declaration order.
209
+ if !tbl && ruby_block == nil then
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+ @priority = proc { |acquires,i| acquires[i] == 1 }
211
+ elsif tbl then
212
+ @priority = proc do |acquires,i|
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+ pri = tbl[i]
214
+ raise "Invalid priority index: #{i}" unless pri
215
+ acquires[pri] == 1
216
+ end
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+ else
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+ @priority = ruby_block
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+ end
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+ end
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+
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+ # Add a point.
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+ def add_point
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+ point = super # The point is added by the parent class.
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+ # Update the access procedure.
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+ name_sub = @name_sub
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+ this = self
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+ size = @size
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+ acquires = @acquires
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+ priority = @priority
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+ HDLRuby::High.cur_system.open do
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+ sub(name_sub) do
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+ seq do
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+ if(size == 1) then
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+ # Anyway, only one accesser.
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+ this.select(0)
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+ else
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+ hif(priority.(acquires,0)) do
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+ this.select(0)
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+ end
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+ (1..size-1).each do |i|
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+ helsif(priority.(acquires,i)) do
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+ this.select(i)
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+ end
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+ end
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+ helse do # No acquire at all, select the first point.
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+ this.select(0)
248
+ end
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+ end
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+ end
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+ end
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+ end
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+ return point
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+ end
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+ end
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+
257
+
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+ # Describes priority-based monitor.
259
+ class PriorityMonitorT < PriorityArbiterT
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+
261
+ # Create a new priority-based arbiter named +name+ with priority table
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+ # +tbl+ or priority algorithm +ruby_block+ for shared signals +sigs+.
263
+ def initialize(name, tbl = nil, *sigs, &ruby_block)
264
+ super(name,tbl,*sigs,&ruby_block)
265
+ # Declare the current selected point.
266
+ selected_point = nil
267
+ name = @name
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+ HDLRuby::High.cur_system.open do
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+ selected_point = [1].inner(HDLRuby.uniq_name(:"#{name}_selected"))
270
+ end
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+ @selected_point = selected_point
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+ end
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+
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+ # Add a point.
275
+ def add_point
276
+ # Redefine to update the size of @selected_point.
277
+ point = super
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+ @selected_point.type.instance_variable_set(:@range,(@size-1).width-1..0)
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+ return point
280
+ end
281
+
282
+ # Shared signal selection code generation.
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+ def select(point)
284
+ # Redefine to remember which point is selected.
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+ super(point)
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+ @selected_point <= point
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+ end
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+
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+ # # Arbiter access code generation: 1 for acquire and 0 for release.
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+ # def <=(val)
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+ # # Fully redefine to lock until selected if acquiring.
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+ # # Add an access point if required.
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+ # point = self.add_point
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+ # # Do the access.
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+ # res = (@acquires[point] <= val)
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+ # selected_point = @selected_point
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+ # # Lock until not selected.
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+ # if val.respond_to?(:to_i) then
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+ # if val.to_i == 1 then
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+ # SequencerT.current.swhile(selected_point != point)
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+ # end
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+ # else
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+ # SequencerT.current.swhile((val.to_expr == 1) & (selected_point != point))
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+ # end
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+ # return res
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+ # end
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+
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+ # Arbiter access code generation: 1 for acquire and 0 for release.
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+ def <=(val)
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+ raise "For monitors, you must use the methods lock and unlock."
311
+ end
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+
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+ # Monitor lock code generation
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+ def lock
315
+ # Fully redefine to lock until selected if acquiring.
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+ # Add an access point if required.
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+ point = self.add_point
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+ # Do the access.
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+ res = (@acquires[point] <= 1)
320
+ selected_point = @selected_point
321
+ # Lock until not selected.
322
+ SequencerT.current.swhile(selected_point != point)
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+ return res
324
+ end
325
+
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+ # Monitor unlock code generation
327
+ def unlock
328
+ # Fully redefine to lock until selected if acquiring.
329
+ # Add an access point if required.
330
+ point = self.add_point
331
+ # Do the access.
332
+ res = (@acquires[point] <= 0)
333
+ selected_point = @selected_point
334
+ return res
335
+ end
336
+ end
337
+
338
+
339
+ # Declares an arbiter named +name+ with priority table +tbl+ or priority
340
+ # procedure +rubyblock+.
341
+ def arbiter(name,tbl = nil, &ruby_block)
342
+ return PriorityArbiterT.new(name,tbl,&ruby_block)
343
+ end
344
+
345
+ # Declares a monitor named +name+ with priority table +tbl+ or priority
346
+ # procedure +rubyblock+.
347
+ def monitor(name,tbl = nil, &ruby_block)
348
+ return PriorityMonitorT.new(name,tbl,&ruby_block)
349
+ end
350
+
351
+
352
+
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+
354
+ # Enhance the Htype module for creating a shared signal.
355
+ module HDLRuby::High::Htype
356
+
357
+ # Create new shared signals from +args+.
358
+ # +args+ can be a name of list of names or a hash associating names to
359
+ # default values.
360
+ def shared(*args)
361
+ # # Process the arguments.
362
+ # Create the shared signal.
363
+ sig = nil
364
+ args.each do |arg|
365
+ if arg.is_a?(Hash) then
366
+ arg.each do |k,v|
367
+ sig = SharedSignalI.new(self,k,v)
368
+ end
369
+ else
370
+ sig = SharedSignalI.new(self,arg)
371
+ end
372
+ end
373
+ return sig
374
+ end
375
+ end
376
+
377
+
378
+ class ::Array
379
+ # Enhance the Array type for creating shared signals.
380
+
381
+ # Create new shared signals from +args+.
382
+ def shared(*names)
383
+ return self.to_type.shared(*names)
384
+ end
385
+ end
386
+
387
+
388
+ class ::Hash
389
+ # Enhance the Struct type for creating shared signals.
390
+
391
+ # Create new shared signals from +args+.
392
+ def shared(*names)
393
+ return self.to_type.shared(*names)
394
+ end
395
+ end
396
+
397
+
398
+
399
+
400
+ end
@@ -0,0 +1,12 @@
1
+
2
+ ##
3
+ # Standard HDLRuby::High library: all the stable functionalities.
4
+ #
5
+ ########################################################################
6
+
7
+ require 'std/clocks.rb'
8
+ require 'std/fixpoint.rb'
9
+ require 'std/decoder.rb'
10
+ require 'std/fsm.rb'
11
+ require 'std/sequencer.rb'
12
+ require 'std/sequencer_sync.rb'
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.11.11"
2
+ VERSION = "3.0.0"
3
3
  end
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