switchboard-hw 0.3.0__cp314-cp314-macosx_11_0_arm64.whl

switchboard/deps/verilog_axi.py

@@ -0,0 +1,23 @@
+from siliconcompiler import Design
+
+
+class VerilogAxi(Design):
+    def __init__(self):
+        super().__init__('verilog_axis')
+
+        self.set_dataroot(
+            name="verilog_axis",
+            path="git+https://github.com/alexforencich/verilog-axis.git@master",
+            tag="25912d48fec2abbf3565bbefe402c1cff99fe470"
+        )
+
+        path = "rtl"
+
+        files = [
+            f"{path}/arbiter.v",
+        ]
+
+        with self.active_fileset('rtl'):
+            for item in files:
+                self.add_file(item)
+

switchboard/dpi/switchboard_dpi.cc

@@ -0,0 +1,119 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+#include <assert.h>
+#include <chrono>
+#include <memory>
+#include <vector>
+
+#include "svdpi.h"
+#include "switchboard.hpp"
+
+// function definitions
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern void pi_sb_rx_init(int* id, const char* uri, int width);
+extern void pi_sb_tx_init(int* id, const char* uri, int width);
+extern void pi_sb_recv(int id, svBitVecVal* rdata, svBitVecVal* rdest, svBit* rlast, int* success);
+extern void pi_sb_send(int id, const svBitVecVal* sdata, const svBitVecVal* sdest, svBit slast,
+    int* success);
+extern void pi_time_taken(double* t);
+#ifdef __cplusplus
+}
+#endif
+
+static std::vector<std::unique_ptr<SBRX>> rxconn;
+static std::vector<std::unique_ptr<SBTX>> txconn;
+static std::vector<int> rxwidth;
+static std::vector<int> txwidth;
+
+void pi_sb_rx_init(int* id, const char* uri, int width) {
+    rxconn.push_back(std::unique_ptr<SBRX>(new SBRX()));
+    rxconn.back()->init(uri);
+
+    // record the width of this connection
+    rxwidth.push_back(width);
+
+    // assign the ID of this connection
+    *id = rxconn.size() - 1;
+}
+
+void pi_sb_tx_init(int* id, const char* uri, int width) {
+    txconn.push_back(std::unique_ptr<SBTX>(new SBTX()));
+    txconn.back()->init(uri);
+
+    // record the width of this connection
+    txwidth.push_back(width);
+
+    // assign the ID of this connection
+    *id = txconn.size() - 1;
+}
+
+void pi_sb_recv(int id, svBitVecVal* rdata, svBitVecVal* rdest, svBit* rlast, int* success) {
+    // make sure this is a valid id
+    assert(id < rxconn.size());
+
+    // try to receive an inbound packet
+    sb_packet p;
+    if (rxconn[id]->recv(p)) {
+        memcpy(rdata, p.data, rxwidth[id]);
+        *rdest = p.destination;
+        *rlast = p.last ? 1 : 0;
+        *success = 1;
+    } else {
+        *success = 0;
+    }
+}
+
+void pi_sb_send(int id, const svBitVecVal* sdata, const svBitVecVal* sdest, svBit slast,
+    int* success) {
+    // make sure this is a valid id
+    assert(id < txconn.size());
+
+    // form the outbound packet
+    sb_packet p;
+    memcpy(p.data, sdata, txwidth[id]);
+    p.destination = *sdest;
+    p.last = slast;
+
+    // try to send the packet
+    if (txconn[id]->send(p)) {
+        *success = 1;
+    } else {
+        *success = 0;
+    }
+}
+
+void pi_time_taken(double* t) {
+    static std::chrono::steady_clock::time_point start_time;
+    static std::chrono::steady_clock::time_point stop_time;
+
+    // compute time taken in seconds
+    stop_time = std::chrono::steady_clock::now();
+    *t = 1.0e-6 *
+         (std::chrono::duration_cast<std::chrono::microseconds>(stop_time - start_time).count());
+    start_time = std::chrono::steady_clock::now();
+}
+
+void pi_start_delay(double value) {
+    // WARNING: not tested yet since Icarus Verilog uses VPI and Verilator
+    // uses start_delay in main(), not through DPI
+    start_delay(value);
+}
+
+void pi_max_rate_tick(svBitVecVal* t_us_vec, svBitVecVal* min_period_us_vec) {
+    // WARNING: not tested yet since Icarus Verilog uses VPI and Verilator
+    // uses max_rate_tick in main(), not through DPI
+
+    // retrieve the previous timestamp and minimum period
+    long t_us, min_period_us;
+    memcpy(&t_us, t_us_vec, 8);
+    memcpy(&min_period_us, min_period_us_vec, 8);
+
+    // call the underlying switchboard function
+    max_rate_tick(t_us, min_period_us);
+
+    // store the new timestamp
+    memcpy(t_us_vec, &t_us, 8);
+}

switchboard/dpi/switchboard_dpi.py

@@ -0,0 +1,13 @@
+from siliconcompiler import Design
+
+from switchboard import sb_path
+
+
+class SwitchboardDPI(Design):
+    def __init__(self):
+        super().__init__("switchboard_dpi")
+
+        self.set_dataroot('localroot', sb_path() / "dpi")
+
+        with self.active_fileset('sim'):
+            self.add_file("switchboard_dpi.cc")

switchboard/dpi/xyce_dpi.cc

@@ -0,0 +1,43 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+#include "svdpi.h"
+
+#include <memory>
+#include <string>
+#include <vector>
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "xyce.hpp"
+
+// function definitions
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern void pi_sb_xyce_init(int* id, char* file);
+extern void pi_sb_xyce_put(int id, char* name, double time, double value);
+extern void pi_sb_xyce_get(int id, char* name, double time, double* val);
+#ifdef __cplusplus
+}
+#endif
+
+static std::vector<std::unique_ptr<XyceIntf>> xyceIntfs;
+
+void pi_sb_xyce_init(int* id, char* file) {
+    // add a new Xyce interface
+    xyceIntfs.push_back(std::unique_ptr<XyceIntf>(new XyceIntf()));
+    xyceIntfs.back()->init(std::string(file));
+
+    // set ID
+    *id = xyceIntfs.size() - 1;
+}
+
+void pi_sb_xyce_put(int id, char* name, double time, double value) {
+    xyceIntfs[id]->put(std::string(name), time, value);
+}
+
+void pi_sb_xyce_get(int id, char* name, double time, double* value) {
+    xyceIntfs[id]->get(std::string(name), time, value);
+}

switchboard/gpio.py

@@ -0,0 +1,108 @@
+# Copyright (c) 2024 Zero ASIC Corporation
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+import numpy as np
+from .bitvector import BitVector
+
+
+class UmiGpioInput:
+    def __init__(self, width, dstaddr, srcaddr, max_bytes, umi):
+        self.width = width
+        self.dstaddr = dstaddr
+        self.srcaddr = srcaddr
+        self.max_bytes = max_bytes
+        self.umi = umi
+
+    def _read(self):
+        # determine the number of bytes to read
+        nbytes = (self.width // 8)
+        if (self.width % 8) != 0:
+            nbytes += 1
+
+        # read the bytes
+        return BitVector.frombytes(
+            self.umi.read(
+                addr=self.dstaddr,
+                num_or_dtype=nbytes,
+                dtype=np.uint8,
+                srcaddr=self.srcaddr,
+                max_bytes=self.max_bytes
+            )
+        )
+
+    def __str__(self):
+        return str(self._read())
+
+    def __int__(self):
+        return int(self[:])
+
+    def __getitem__(self, key):
+        bv = self._read()
+        return bv.__getitem__(key=key)
+
+
+class UmiGpioOutput:
+    def __init__(self, width, init, dstaddr, srcaddr, posted, max_bytes, umi):
+        self.width = width
+        self.dstaddr = dstaddr
+        self.srcaddr = srcaddr
+        self.posted = posted
+        self.max_bytes = max_bytes
+        self.umi = umi
+
+        self.bv = BitVector(init)
+
+        if init is not None:
+            self._write()
+
+    def _write(self):
+        # determine the number of bytes to write
+        nbytes = (self.width // 8)
+        if (self.width % 8) != 0:
+            nbytes += 1
+
+        # write the bytes
+        self.umi.write(
+            addr=self.dstaddr,
+            data=self.bv.tobytes(n=nbytes),
+            srcaddr=self.srcaddr,
+            max_bytes=self.max_bytes,
+            posted=self.posted
+        )
+
+    def __setitem__(self, key, value):
+        self.bv.__setitem__(key=key, value=value)
+        self._write()
+
+    # read functions provided for convenience
+
+    def __str__(self):
+        return str(self.bv)
+
+    def __int__(self):
+        return int(self[:])
+
+    def __getitem__(self, key):
+        return self.bv.__getitem__(key=key)
+
+
+class UmiGpio(object):
+    def __init__(self, iwidth, owidth, init, dstaddr, srcaddr, posted, max_bytes, umi):
+
+        self.i = UmiGpioInput(
+            width=iwidth,
+            dstaddr=dstaddr,
+            srcaddr=srcaddr,
+            max_bytes=max_bytes,
+            umi=umi
+        )
+
+        self.o = UmiGpioOutput(
+            width=owidth,
+            init=init,
+            dstaddr=dstaddr,
+            srcaddr=srcaddr,
+            posted=posted,
+            max_bytes=max_bytes,
+            umi=umi
+        )

switchboard/icarus.py

@@ -0,0 +1,85 @@
+# Utilities for working with Icarus Verilog
+
+# Copyright (c) 2024 Zero ASIC Corporation
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+# TODO: replace with SiliconCompiler functionality
+
+from typing import Union, List
+from pathlib import Path
+
+from .util import plusargs_to_args, binary_run
+from .switchboard import path as sb_path
+from subprocess import check_output, STDOUT, CalledProcessError
+
+
+def run(command: list, cwd: str = None) -> str:
+    return check_output(command, cwd=cwd, stderr=STDOUT).decode()
+
+
+def icarus_build_vpi(
+    cwd: str = None,
+    name: str = 'switchboard',
+    cincludes: List[str] = None,
+    ldflags: List[str] = None
+) -> str:
+    if cincludes is None:
+        cincludes = []
+
+    if ldflags is None:
+        ldflags = []
+
+    sbdir = sb_path()
+    incdirs = cincludes + [f'{sbdir}/cpp']
+
+    cmd = []
+    cmd += ['iverilog-vpi']
+    cmd += [f'-I{incdir}' for incdir in incdirs]
+    cmd += ldflags
+    cmd += [str(sbdir / 'vpi' / f'{name}_vpi.cc')]
+
+    try:
+        run(cmd, cwd)
+    except CalledProcessError as e:
+        print(e.output)
+        raise
+
+
+def icarus_find_vpi(cwd: Union[str, Path] = None, name: str = 'switchboard') -> Path:
+    path = Path(f'{name}_vpi.vpi')
+
+    if cwd is not None:
+        path = Path(cwd) / path
+
+    if path.exists():
+        return path
+    else:
+        return None
+
+
+def icarus_run(vvp, plusargs=None, modules=None, extra_args=None, **kwargs):
+    args = []
+
+    args += ['-n']
+
+    mdirs = set()
+
+    if modules is not None:
+        if not isinstance(modules, list):
+            raise TypeError('modules must be a list')
+        for module in modules:
+            mdirs.add(str(Path(module.resolve().parent)))
+            args += ['-m', Path(module).stem]
+
+    for mdir in mdirs:
+        args += [f'-M{mdir}']
+
+    args += [vvp]
+    args += plusargs_to_args(plusargs)
+
+    if extra_args is not None:
+        if not isinstance(modules, list):
+            raise TypeError('extra_args must be a list')
+        args += extra_args
+
+    return binary_run(bin='vvp', args=args, **kwargs)

switchboard/loopback.py

@@ -0,0 +1,157 @@
+# Loopback test to check the behavior of blocks that split/merge UMI packets
+
+# Copyright (c) 2024 Zero ASIC Corporation
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+from numbers import Integral
+from typing import Iterable, Iterator, Union
+
+try:
+    from tqdm import tqdm
+except ModuleNotFoundError:
+    tqdm = None
+
+from .umi import UmiTxRx, random_umi_packet
+
+
+def umi_loopback(
+    umi: UmiTxRx,
+    packets: Union[Integral, Iterable, Iterator] = 10,
+    **kwargs
+):
+    """
+    Performs a loopback test by sending packets into a block and checking that
+    the packets received back are equivalent under the UMI split/merge rules.
+
+    Parameters
+    ----------
+    umi: UmiTxRx
+    packets:
+        Can be a number, a list of packets, or a generator.
+
+        - If this is a number, it represents the number of packets to send,
+          which are generated with random_umi_packet. Any remaining arguments
+          are passed directly to random_umi_packet.
+        - If this is an iterable (list, tuple, etc.), then it represents a list
+          of packets to use for the test.  This is helpful if you want to use a very
+          specific sequence of transactions.
+        - This can also be an iterator, which might be convenient if you want to
+          send a very large number of packets without having to store them
+          all in memory at once, e.g. (random_umi_packet() for _ in range(1000000))
+
+    Raises
+    ------
+    ValueError
+        If the number of packets is not positive or if the `packets` argument is empty
+    Exception
+        If a received packet does not match the corresponding transmitted packet
+
+    """
+
+    # input validation
+
+    if isinstance(packets, Integral):
+        if packets <= 0:
+            raise ValueError(f'The number of packets must be positive (got packets={packets}).')
+        else:
+            total = packets
+            packets = (random_umi_packet(**kwargs) for _ in range(packets))
+    elif isinstance(packets, Iterable):
+        if isinstance(packets, (list, tuple)):
+            total = len(packets)
+        else:
+            total = float('inf')
+        packets = iter(packets)
+    elif isinstance(packets, Iterator):
+        total = float('inf')
+    else:
+        raise TypeError(f'Unsupported type for packets: {type(packets)}')
+
+    tx_sets = []  # kept for debug purposes
+    tx_hist = []
+
+    tx_set = None
+    tx_partial = None
+
+    rx_set = None  # kept for debug purposes
+    rx_partial = None
+
+    if tqdm is not None:
+        pbar = tqdm(total=total)
+    else:
+        pbar = None
+
+    # get the first element
+    try:
+        txp = next(packets)
+        if pbar is not None:
+            pbar.update(0)
+    except StopIteration:
+        raise ValueError('The argument "packets" is empty.')
+
+    while (txp is not None) or (len(tx_hist) > 0):
+        # send data
+        if txp is not None:
+            if umi.send(txp, blocking=False):
+                if tx_partial is not None:
+                    if not tx_partial.merge(txp):
+                        tx_hist.append(tx_partial)
+                        tx_sets.append(tx_set)
+                        tx_start_new = True
+                    else:
+                        tx_set.append(txp)
+                        tx_start_new = False
+                else:
+                    tx_start_new = True
+
+                if tx_start_new:
+                    tx_partial = txp
+                    tx_set = [txp]
+
+                try:
+                    txp = next(packets)
+                except StopIteration:
+                    txp = None
+
+                if txp is None:
+                    # if this is the last packet, add it to the history
+                    # even if the merge was successful
+                    tx_hist.append(tx_partial)
+                    tx_sets.append(tx_set)
+
+        # receive data
+        if len(tx_hist) > 0:
+            rxp = umi.recv(blocking=False)
+            if rxp is not None:
+                # try to merge into an existing partial packet
+                if rx_partial is not None:
+                    if not rx_partial.merge(rxp):
+                        print('=== Mismatch detected ===')
+                        for i, p in enumerate(tx_sets[0]):
+                            print(f'* TX[{i}] *')
+                            print(p)
+                        print('---')
+                        for i, p in enumerate(rx_set):
+                            print(f'* RX[{i}] *')
+                            print(p)
+                        print('=========================')
+                        raise Exception('Mismatch!')
+                    else:
+                        rx_set.append(rxp)
+                else:
+                    rx_partial = rxp
+                    rx_set = [rxp]
+
+                # at this point it is guaranteed there is something in
+                # rx_partial, so compare it to the expected outbound packet
+                if rx_partial == tx_hist[0]:
+                    tx_hist.pop(0)
+                    tx_sets.pop(0)
+                    rx_partial = None
+                    rx_set = None
+
+                    if pbar is not None:
+                        pbar.update()
+
+    if pbar is not None:
+        pbar.close()