switchboard-hw 0.3.0__cp314-cp314-macosx_11_0_arm64.whl

switchboard/verilog/sim/queue_to_sb_sim.sv

@@ -0,0 +1,176 @@
+// queue_to_sb_sim
+
+// valid_mode settings (in all cases, valid remains low if there is no incoming data)
+// valid_mode=0: valid alternates between "0" and "1" if there is a continuous stream of incoming data
+// valid_mode=1: valid remains at "1" if there is a continuous stream of incoming data
+// valid_mode=2: valid toggles randomly if there is a continuous stream of incoming data
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module queue_to_sb_sim #(
+    parameter integer VALID_MODE_DEFAULT=0,
+    parameter integer DW=416,
+    parameter FILE=""
+) (
+    input clk,
+    input reset,
+    output [DW-1:0] data,
+    output reg [31:0] dest=32'b0,
+    output reg last=1'b0,
+    input ready,
+    output reg valid=1'b0
+);
+    // SBDW value corresponds to UMI DW=256
+    // 32b (cmd) + 64b (srcaddr) + 64b (dstaddr) + 256b = 416b
+
+    // SBDW must be a multiple of 32 (constrained by VPI driver,
+    // which transfers data in 32-bit chunks)
+    localparam SBDW = 416;
+
+    `ifdef __ICARUS__
+        `define SB_EXT_FUNC(x) $``x``
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+        `define SB_VAR_BIT reg
+    `else
+        `define SB_EXT_FUNC(x) x
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+        `define SB_VAR_BIT var bit
+
+        import "DPI-C" function void pi_sb_rx_init(output int id,
+            input string uri, input int width);
+        import "DPI-C" function void pi_sb_recv(input int id, output bit [SBDW-1:0] rdata,
+            output bit [31:0] rdest, output bit rlast, output int success);
+    `endif
+
+    // internal signals
+
+    integer id = -1;
+
+    `SB_START_FUNC init(input string uri);
+        /* verilator lint_off IGNOREDRETURN */
+        `SB_EXT_FUNC(pi_sb_rx_init)(id, uri, (DW + 7)/8);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    integer success = 0;
+
+    `SB_VAR_BIT [SBDW-1:0] rdata;
+    `SB_VAR_BIT [31:0] rdest;
+    `SB_VAR_BIT rlast;
+
+    `SB_VAR_BIT [SBDW-1:0] data_padded = 'b0;
+    assign data = data_padded[DW-1:0];
+
+    initial begin
+        rdata = 'b0;
+        rdest = 32'b0;
+        rlast = 1'b0;
+    end
+
+    // valid mode
+
+    integer valid_mode = VALID_MODE_DEFAULT;
+
+    `SB_START_FUNC set_valid_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        valid_mode = value;
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    // main logic
+
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            valid <= 1'b0;
+            last <= 1'b0;
+        end else begin
+            if (ready && valid) begin
+                // the transaction has completed, so we can try to get another
+                // packet if we want to.  whether we try to do this or not depends
+                // on the valid_mode setting.
+
+                if ((valid_mode == 32'd1) ||
+                    ((valid_mode == 32'd2) && ($random % 2 == 32'd1))) begin
+                    // try to receive a packet
+                    if (id != -1) begin
+                        /* verilator lint_off IGNOREDRETURN */
+                        `SB_EXT_FUNC(pi_sb_recv)(id, rdata, rdest, rlast, success);
+                        /* verilator lint_on IGNOREDRETURN */
+                    end else begin
+                        /* verilator lint_off BLKSEQ */
+                        success = 32'd0;
+                        /* verilator lint_on BLKSEQ */
+                    end
+
+                    // if a packet was received, mark the output as valid
+                    if (success == 32'd0) begin
+                        valid <= 1'b0;
+                    end else begin
+                        valid <= 1'b1;
+                        data_padded <= rdata;
+                        dest <= rdest;
+                        last <= rlast;
+                    end
+                end else begin
+                    valid <= 1'b0;
+                end
+            end else if (!valid) begin
+                // if there isn't a packet being presented, we can try to get one
+                // to present.  whether we do or not depends on valid_mode: if
+                // valid_mode=2, then flip a coin to decide if a new packet is read.
+                // in any other case, try to read a packet.
+
+                if ((valid_mode == 32'd0) || (valid_mode == 32'd1) ||
+                    ((valid_mode == 32'd2) && ($random % 2 == 32'd1))) begin
+                    // try to receive a packet
+                    if (id != -1) begin
+                        /* verilator lint_off IGNOREDRETURN */
+                        `SB_EXT_FUNC(pi_sb_recv)(id, rdata, rdest, rlast, success);
+                        /* verilator lint_on IGNOREDRETURN */
+                    end else begin
+                        /* verilator lint_off BLKSEQ */
+                        success = 32'd0;
+                        /* verilator lint_on BLKSEQ */
+                    end
+
+                    // if a packet was received, mark the output as valid
+                    if (success == 32'd0) begin
+                        valid <= 1'b0;
+                    end else begin
+                        valid <= 1'b1;
+                        data_padded <= rdata;
+                        dest <= rdest;
+                        last <= rlast;
+                    end
+                end else begin
+                    valid <= 1'b0;
+                end
+            end
+        end
+    end
+
+    // initialize
+
+    initial begin
+        if (FILE != "") begin
+            /* verilator lint_off IGNOREDRETURN */
+            init(FILE);
+            /* verilator lint_on IGNOREDRETURN */
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_EXT_FUNC
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+    `undef SB_VAR_BIT
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/queue_to_umi_sim.sv

@@ -0,0 +1,66 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module queue_to_umi_sim #(
+    parameter integer VALID_MODE_DEFAULT=0,
+    parameter integer DW=256,
+    parameter integer AW=64,
+    parameter integer CW=32,
+    parameter FILE=""
+) (
+    input clk,
+    input reset,
+    output [DW-1:0] data,
+    output [AW-1:0] srcaddr,
+    output [AW-1:0] dstaddr,
+    output [CW-1:0] cmd,
+    input ready,
+    output valid
+);
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(DW+AW+AW+CW),
+        .FILE(FILE)
+    ) rx_i (
+        .clk(clk),
+        .reset(reset),
+        .data({data, srcaddr, dstaddr, cmd}),
+        .dest(),
+        .last(),
+        .ready(ready),
+        .valid(valid)
+    );
+
+    // handle differences between simulators
+
+    `ifdef __ICARUS__
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+    `else
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+    `endif
+
+    `SB_START_FUNC init(input string uri);
+        /* verilator lint_off IGNOREDRETURN */
+        rx_i.init(uri);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_valid_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        rx_i.set_valid_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    // clean up macros
+
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/sb_apb_m.sv

@@ -0,0 +1,146 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module sb_apb_m #(
+    // AXI settings
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 16,
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+
+    // Switchboard settings
+    parameter integer VALID_MODE_DEFAULT=1,
+    parameter FILE=""
+) (
+    input wire clk,
+    input wire reset,
+
+    // APB master interface
+    output wire                     m_apb_psel,
+    output wire                     m_apb_penable,
+    output wire                     m_apb_pwrite,
+    output wire [2:0]               m_apb_pprot,
+    output wire [ADDR_WIDTH-1:0]    m_apb_paddr,
+    output wire [STRB_WIDTH-1:0]    m_apb_pstrb,
+    output wire [DATA_WIDTH-1:0]    m_apb_pwdata,
+    input  wire [DATA_WIDTH-1:0]    m_apb_prdata,
+    input  wire                     m_apb_pready,
+    input  wire                     m_apb_pslverr
+);
+
+    // APB FSM state register type
+    typedef enum logic [1:0] {
+        APB_IDLE,
+        APB_SETUP,
+        APB_ACCESS
+    } apb_state_t;
+
+    // Wires
+    wire apb_trans_avail;
+    wire apb_fire;
+
+    // APB FSM state register
+    apb_state_t apb_state;
+
+    // APB request channel
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(1 + 3 + STRB_WIDTH + ADDR_WIDTH + DATA_WIDTH)
+    ) apb_req_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_apb_pwrite, m_apb_pprot, m_apb_pstrb, m_apb_paddr, m_apb_pwdata}),
+        .dest(),
+        .last(),
+        .valid(apb_trans_avail),
+        .ready(apb_fire)
+    );
+
+    // APB response channel
+    sb_to_queue_sim #(
+        // Queue should always be ready to receive responses
+        .READY_MODE_DEFAULT(1),
+        .DW(DATA_WIDTH + 1)
+    ) apb_resp_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_apb_pslverr, m_apb_prdata}),
+        .dest(),
+        .last(),
+        .valid(apb_fire),
+        .ready()
+    );
+
+    // APB master state machine
+    always_ff @(posedge clk or posedge reset)
+        if (reset)
+            apb_state <= APB_IDLE;
+        else
+            case (apb_state)
+                APB_IDLE:
+                    if (apb_trans_avail) apb_state <= APB_SETUP;
+                APB_SETUP:
+                    apb_state <= APB_ACCESS;
+                APB_ACCESS:
+                    if (m_apb_pready) apb_state <= APB_IDLE;
+                default:
+                    apb_state <= APB_IDLE;
+            endcase
+
+    assign m_apb_psel = (apb_state == APB_SETUP || apb_state == APB_ACCESS);
+    assign m_apb_penable = (apb_state == APB_ACCESS);
+    assign apb_fire = m_apb_psel & m_apb_penable & m_apb_pready;
+
+    // handle differences between simulators
+
+    `ifdef __ICARUS__
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+    `else
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+    `endif
+
+    `SB_START_FUNC init(input string uri);
+        string s;
+
+        /* verilator lint_off IGNOREDRETURN */
+        $sformat(s, "%0s_apb_req.q", uri);
+        apb_req_channel.init(s);
+
+        $sformat(s, "%0s_apb_resp.q", uri);
+        apb_resp_channel.init(s);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_valid_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        apb_req_channel.set_valid_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_ready_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        apb_resp_channel.set_ready_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    // initialize
+
+    initial begin
+        if (FILE != "") begin
+            /* verilator lint_off IGNOREDRETURN */
+            init(FILE);
+            /* verilator lint_on IGNOREDRETURN */
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/sb_axi_m.sv

@@ -0,0 +1,199 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module sb_axi_m #(
+    // AXI settings
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 16,
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    parameter ID_WIDTH = 8,
+
+    // Switchboard settings
+    parameter integer VALID_MODE_DEFAULT=1,
+    parameter integer READY_MODE_DEFAULT=1,
+    parameter FILE=""
+) (
+    input wire clk,
+    input wire reset,
+
+    // AXI master interface
+    // adapted from https://github.com/alexforencich/verilog-axi
+    output wire [ID_WIDTH-1:0]    m_axi_awid,
+    output wire [ADDR_WIDTH-1:0]  m_axi_awaddr,
+    output wire [7:0]             m_axi_awlen,
+    output wire [2:0]             m_axi_awsize,
+    output wire [1:0]             m_axi_awburst,
+    output wire                   m_axi_awlock,
+    output wire [3:0]             m_axi_awcache,
+    output wire [2:0]             m_axi_awprot,
+    output wire                   m_axi_awvalid,
+    input  wire                   m_axi_awready,
+    output wire [DATA_WIDTH-1:0]  m_axi_wdata,
+    output wire [STRB_WIDTH-1:0]  m_axi_wstrb,
+    output wire                   m_axi_wlast,
+    output wire                   m_axi_wvalid,
+    input  wire                   m_axi_wready,
+    input  wire [ID_WIDTH-1:0]    m_axi_bid,
+    input  wire [1:0]             m_axi_bresp,
+    input  wire                   m_axi_bvalid,
+    output wire                   m_axi_bready,
+    output wire [ID_WIDTH-1:0]    m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]  m_axi_araddr,
+    output wire [7:0]             m_axi_arlen,
+    output wire [2:0]             m_axi_arsize,
+    output wire [1:0]             m_axi_arburst,
+    output wire                   m_axi_arlock,
+    output wire [3:0]             m_axi_arcache,
+    output wire [2:0]             m_axi_arprot,
+    output wire                   m_axi_arvalid,
+    input  wire                   m_axi_arready,
+    input  wire [ID_WIDTH-1:0]    m_axi_rid,
+    input  wire [DATA_WIDTH-1:0]  m_axi_rdata,
+    input  wire [1:0]             m_axi_rresp,
+    input  wire                   m_axi_rlast,
+    input  wire                   m_axi_rvalid,
+    output wire                   m_axi_rready
+);
+    // AW channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(ADDR_WIDTH + 3 + ID_WIDTH + 8 + 3 + 2 + 1 + 4)
+    ) aw_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axi_awcache, m_axi_awlock, m_axi_awburst, m_axi_awsize,
+            m_axi_awlen, m_axi_awid, m_axi_awprot, m_axi_awaddr}),
+        .dest(),
+        .last(),
+        .valid(m_axi_awvalid),
+        .ready(m_axi_awready)
+    );
+
+    // W channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(DATA_WIDTH + STRB_WIDTH + 1)
+    ) w_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axi_wlast, m_axi_wstrb, m_axi_wdata}),
+        .dest(),
+        .last(),
+        .valid(m_axi_wvalid),
+        .ready(m_axi_wready)
+    );
+
+    // B channel
+
+    sb_to_queue_sim #(
+        .READY_MODE_DEFAULT(READY_MODE_DEFAULT),
+        .DW(2 + ID_WIDTH)
+    ) b_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axi_bid, m_axi_bresp}),
+        .dest(),
+        .last(),
+        .valid(m_axi_bvalid),
+        .ready(m_axi_bready)
+    );
+
+    // AR channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(ADDR_WIDTH + 3 + ID_WIDTH + 8 + 3 + 2 + 1 + 4)
+    ) ar_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axi_arcache, m_axi_arlock, m_axi_arburst, m_axi_arsize,
+            m_axi_arlen, m_axi_arid, m_axi_arprot, m_axi_araddr}),
+        .dest(),
+        .last(),
+        .valid(m_axi_arvalid),
+        .ready(m_axi_arready)
+    );
+
+    // R channel
+
+    sb_to_queue_sim #(
+        .READY_MODE_DEFAULT(READY_MODE_DEFAULT),
+        .DW(DATA_WIDTH + 2 + ID_WIDTH + 1)
+    ) r_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axi_rlast, m_axi_rid, m_axi_rresp, m_axi_rdata}),
+        .dest(),
+        .last(),
+        .valid(m_axi_rvalid),
+        .ready(m_axi_rready)
+    );
+
+    // handle differences between simulators
+
+    `ifdef __ICARUS__
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+    `else
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+    `endif
+
+    `SB_START_FUNC init(input string uri);
+        string s;
+
+        /* verilator lint_off IGNOREDRETURN */
+        $sformat(s, "%0s-aw.q", uri);
+        aw_channel.init(s);
+
+        $sformat(s, "%0s-w.q", uri);
+        w_channel.init(s);
+
+        $sformat(s, "%0s-b.q", uri);
+        b_channel.init(s);
+
+        $sformat(s, "%0s-ar.q", uri);
+        ar_channel.init(s);
+
+        $sformat(s, "%0s-r.q", uri);
+        r_channel.init(s);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_valid_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        aw_channel.set_valid_mode(value);
+        w_channel.set_valid_mode(value);
+        ar_channel.set_valid_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_ready_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        b_channel.set_ready_mode(value);
+        r_channel.set_ready_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    // initialize
+
+    initial begin
+        if (FILE != "") begin
+            /* verilator lint_off IGNOREDRETURN */
+            init(FILE);
+            /* verilator lint_on IGNOREDRETURN */
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+
+endmodule
+
+`default_nettype wire