switchboard-hw 0.3.0__cp314-cp314-macosx_11_0_arm64.whl

switchboard/verilog/sim/sb_axil_m.sv

@@ -0,0 +1,180 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module sb_axil_m #(
+    // AXI settings
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 16,
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+
+    // Switchboard settings
+    parameter integer VALID_MODE_DEFAULT=1,
+    parameter integer READY_MODE_DEFAULT=1,
+    parameter FILE=""
+) (
+    input wire clk,
+    input wire reset,
+
+    // AXI lite master interface
+    // adapted from https://github.com/alexforencich/verilog-axi
+    output wire [ADDR_WIDTH-1:0] m_axil_awaddr,
+    output wire [2:0]            m_axil_awprot,
+    output wire                  m_axil_awvalid,
+    input  wire                  m_axil_awready,
+    output wire [DATA_WIDTH-1:0] m_axil_wdata,
+    output wire [STRB_WIDTH-1:0] m_axil_wstrb,
+    output wire                  m_axil_wvalid,
+    input  wire                  m_axil_wready,
+    input  wire [1:0]            m_axil_bresp,
+    input  wire                  m_axil_bvalid,
+    output wire                  m_axil_bready,
+    output wire [ADDR_WIDTH-1:0] m_axil_araddr,
+    output wire [2:0]            m_axil_arprot,
+    output wire                  m_axil_arvalid,
+    input  wire                  m_axil_arready,
+    input  wire [DATA_WIDTH-1:0] m_axil_rdata,
+    input  wire [1:0]            m_axil_rresp,
+    input  wire                  m_axil_rvalid,
+    output wire                  m_axil_rready
+);
+    // AW channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(ADDR_WIDTH + 3)
+    ) aw_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axil_awprot, m_axil_awaddr}),
+        .dest(),
+        .last(),
+        .valid(m_axil_awvalid),
+        .ready(m_axil_awready)
+    );
+
+    // W channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(DATA_WIDTH + STRB_WIDTH)
+    ) w_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axil_wstrb, m_axil_wdata}),
+        .dest(),
+        .last(),
+        .valid(m_axil_wvalid),
+        .ready(m_axil_wready)
+    );
+
+    // B channel
+
+    sb_to_queue_sim #(
+        .READY_MODE_DEFAULT(READY_MODE_DEFAULT),
+        .DW(2)
+    ) b_channel (
+        .clk(clk),
+        .reset(reset),
+        .data(m_axil_bresp),
+        .dest(),
+        .last(),
+        .valid(m_axil_bvalid),
+        .ready(m_axil_bready)
+    );
+
+    // AR channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(ADDR_WIDTH + 3)
+    ) ar_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axil_arprot, m_axil_araddr}),
+        .dest(),
+        .last(),
+        .valid(m_axil_arvalid),
+        .ready(m_axil_arready)
+    );
+
+    // R channel
+
+    sb_to_queue_sim #(
+        .READY_MODE_DEFAULT(READY_MODE_DEFAULT),
+        .DW(DATA_WIDTH + 2)
+    ) r_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({m_axil_rresp, m_axil_rdata}),
+        .dest(),
+        .last(),
+        .valid(m_axil_rvalid),
+        .ready(m_axil_rready)
+    );
+
+    // handle differences between simulators
+
+    `ifdef __ICARUS__
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+    `else
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+    `endif
+
+    `SB_START_FUNC init(input string uri);
+        string s;
+
+        /* verilator lint_off IGNOREDRETURN */
+        $sformat(s, "%0s-aw.q", uri);
+        aw_channel.init(s);
+
+        $sformat(s, "%0s-w.q", uri);
+        w_channel.init(s);
+
+        $sformat(s, "%0s-b.q", uri);
+        b_channel.init(s);
+
+        $sformat(s, "%0s-ar.q", uri);
+        ar_channel.init(s);
+
+        $sformat(s, "%0s-r.q", uri);
+        r_channel.init(s);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_valid_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        aw_channel.set_valid_mode(value);
+        w_channel.set_valid_mode(value);
+        ar_channel.set_valid_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_ready_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        b_channel.set_ready_mode(value);
+        r_channel.set_ready_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    // initialize
+
+    initial begin
+        if (FILE != "") begin
+            /* verilator lint_off IGNOREDRETURN */
+            init(FILE);
+            /* verilator lint_on IGNOREDRETURN */
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/sb_axil_s.sv

@@ -0,0 +1,180 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module sb_axil_s #(
+    // AXI settings
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 16,
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+
+    // Switchboard settings
+    parameter integer VALID_MODE_DEFAULT=1,
+    parameter integer READY_MODE_DEFAULT=1,
+    parameter FILE=""
+) (
+    input wire clk,
+    input wire reset,
+
+    // AXI lite master interface
+    // adapted from https://github.com/alexforencich/verilog-axi
+    input  wire [ADDR_WIDTH-1:0] s_axil_awaddr,
+    input  wire [2:0]            s_axil_awprot,
+    input  wire                  s_axil_awvalid,
+    output wire                  s_axil_awready,
+    input  wire [DATA_WIDTH-1:0] s_axil_wdata,
+    input  wire [STRB_WIDTH-1:0] s_axil_wstrb,
+    input  wire                  s_axil_wvalid,
+    output wire                  s_axil_wready,
+    output wire [1:0]            s_axil_bresp,
+    output wire                  s_axil_bvalid,
+    input  wire                  s_axil_bready,
+    input  wire [ADDR_WIDTH-1:0] s_axil_araddr,
+    input  wire [2:0]            s_axil_arprot,
+    input  wire                  s_axil_arvalid,
+    output wire                  s_axil_arready,
+    output wire [DATA_WIDTH-1:0] s_axil_rdata,
+    output wire [1:0]            s_axil_rresp,
+    output wire                  s_axil_rvalid,
+    input  wire                  s_axil_rready
+);
+    // AW channel
+
+    sb_to_queue_sim #(
+        .READY_MODE_DEFAULT(READY_MODE_DEFAULT),
+        .DW(ADDR_WIDTH + 3)
+    ) aw_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({s_axil_awprot, s_axil_awaddr}),
+        .dest(),
+        .last(),
+        .valid(s_axil_awvalid),
+        .ready(s_axil_awready)
+    );
+
+    // W channel
+
+    sb_to_queue_sim #(
+        .READY_MODE_DEFAULT(READY_MODE_DEFAULT),
+        .DW(DATA_WIDTH + STRB_WIDTH)
+    ) w_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({s_axil_wstrb, s_axil_wdata}),
+        .dest(),
+        .last(),
+        .valid(s_axil_wvalid),
+        .ready(s_axil_wready)
+    );
+
+    // B channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(2)
+    ) b_channel (
+        .clk(clk),
+        .reset(reset),
+        .data(s_axil_bresp),
+        .dest(),
+        .last(),
+        .valid(s_axil_bvalid),
+        .ready(s_axil_bready)
+    );
+
+    // AR channel
+
+    sb_to_queue_sim #(
+        .READY_MODE_DEFAULT(READY_MODE_DEFAULT),
+        .DW(ADDR_WIDTH + 3)
+    ) ar_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({s_axil_arprot, s_axil_araddr}),
+        .dest(),
+        .last(),
+        .valid(s_axil_arvalid),
+        .ready(s_axil_arready)
+    );
+
+    // R channel
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(DATA_WIDTH + 2)
+    ) r_channel (
+        .clk(clk),
+        .reset(reset),
+        .data({s_axil_rresp, s_axil_rdata}),
+        .dest(),
+        .last(),
+        .valid(s_axil_rvalid),
+        .ready(s_axil_rready)
+    );
+
+    // handle differences between simulators
+
+    `ifdef __ICARUS__
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+    `else
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+    `endif
+
+    `SB_START_FUNC init(input string uri);
+        string s;
+
+        /* verilator lint_off IGNOREDRETURN */
+        $sformat(s, "%0s-aw.q", uri);
+        aw_channel.init(s);
+
+        $sformat(s, "%0s-w.q", uri);
+        w_channel.init(s);
+
+        $sformat(s, "%0s-b.q", uri);
+        b_channel.init(s);
+
+        $sformat(s, "%0s-ar.q", uri);
+        ar_channel.init(s);
+
+        $sformat(s, "%0s-r.q", uri);
+        r_channel.init(s);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_valid_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        b_channel.set_valid_mode(value);
+        r_channel.set_valid_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_ready_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        aw_channel.set_ready_mode(value);
+        w_channel.set_ready_mode(value);
+        ar_channel.set_ready_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    // initialize
+
+    initial begin
+        if (FILE != "") begin
+            /* verilator lint_off IGNOREDRETURN */
+            init(FILE);
+            /* verilator lint_on IGNOREDRETURN */
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/sb_clk_gen.sv

@@ -0,0 +1,89 @@
+// Module for generating a simulation clock, needed for non-Verilator simulations
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+module sb_clk_gen #(
+    parameter real DEFAULT_PERIOD = 10e-9,
+    parameter real DEFAULT_DUTY_CYCLE = 0.5,
+    parameter real DEFAULT_MAX_RATE = -1,
+    parameter real DEFAULT_START_DELAY = -1
+) (
+    output wire clk
+);
+    // configure timing
+
+    `ifdef SB_XYCE
+        timeunit 1s;
+        timeprecision 1fs;
+        `define SB_DELAY(t) #(t)
+    `else
+        timeunit 1ns;
+        timeprecision 1ns;
+        `define SB_DELAY(t) #((t)*1e9)
+    `endif
+
+    // import external functions
+
+    `ifdef __ICARUS__
+        `define SB_EXT_FUNC(x) $``x``
+    `else
+        `define SB_EXT_FUNC(x) x
+
+        import "DPI-C" function void pi_start_delay (
+            input real value
+        );
+
+        import "DPI-C" function void pi_max_rate_tick (
+            inout signed [63:0] t_us,
+            input signed [63:0] min_period_us
+        );
+    `endif
+
+    // read in command-line arguments
+
+    real period = DEFAULT_PERIOD;
+    real duty_cycle = DEFAULT_DUTY_CYCLE;
+    real max_rate = DEFAULT_MAX_RATE;
+    real start_delay = DEFAULT_START_DELAY;
+
+    reg signed [63:0] t_us = -(64'sd1);
+    reg signed [63:0] min_period_us = -(64'sd1);
+
+    initial begin
+        void'($value$plusargs("period=%f", period));
+        void'($value$plusargs("duty-cycle=%f", duty_cycle));
+        void'($value$plusargs("start-delay=%f", start_delay));
+
+        void'($value$plusargs("max-rate=%f", max_rate));
+
+        if (max_rate > 0) begin
+            min_period_us = 1.0e6 / max_rate;  // rounds according to LRM
+        end
+    end
+
+    // main clock generation code
+
+    reg clk_r;
+    assign clk = clk_r;
+
+    initial begin
+        `SB_EXT_FUNC(pi_start_delay)(start_delay);
+
+        forever begin
+            `SB_EXT_FUNC(pi_max_rate_tick)(t_us, min_period_us);
+
+            clk_r = 1'b0;
+            `SB_DELAY((1.0 - duty_cycle) * period);
+
+            clk_r = 1'b1;
+            `SB_DELAY(duty_cycle * period);
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_EXT_FUNC
+    `undef SB_DELAY
+
+endmodule

switchboard/verilog/sim/sb_jtag_rbb_sim.sv

@@ -0,0 +1,148 @@
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module sb_jtag_rbb_sim (
+    input clk,
+    input rst,
+    output tck,
+    output tms,
+    output tdi,
+    input tdo,
+    output trst,
+    output srst,
+    output reg led=1'b0
+);
+    `ifdef __ICARUS__
+        `define SB_EXT_FUNC(x) $``x``
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+        `define SB_VAR_BIT reg
+    `else
+        `define SB_EXT_FUNC(x) x
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+        `define SB_VAR_BIT var bit
+
+        import "DPI-C" function void pi_sb_rx_init(output int id, input string uri);
+        import "DPI-C" function void pi_sb_recv(input int id, output bit [255:0] rdata,
+            output bit [31:0] rdest, output bit rlast, output int success);
+
+        import "DPI-C" function void pi_sb_tx_init (output int id, input string uri);
+        import "DPI-C" function void pi_sb_send (input int id, input bit [255:0] sdata,
+            input bit [31:0] sdest, input bit slast, output int success);
+    `endif
+
+    // SB DPI/VPI interface
+
+    integer rxid=-1;
+    integer txid=-1;
+
+    `SB_START_FUNC init(input string rxuri, input string txuri);
+        /* verilator lint_off IGNOREDRETURN */
+        `SB_EXT_FUNC(pi_sb_rx_init)(rxid, rxuri);
+        `SB_EXT_FUNC(pi_sb_tx_init)(txid, txuri);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_VAR_BIT [255:0] sdata;
+    `SB_VAR_BIT [31:0] sdest;
+    `SB_VAR_BIT slast;
+
+    `SB_VAR_BIT [255:0] rdata;
+    `SB_VAR_BIT [31:0] rdest;
+    `SB_VAR_BIT rlast;
+
+    // initialize
+
+    integer r_success = 0;
+    integer s_success = 0;
+
+    initial begin
+        sdata = 256'd0;
+        sdest = 32'd0;
+        slast = 1'b1;
+    end
+
+    // main logic
+
+    reg [31:0] read_count = 32'd0;
+
+    // convenient to group these together,
+    // so that the output value can be computed
+    // from the incoming ASCII command
+
+    reg [2:0] tck_tms_tdi = 3'b011;
+    assign tck = tck_tms_tdi[2];
+    assign tms = tck_tms_tdi[1];
+    assign tdi = tck_tms_tdi[0];
+
+    reg [1:0] trst_srst = 2'b11;
+    assign trst = trst_srst[1];
+    assign srst = trst_srst[0];
+
+    always @(posedge clk) begin
+        if (rst) begin
+            // external pins
+            tck_tms_tdi <= 3'b011;
+            trst_srst <= 2'b11;
+            led <= 1'b0;
+
+            // internal state
+            read_count <= 32'd0;
+        end else begin
+            // write output value
+            if (read_count > 0) begin
+                sdata[7:0] = tdo ? "1" : "0";  // intended to be blocking
+                if (txid != -1) begin
+                    `SB_EXT_FUNC(pi_sb_send)(txid, sdata, sdest, slast, s_success);
+                end else begin
+                    s_success = 32'd0;
+                end
+                if (s_success == 32'd1) begin
+                    read_count <= read_count - 1;
+                end
+            end
+
+            // get next command as long as long as it
+            // couldn't overflow the read counter
+            if (read_count < 32'h7fffffff) begin
+                if (rxid != -1) begin
+                    `SB_EXT_FUNC(pi_sb_recv)(rxid, rdata, rdest, rlast, r_success);
+                end else begin
+                    r_success = 32'd0;
+                end
+                if (r_success == 32'd1) begin
+                    if (rdata[7:0] == "B") begin
+                        led <= 1'b1;
+                    end else if (rdata[7:0] == "b") begin
+                        led <= 1'b0;
+                    end else if (rdata[7:0] == "R") begin
+                        read_count <= read_count + 32'd1;
+                    end else if (rdata[7:0] == "Q") begin
+                        // TODO: quit
+                    end else if (("0" <= rdata[7:0]) && (rdata[7:0] <= "7")) begin
+                        /* verilator lint_off WIDTH */
+                        tck_tms_tdi <= {rdata[7:0] - "0"};
+                        /* verilator lint_on WIDTH */
+                    end else if (("r" <= rdata[7:0]) && (rdata[7:0] <= "u")) begin
+                        /* verilator lint_off WIDTH */
+                        trst_srst <= {rdata[7:0] - "r"};
+                        /* verilator lint_on WIDTH */
+                    end
+                end
+            end
+        end
+    end
+
+    // clean up macros
+
+    `undef SB_EXT_FUNC
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+    `undef SB_VAR_BIT
+
+endmodule
+
+`default_nettype wire

switchboard/verilog/sim/sb_rx_sim.sv

@@ -0,0 +1,55 @@
+// Wrapper module for backwards compatibility (will eventually be removed)
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`default_nettype none
+
+module sb_rx_sim #(
+    parameter integer VALID_MODE_DEFAULT=0,
+    parameter integer DW=416,
+    parameter FILE=""
+) (
+    input clk,
+    output [DW-1:0] data,
+    output [31:0] dest,
+    output last,
+    input ready,
+    output valid
+);
+    `ifdef __ICARUS__
+        `define SB_START_FUNC task
+        `define SB_END_FUNC endtask
+    `else
+        `define SB_START_FUNC function void
+        `define SB_END_FUNC endfunction
+    `endif
+
+    queue_to_sb_sim #(
+        .VALID_MODE_DEFAULT(VALID_MODE_DEFAULT),
+        .DW(DW),
+        .FILE(FILE)
+    ) rx_i (
+        .*
+    );
+
+    `SB_START_FUNC init(input string uri);
+        /* verilator lint_off IGNOREDRETURN */
+        rx_i.init(uri);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    `SB_START_FUNC set_valid_mode(input integer value);
+        /* verilator lint_off IGNOREDRETURN */
+        rx_i.set_valid_mode(value);
+        /* verilator lint_on IGNOREDRETURN */
+    `SB_END_FUNC
+
+    // clean up macros
+
+    `undef SB_START_FUNC
+    `undef SB_END_FUNC
+
+endmodule
+
+`default_nettype wire