switchboard-hw 0.3.0__cp314-cp314-macosx_11_0_arm64.whl

switchboard/util.py

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+# General utilities for working with switchboard
+
+# Copyright (c) 2024 Zero ASIC Corporation
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+import atexit
+import signal
+import subprocess
+import shlex
+
+
+def plusargs_to_args(plusargs):
+    args = []
+    if plusargs is not None:
+        if not isinstance(plusargs, list):
+            raise TypeError('plusargs must be a list')
+        for plusarg in plusargs:
+            if isinstance(plusarg, (list, tuple)):
+                if len(plusarg) != 2:
+                    raise ValueError('Only lists/tuples of length 2 allowed')
+                args += [f'+{plusarg[0]}={plusarg[1]}']
+            else:
+                args += [f'+{plusarg}']
+    return args
+
+
+def binary_run(bin, args=None, stop_timeout=10, use_sigint=False,
+    quiet=False, print_command=False, cwd=None, env=None):
+
+    cmd = []
+
+    cmd += [bin]
+
+    if args is not None:
+        if not isinstance(args, list):
+            raise TypeError('args must be a list')
+        cmd += args
+
+    cmd = [str(elem) for elem in cmd]
+    if print_command:
+        print(' '.join([shlex.quote(elem) for elem in cmd]))
+
+    kwargs = {}
+    if quiet:
+        kwargs['stdout'] = subprocess.DEVNULL
+        kwargs['stderr'] = subprocess.DEVNULL
+
+    p = subprocess.Popen(cmd, cwd=cwd, env=env, **kwargs)
+
+    def stop_bin(p=p, stop_timeout=stop_timeout, use_sigint=use_sigint):
+        poll = p.poll()
+        if poll is not None:
+            # process has stopped
+            return
+
+        if use_sigint:
+            try:
+                p.send_signal(signal.SIGINT)
+                p.wait(stop_timeout)
+                return
+            except:  # noqa: E722
+                # if there is an exception for any reason, including
+                # Ctrl-C during the wait() call, want to make sure
+                # that the process is actually terminated
+                pass
+
+        # if we get to this point, the process is still running
+        # and sigint didn't work (or we didn't try it)
+        p.terminate()
+
+    # note: tried combining all process terminations into a single
+    # function registered with atexit, but it didn't appear to make
+    # a difference when running with a few hundred verilator sim
+    # processes - still took a few dozen milliseconds to stop each
+    # simulator.
+
+    atexit.register(stop_bin)
+
+    return p
+
+
+class ProcessCollection:
+    def __init__(self):
+        self.processes = []
+
+    def add(self, process):
+        self.processes.append(process)
+
+    def wait(self):
+        import subprocess
+        import multiprocessing
+
+        for process in self.processes:
+            if isinstance(process, subprocess.Popen):
+                process.wait()
+            elif isinstance(process, multiprocessing.Process):
+                process.join()
+            else:
+                raise Exception(f'Unknown process type: {type(process)}')
+
+    def terminate(
+        self,
+        stop_timeout=10,
+        use_sigint=False
+    ):
+        if not self.processes:
+            return
+
+        for p in self.processes:
+            if isinstance(p, ProcessCollection):
+                p.terminate(stop_timeout=stop_timeout, use_sigint=use_sigint)
+            else:
+                poll = p.poll()
+                if poll is not None:
+                    # process has stopped
+                    return
+
+                if use_sigint:
+                    try:
+                        p.send_signal(signal.SIGINT)
+                        p.wait(stop_timeout)
+                        return
+                    except:  # noqa: E722
+                        # if there is an exception for any reason, including
+                        # Ctrl-C during the wait() call, want to make sure
+                        # that the process is actually terminated
+                        pass
+
+                # if we get to this point, the process is still running
+                # and sigint didn't work (or we didn't try it)
+                p.terminate()

switchboard/verilator/config.vlt

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+// This file silences Verilator warnings in the verilog-axi third party library.
+// Note: this file must be passed to Verilator *before* Verilog sources.
+
+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+`verilator_config
+
+lint_off -file "*/deps/verilog-axi/rtl/*"
+
+// For some reason these are not caught by the blanket statement above
+lint_off -rule UNOPTFLAT -file "*/deps/verilog-axi/rtl/*"
+lint_off -rule INITIALDLY -file "*/deps/verilog-axi/rtl/*"

switchboard/verilator/testbench.cc

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+// Copyright (c) 2024 Zero ASIC Corporation
+// This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+// modified from examples/make_tracing_c/sim_main.cpp in https://github.com/verilator/verilator,
+// by Wilson Snyder (2017), released as Creative Commons Public Domain
+
+// For Ctrl-C handling
+#include <signal.h>
+
+// For std::unique_ptr
+#include <memory>
+
+// For changing the clock period
+#include <cmath>
+#include <iostream>
+#include <sstream>
+#include <string>
+
+// Include common routines
+#include <verilated.h>
+
+// Include model header, generated from Verilating "top.v"
+#include "Vtestbench.h"
+
+// Include switchboard functions
+#include "switchboard.hpp"
+
+// Legacy function required only so linking works on Cygwin and MSVC++
+double sc_time_stamp() {
+    return 0;
+}
+
+// ref: https://stackoverflow.com/a/4217052
+static volatile int got_sigint = 0;
+
+void sigint_handler(int unused) {
+    got_sigint = 1;
+}
+
+std::string extract_plusarg_value(const char* match, const char* name) {
+    if (match) {
+        std::string full = std::string(match);
+        std::string prefix = "+" + std::string(name) + "=";
+        size_t len = prefix.size();
+        // match requirements: there must be at least one character after
+        // the prefix, and the argument must start with the prefix,
+        // ignoring the last character of the prefix, which can be
+        // anything (typically "=" or "+")
+        if ((full.size() >= (len + 1)) && (full.substr(0, len - 1) == prefix.substr(0, len - 1))) {
+            return std::string(match).substr(len);
+        }
+    }
+
+    // if we get here, return an empty string
+    return "";
+}
+
+template <typename T> void parse_plusarg(const char* match, const char* name, T& result) {
+    std::string value = extract_plusarg_value(match, name);
+
+    if (value != "") {
+        std::istringstream iss(value);
+        iss >> result;
+    }
+}
+
+int main(int argc, char** argv, char** env) {
+    // Prevent unused variable warnings
+    if (false && argc && argv && env) {}
+
+    // Using unique_ptr is similar to
+    // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    // Do not instead make Vtop as a file-scope static variable, as the
+    // "C++ static initialization order fiasco" may cause a crash
+
+    // Verilator must compute traced signals
+    contextp->traceEverOn(true);
+
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    contextp->commandArgs(argc, argv);
+
+    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v".
+    // Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end.
+    // "TOP" will be the hierarchical name of the module.
+    const std::unique_ptr<Vtestbench> top{new Vtestbench{contextp.get(), "TOP"}};
+
+    // parse the clock period, if provided
+    double period = 10e-9;
+    const char* period_match = contextp->commandArgsPlusMatch("period");
+    parse_plusarg<double>(period_match, "period", period);
+
+    // parse the maximum simulation rate, if provided.  convert it to a target
+    // period in microseconds
+
+    double max_rate = -1;
+    const char* rate_match = contextp->commandArgsPlusMatch("max-rate");
+    parse_plusarg<double>(rate_match, "max-rate", max_rate);
+
+    // convert the clock period an integer, scaling by the time precision
+    uint64_t iperiod = std::round(period * std::pow(10.0, -1.0 * contextp->timeprecision()));
+    uint64_t duration0 = iperiod / 2;
+    uint64_t duration1 = iperiod - duration0;
+
+    // Set Vtestbench's input signals
+    top->clk = 0;
+    top->eval();
+
+    // Set up Ctrl-C handler
+    signal(SIGINT, sigint_handler);
+
+    // Optional delay before setting up main loop
+
+    double start_delay_value = -1;
+    const char* delay_match = contextp->commandArgsPlusMatch("start-delay");
+    parse_plusarg<double>(delay_match, "start-delay", start_delay_value);
+
+    start_delay(start_delay_value);
+
+    // Main loop
+
+    long t_us = -1;
+    long min_period_us = (1.0e6 / max_rate) + 0.5;
+
+    while (!(contextp->gotFinish() || got_sigint)) {
+        max_rate_tick(t_us, min_period_us);
+
+        contextp->timeInc(duration0);
+        top->clk = 1;
+        top->eval();
+        contextp->timeInc(duration1);
+        top->clk = 0;
+        top->eval();
+    }
+
+    // Final model cleanup
+    top->final();
+
+    // Return good completion status
+    // Don't use exit() or destructor won't get called
+    return 0;
+}

switchboard/verilator/verilator.py

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+from siliconcompiler import Design
+
+from switchboard import sb_path
+
+
+class Verilator(Design):
+    def __init__(self):
+        super().__init__("verilator")
+
+        self.set_dataroot('localroot', sb_path() / "verilator")
+
+        with self.active_fileset('verilator'):
+            self.add_file("testbench.cc")

switchboard/verilator_run.py

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+# Utilities for working with Verilator
+
+# Copyright (c) 2024 Zero ASIC Corporation
+# This code is licensed under Apache License 2.0 (see LICENSE for details)
+
+# TODO: replace with SiliconCompiler functionality
+
+from .util import plusargs_to_args, binary_run
+
+
+def verilator_run(bin, plusargs=None, args=None, use_sigint=True, **kwargs):
+    if args is None:
+        extra_args = []
+    elif isinstance(args, (list, tuple)):
+        # even if args is already a list, make a copy to
+        # ensure that changes don't propagate back to the
+        # value that the user provided for args
+        extra_args = list(args)
+    else:
+        # if the user provided a single value for args,
+        # wrap it in a list rather than erroring out
+        extra_args = [args]
+
+    # build up the argument list
+    args = []
+    args += plusargs_to_args(plusargs)
+
+    # append any extra arguments user provided by the user
+    args += extra_args
+
+    return binary_run(bin=bin, args=args, use_sigint=use_sigint, **kwargs)

switchboard/verilog/common/common.py

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+from siliconcompiler import Design
+
+from umi.sumi import Unpack, Pack
+
+from switchboard import sb_path
+
+
+class Common(Design):
+    def __init__(self):
+
+        super().__init__("common")
+
+        files = [
+            "uart_xactor.sv",
+            "umi_gpio.v"
+        ]
+        deps = [Unpack(), Pack()]
+
+        self.set_dataroot('sb_verilog_common', sb_path() / "verilog" / "common")
+
+        with self.active_fileset('rtl'):
+            self.add_idir(".")
+            for item in files:
+                self.add_file(item)
+            for item in deps:
+                self.add_depfileset(item)