qiskit 1.0.0b1__cp38-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl

qiskit/transpiler/passes/scheduling/padding/pad_delay.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2022.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Padding pass to insert Delay to the empty slots."""
+
+from qiskit.circuit import Qubit
+from qiskit.circuit.delay import Delay
+from qiskit.dagcircuit import DAGCircuit, DAGNode, DAGOutNode
+from qiskit.transpiler.target import Target
+
+from .base_padding import BasePadding
+
+
+class PadDelay(BasePadding):
+    """Padding idle time with Delay instructions.
+
+    Consecutive delays will be merged in the output of this pass.
+
+    .. code-block:: python
+
+        durations = InstructionDurations([("x", None, 160), ("cx", None, 800)])
+
+        qc = QuantumCircuit(2)
+        qc.delay(100, 0)
+        qc.x(1)
+        qc.cx(0, 1)
+
+    The ASAP-scheduled circuit output may become
+
+    .. parsed-literal::
+
+             ┌────────────────┐
+        q_0: ┤ Delay(160[dt]) ├──■──
+             └─────┬───┬──────┘┌─┴─┐
+        q_1: ──────┤ X ├───────┤ X ├
+                   └───┘       └───┘
+
+    Note that the additional idle time of 60dt on the ``q_0`` wire coming from the duration difference
+    between ``Delay`` of 100dt (``q_0``) and ``XGate`` of 160 dt (``q_1``) is absorbed in
+    the delay instruction on the ``q_0`` wire, i.e. in total 160 dt.
+
+    See :class:`BasePadding` pass for details.
+    """
+
+    def __init__(self, fill_very_end: bool = True, target: Target = None):
+        """Create new padding delay pass.
+
+        Args:
+            fill_very_end: Set ``True`` to fill the end of circuit with delay.
+            target: The :class:`~.Target` representing the target backend.
+                If it is supplied and does not support delay instruction on a qubit,
+                padding passes do not pad any idle time of the qubit.
+        """
+        super().__init__(target=target)
+        self.fill_very_end = fill_very_end
+
+    def _pad(
+        self,
+        dag: DAGCircuit,
+        qubit: Qubit,
+        t_start: int,
+        t_end: int,
+        next_node: DAGNode,
+        prev_node: DAGNode,
+    ):
+        if not self.fill_very_end and isinstance(next_node, DAGOutNode):
+            return
+
+        time_interval = t_end - t_start
+        self._apply_scheduled_op(dag, t_start, Delay(time_interval, dag.unit), qubit)

qiskit/transpiler/passes/scheduling/rzx_templates.py

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+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2021.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+# pylint: disable=unused-import
+
+"""
+Convenience function to load RZXGate based templates.
+"""
+
+import warnings
+from qiskit.transpiler.passes.calibration.rzx_templates import rzx_templates
+
+# TODO remove this import after sufficient deprecation period
+
+warnings.warn(
+    "rzx_templates function is moved to `qiskit.transpiler.passes.calibration.rzx_templates`. "
+    "This import path is being deprecated.",
+    DeprecationWarning,
+)

qiskit/transpiler/passes/scheduling/scheduling/__init__.py

@@ -0,0 +1,17 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2022.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Scheduling pass to assign instruction start time."""
+
+from .asap import ASAPScheduleAnalysis
+from .alap import ALAPScheduleAnalysis
+from .set_io_latency import SetIOLatency

qiskit/transpiler/passes/scheduling/scheduling/alap.py

@@ -0,0 +1,127 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2020.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""ALAP Scheduling."""
+from qiskit.circuit import Measure
+from qiskit.transpiler.exceptions import TranspilerError
+
+from qiskit.transpiler.passes.scheduling.scheduling.base_scheduler import BaseScheduler
+
+
+class ALAPScheduleAnalysis(BaseScheduler):
+    """ALAP Scheduling pass, which schedules the **stop** time of instructions as late as possible.
+
+    See the :ref:`scheduling_stage` section in the :mod:`qiskit.transpiler`
+    module documentation for the detailed behavior of the control flow
+    operation, i.e. ``c_if``.
+    """
+
+    def run(self, dag):
+        """Run the ALAPSchedule pass on `dag`.
+
+        Args:
+            dag (DAGCircuit): DAG to schedule.
+
+        Returns:
+            DAGCircuit: A scheduled DAG.
+
+        Raises:
+            TranspilerError: if the circuit is not mapped on physical qubits.
+            TranspilerError: if conditional bit is added to non-supported instruction.
+        """
+        if len(dag.qregs) != 1 or dag.qregs.get("q", None) is None:
+            raise TranspilerError("ALAP schedule runs on physical circuits only")
+
+        conditional_latency = self.property_set.get("conditional_latency", 0)
+        clbit_write_latency = self.property_set.get("clbit_write_latency", 0)
+
+        node_start_time = {}
+        idle_before = {q: 0 for q in dag.qubits + dag.clbits}
+        for node in reversed(list(dag.topological_op_nodes())):
+            op_duration = self._get_node_duration(node, dag)
+
+            # compute t0, t1: instruction interval, note that
+            # t0: start time of instruction
+            # t1: end time of instruction
+
+            # since this is alap scheduling, node is scheduled in reversed topological ordering
+            # and nodes are packed from the very end of the circuit.
+            # the physical meaning of t0 and t1 is flipped here.
+            if isinstance(node.op, self.CONDITIONAL_SUPPORTED):
+                t0q = max(idle_before[q] for q in node.qargs)
+                if node.op.condition_bits:
+                    # conditional is bit tricky due to conditional_latency
+                    t0c = max(idle_before[c] for c in node.op.condition_bits)
+                    # Assume following case (t0c > t0q):
+                    #
+                    #                |t0q
+                    # Q ░░░░░░░░░░░░░▒▒▒
+                    # C ░░░░░░░░▒▒▒▒▒▒▒▒
+                    #           |t0c
+                    #
+                    # In this case, there is no actual clbit read before gate.
+                    #
+                    #             |t0q' = t0c - conditional_latency
+                    # Q ░░░░░░░░▒▒▒░░▒▒▒
+                    # C ░░░░░░▒▒▒▒▒▒▒▒▒▒
+                    #         |t1c' = t0c + conditional_latency
+                    #
+                    # rather than naively doing
+                    #
+                    #        |t1q' = t0c + duration
+                    # Q ░░░░░▒▒▒░░░░░▒▒▒
+                    # C ░░▒▒░░░░▒▒▒▒▒▒▒▒
+                    #     |t1c' = t0c + duration + conditional_latency
+                    #
+                    t0 = max(t0q, t0c - op_duration)
+                    t1 = t0 + op_duration
+                    for clbit in node.op.condition_bits:
+                        idle_before[clbit] = t1 + conditional_latency
+                else:
+                    t0 = t0q
+                    t1 = t0 + op_duration
+            else:
+                if node.op.condition_bits:
+                    raise TranspilerError(
+                        f"Conditional instruction {node.op.name} is not supported in ALAP scheduler."
+                    )
+
+                if isinstance(node.op, Measure):
+                    # clbit time is always right (alap) justified
+                    t0 = max(idle_before[bit] for bit in node.qargs + node.cargs)
+                    t1 = t0 + op_duration
+                    #
+                    #        |t1 = t0 + duration
+                    # Q ░░░░░▒▒▒▒▒▒▒▒▒▒▒
+                    # C ░░░░░░░░░▒▒▒▒▒▒▒
+                    #            |t0 + (duration - clbit_write_latency)
+                    #
+                    for clbit in node.cargs:
+                        idle_before[clbit] = t0 + (op_duration - clbit_write_latency)
+                else:
+                    # It happens to be directives such as barrier
+                    t0 = max(idle_before[bit] for bit in node.qargs + node.cargs)
+                    t1 = t0 + op_duration
+
+            for bit in node.qargs:
+                idle_before[bit] = t1
+
+            node_start_time[node] = t1
+
+        # Compute maximum instruction available time, i.e. very end of t1
+        circuit_duration = max(idle_before.values())
+
+        # Note that ALAP pass is inversely schedule, thus
+        # t0 is computed by subtracting entire circuit duration from t1.
+        self.property_set["node_start_time"] = {
+            n: circuit_duration - t1 for n, t1 in node_start_time.items()
+        }

qiskit/transpiler/passes/scheduling/scheduling/asap.py

@@ -0,0 +1,131 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2020.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""ASAP Scheduling."""
+from qiskit.circuit import Measure
+from qiskit.transpiler.exceptions import TranspilerError
+
+from qiskit.transpiler.passes.scheduling.scheduling.base_scheduler import BaseScheduler
+
+
+class ASAPScheduleAnalysis(BaseScheduler):
+    """ASAP Scheduling pass, which schedules the start time of instructions as early as possible.
+
+    See the :ref:`scheduling_stage` section in the :mod:`qiskit.transpiler`
+    module documentation for the detailed behavior of the control flow
+    operation, i.e. ``c_if``.
+    """
+
+    def run(self, dag):
+        """Run the ASAPSchedule pass on `dag`.
+
+        Args:
+            dag (DAGCircuit): DAG to schedule.
+
+        Returns:
+            DAGCircuit: A scheduled DAG.
+
+        Raises:
+            TranspilerError: if the circuit is not mapped on physical qubits.
+            TranspilerError: if conditional bit is added to non-supported instruction.
+        """
+        if len(dag.qregs) != 1 or dag.qregs.get("q", None) is None:
+            raise TranspilerError("ASAP schedule runs on physical circuits only")
+
+        conditional_latency = self.property_set.get("conditional_latency", 0)
+        clbit_write_latency = self.property_set.get("clbit_write_latency", 0)
+
+        node_start_time = {}
+        idle_after = {q: 0 for q in dag.qubits + dag.clbits}
+        for node in dag.topological_op_nodes():
+            op_duration = self._get_node_duration(node, dag)
+
+            # compute t0, t1: instruction interval, note that
+            # t0: start time of instruction
+            # t1: end time of instruction
+            if isinstance(node.op, self.CONDITIONAL_SUPPORTED):
+                t0q = max(idle_after[q] for q in node.qargs)
+                if node.op.condition_bits:
+                    # conditional is bit tricky due to conditional_latency
+                    t0c = max(idle_after[bit] for bit in node.op.condition_bits)
+                    if t0q > t0c:
+                        # This is situation something like below
+                        #
+                        #           |t0q
+                        # Q ▒▒▒▒▒▒▒▒▒░░
+                        # C ▒▒▒░░░░░░░░
+                        #     |t0c
+                        #
+                        # In this case, you can insert readout access before tq0
+                        #
+                        #           |t0q
+                        # Q ▒▒▒▒▒▒▒▒▒▒▒
+                        # C ▒▒▒░░░▒▒░░░
+                        #         |t0q - conditional_latency
+                        #
+                        t0c = max(t0q - conditional_latency, t0c)
+                    t1c = t0c + conditional_latency
+                    for bit in node.op.condition_bits:
+                        # Lock clbit until state is read
+                        idle_after[bit] = t1c
+                    # It starts after register read access
+                    t0 = max(t0q, t1c)
+                else:
+                    t0 = t0q
+                t1 = t0 + op_duration
+            else:
+                if node.op.condition_bits:
+                    raise TranspilerError(
+                        f"Conditional instruction {node.op.name} is not supported in ASAP scheduler."
+                    )
+
+                if isinstance(node.op, Measure):
+                    # measure instruction handling is bit tricky due to clbit_write_latency
+                    t0q = max(idle_after[q] for q in node.qargs)
+                    t0c = max(idle_after[c] for c in node.cargs)
+                    # Assume following case (t0c > t0q)
+                    #
+                    #       |t0q
+                    # Q ▒▒▒▒░░░░░░░░░░░░
+                    # C ▒▒▒▒▒▒▒▒░░░░░░░░
+                    #           |t0c
+                    #
+                    # In this case, there is no actual clbit access until clbit_write_latency.
+                    # The node t0 can be push backward by this amount.
+                    #
+                    #         |t0q' = t0c - clbit_write_latency
+                    # Q ▒▒▒▒░░▒▒▒▒▒▒▒▒▒▒
+                    # C ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒
+                    #           |t0c' = t0c
+                    #
+                    # rather than naively doing
+                    #
+                    #           |t0q' = t0c
+                    # Q ▒▒▒▒░░░░▒▒▒▒▒▒▒▒
+                    # C ▒▒▒▒▒▒▒▒░░░▒▒▒▒▒
+                    #              |t0c' = t0c + clbit_write_latency
+                    #
+                    t0 = max(t0q, t0c - clbit_write_latency)
+                    t1 = t0 + op_duration
+                    for clbit in node.cargs:
+                        idle_after[clbit] = t1
+                else:
+                    # It happens to be directives such as barrier
+                    t0 = max(idle_after[bit] for bit in node.qargs + node.cargs)
+                    t1 = t0 + op_duration
+
+            for bit in node.qargs:
+                idle_after[bit] = t1
+
+            node_start_time[node] = t0
+
+        self.property_set["node_start_time"] = node_start_time

qiskit/transpiler/passes/scheduling/scheduling/base_scheduler.py

@@ -0,0 +1,89 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2020.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Base circuit scheduling pass."""
+
+import warnings
+
+from qiskit.transpiler import InstructionDurations
+from qiskit.transpiler.basepasses import AnalysisPass
+from qiskit.transpiler.passes.scheduling.time_unit_conversion import TimeUnitConversion
+from qiskit.dagcircuit import DAGOpNode, DAGCircuit
+from qiskit.circuit import Delay, Gate
+from qiskit.circuit.parameterexpression import ParameterExpression
+from qiskit.transpiler.exceptions import TranspilerError
+from qiskit.transpiler.target import Target
+
+
+class BaseScheduler(AnalysisPass):
+    """Base scheduler pass."""
+
+    CONDITIONAL_SUPPORTED = (Gate, Delay)
+
+    def __init__(self, durations: InstructionDurations = None, target: Target = None):
+        """Scheduler initializer.
+
+        Args:
+            durations: Durations of instructions to be used in scheduling
+            target: The :class:`~.Target` representing the target backend, if both
+                  ``durations`` and this are specified then this argument will take
+                  precedence and ``durations`` will be ignored.
+
+        """
+        super().__init__()
+        self.durations = durations
+        if target is not None:
+            self.durations = target.durations()
+
+        # Ensure op node durations are attached and in consistent unit
+        self.requires.append(TimeUnitConversion(inst_durations=durations, target=target))
+
+        # Initialize timeslot
+        if "node_start_time" in self.property_set:
+            warnings.warn(
+                "This circuit has been already scheduled. "
+                "The output of previous scheduling pass will be overridden.",
+                UserWarning,
+            )
+        self.property_set["node_start_time"] = {}
+
+    @staticmethod
+    def _get_node_duration(
+        node: DAGOpNode,
+        dag: DAGCircuit,
+    ) -> int:
+        """A helper method to get duration from node or calibration."""
+        indices = [dag.find_bit(qarg).index for qarg in node.qargs]
+
+        if dag.has_calibration_for(node):
+            # If node has calibration, this value should be the highest priority
+            cal_key = tuple(indices), tuple(float(p) for p in node.op.params)
+            duration = dag.calibrations[node.op.name][cal_key].duration
+
+            # Note that node duration is updated (but this is analysis pass)
+            node.op = node.op.to_mutable()
+            node.op.duration = duration
+        else:
+            duration = node.op.duration
+
+        if isinstance(duration, ParameterExpression):
+            raise TranspilerError(
+                f"Parameterized duration ({duration}) "
+                f"of {node.op.name} on qubits {indices} is not bounded."
+            )
+        if duration is None:
+            raise TranspilerError(f"Duration of {node.op.name} on qubits {indices} is not found.")
+
+        return duration
+
+    def run(self, dag: DAGCircuit):
+        raise NotImplementedError

qiskit/transpiler/passes/scheduling/scheduling/set_io_latency.py

@@ -0,0 +1,64 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2022.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+"""Set classical IO latency information to circuit."""
+
+from qiskit.transpiler.basepasses import AnalysisPass
+from qiskit.dagcircuit import DAGCircuit
+
+
+class SetIOLatency(AnalysisPass):
+    """Set IOLatency information to the input circuit.
+
+    The ``clbit_write_latency`` and ``conditional_latency`` are added to
+    the property set of pass manager. This information can be shared among the passes
+    that perform scheduling on instructions acting on classical registers.
+
+    Once these latencies are added to the property set, this information
+    is also copied to the output circuit object as protected attributes,
+    so that it can be utilized outside the transpilation,
+    for example, the timeline visualization can use latency to accurately show
+    time occupation by instructions on the classical registers.
+    """
+
+    def __init__(
+        self,
+        clbit_write_latency: int = 0,
+        conditional_latency: int = 0,
+    ):
+        """Create pass with latency information.
+
+        Args:
+            clbit_write_latency: A control flow constraints. Because standard superconducting
+                quantum processor implement dispersive QND readout, the actual data transfer
+                to the clbit happens after the round-trip stimulus signal is buffered
+                and discriminated into quantum state.
+                The interval ``[t0, t0 + clbit_write_latency]`` is regarded as idle time
+                for clbits associated with the measure instruction.
+                This defaults to 0 dt which is identical to Qiskit Pulse scheduler.
+            conditional_latency: A control flow constraints. This value represents
+                a latency of reading a classical register for the conditional operation.
+                The gate operation occurs after this latency. This appears as a delay
+                in front of the DAGOpNode of the gate.
+                This defaults to 0 dt.
+        """
+        super().__init__()
+        self._conditional_latency = conditional_latency
+        self._clbit_write_latency = clbit_write_latency
+
+    def run(self, dag: DAGCircuit):
+        """Add IO latency information.
+
+        Args:
+            dag: Input DAG circuit.
+        """
+        self.property_set["conditional_latency"] = self._conditional_latency
+        self.property_set["clbit_write_latency"] = self._clbit_write_latency

qiskit/transpiler/passes/scheduling/time_unit_conversion.py

@@ -0,0 +1,135 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2021.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Unify time unit in circuit for scheduling and following passes."""
+from typing import Set
+
+from qiskit.circuit import Delay
+from qiskit.dagcircuit import DAGCircuit
+from qiskit.transpiler.basepasses import TransformationPass
+from qiskit.transpiler.exceptions import TranspilerError
+from qiskit.transpiler.instruction_durations import InstructionDurations
+from qiskit.transpiler.target import Target
+
+
+class TimeUnitConversion(TransformationPass):
+    """Choose a time unit to be used in the following time-aware passes,
+    and make all circuit time units consistent with that.
+
+    This pass will add a :attr:`.Instruction.duration` metadata to each op whose duration is known
+    which will be used by subsequent scheduling passes for scheduling.
+
+    If ``dt`` (in seconds) is known to transpiler, the unit ``'dt'`` is chosen. Otherwise,
+    the unit to be selected depends on what units are used in delays and instruction durations:
+
+    * ``'s'``: if they are all in SI units.
+    * ``'dt'``: if they are all in the unit ``'dt'``.
+    * raise error: if they are a mix of SI units and ``'dt'``.
+    """
+
+    def __init__(self, inst_durations: InstructionDurations = None, target: Target = None):
+        """TimeUnitAnalysis initializer.
+
+        Args:
+            inst_durations (InstructionDurations): A dictionary of durations of instructions.
+            target: The :class:`~.Target` representing the target backend, if both
+                  ``inst_durations`` and ``target`` are specified then this argument will take
+                  precedence and ``inst_durations`` will be ignored.
+
+
+        """
+        super().__init__()
+        self.inst_durations = inst_durations or InstructionDurations()
+        if target is not None:
+            self.inst_durations = target.durations()
+
+    def run(self, dag: DAGCircuit):
+        """Run the TimeUnitAnalysis pass on `dag`.
+
+        Args:
+            dag (DAGCircuit): DAG to be checked.
+
+        Returns:
+            DAGCircuit: DAG with consistent timing and op nodes annotated with duration.
+
+        Raises:
+            TranspilerError: if the units are not unifiable
+        """
+        # Choose unit
+        if self.inst_durations.dt is not None:
+            time_unit = "dt"
+        else:
+            # Check what units are used in delays and other instructions: dt or SI or mixed
+            units_delay = self._units_used_in_delays(dag)
+            if self._unified(units_delay) == "mixed":
+                raise TranspilerError(
+                    "Fail to unify time units in delays. SI units "
+                    "and dt unit must not be mixed when dt is not supplied."
+                )
+            units_other = self.inst_durations.units_used()
+            if self._unified(units_other) == "mixed":
+                raise TranspilerError(
+                    "Fail to unify time units in instruction_durations. SI units "
+                    "and dt unit must not be mixed when dt is not supplied."
+                )
+
+            unified_unit = self._unified(units_delay | units_other)
+            if unified_unit == "SI":
+                time_unit = "s"
+            elif unified_unit == "dt":
+                time_unit = "dt"
+            else:
+                raise TranspilerError(
+                    "Fail to unify time units. SI units "
+                    "and dt unit must not be mixed when dt is not supplied."
+                )
+
+        # Make units consistent
+        for node in dag.op_nodes():
+            try:
+                duration = self.inst_durations.get(
+                    node.op, [dag.find_bit(qarg).index for qarg in node.qargs], unit=time_unit
+                )
+            except TranspilerError:
+                continue
+            node.op = node.op.to_mutable()
+            node.op.duration = duration
+            node.op.unit = time_unit
+
+        self.property_set["time_unit"] = time_unit
+        return dag
+
+    @staticmethod
+    def _units_used_in_delays(dag: DAGCircuit) -> Set[str]:
+        units_used = set()
+        for node in dag.op_nodes(op=Delay):
+            units_used.add(node.op.unit)
+        return units_used
+
+    @staticmethod
+    def _unified(unit_set: Set[str]) -> str:
+        if not unit_set:
+            return "dt"
+
+        if len(unit_set) == 1 and "dt" in unit_set:
+            return "dt"
+
+        all_si = True
+        for unit in unit_set:
+            if not unit.endswith("s"):
+                all_si = False
+                break
+
+        if all_si:
+            return "SI"
+
+        return "mixed"