pyvex 9.2.189__cp312-cp312-win_amd64.whl

pyvex/include/libvex_guest_arm.h

@@ -0,0 +1,224 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin                                libvex_guest_arm.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright (C) 2004-2015 OpenWorks LLP
+      info@open-works.net
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __LIBVEX_PUB_GUEST_ARM_H
+#define __LIBVEX_PUB_GUEST_ARM_H
+
+#include "libvex_basictypes.h"
+
+
+/*---------------------------------------------------------------*/
+/*--- Vex's representation of the ARM CPU state.              ---*/
+/*---------------------------------------------------------------*/
+
+typedef
+   struct {
+      /* 0 */
+      /* Event check fail addr and counter. */
+      UInt host_EvC_FAILADDR; /* 0 */
+      UInt host_EvC_COUNTER;  /* 4 */
+      UInt guest_R0;
+      UInt guest_R1;
+      UInt guest_R2;
+      UInt guest_R3;
+      UInt guest_R4;
+      UInt guest_R5;
+      UInt guest_R6;
+      UInt guest_R7;
+      UInt guest_R8;
+      UInt guest_R9;
+      UInt guest_R10;
+      UInt guest_R11;
+      UInt guest_R12;
+      UInt guest_R13;     /* stack pointer */
+      UInt guest_R14;     /* link register */
+      UInt guest_R15T;
+      /* program counter[31:1] ++ [T], encoding both the current
+         instruction address and the ARM vs Thumb state of the
+         machine.  T==1 is Thumb, T==0 is ARM.  Hence values of the
+         form X--(31)--X1 denote a Thumb instruction at location
+         X--(31)--X0, values of the form X--(30)--X00 denote an ARM
+         instruction at precisely that address, and values of the form
+         X--(30)--10 are invalid since they would imply an ARM
+         instruction at a non-4-aligned address. */
+
+      /* 4-word thunk used to calculate N(sign) Z(zero) C(carry,
+         unsigned overflow) and V(signed overflow) flags. */
+      /* 72 */
+      UInt guest_CC_OP;
+      UInt guest_CC_DEP1;
+      UInt guest_CC_DEP2;
+      UInt guest_CC_NDEP;
+
+      /* A 32-bit value which is used to compute the APSR.Q (sticky
+         saturation) flag, when necessary.  If the value stored here
+         is zero, APSR.Q is currently zero.  If it is any other value,
+         APSR.Q is currently one. */
+      UInt guest_QFLAG32;
+
+      /* 32-bit values to represent APSR.GE0 .. GE3.  Same
+         zero-vs-nonzero scheme as for QFLAG32. */
+      UInt guest_GEFLAG0;
+      UInt guest_GEFLAG1;
+      UInt guest_GEFLAG2;
+      UInt guest_GEFLAG3;
+
+      /* Various pseudo-regs mandated by Vex or Valgrind. */
+      /* Emulation notes */
+      UInt guest_EMNOTE;
+
+      /* For clinval/clflush: record start and length of area */
+      UInt guest_CMSTART;
+      UInt guest_CMLEN;
+
+      /* Used to record the unredirected guest address at the start of
+         a translation whose start has been redirected.  By reading
+         this pseudo-register shortly afterwards, the translation can
+         find out what the corresponding no-redirection address was.
+         Note, this is only set for wrap-style redirects, not for
+         replace-style ones. */
+      UInt guest_NRADDR;
+
+      /* Needed for Darwin (but mandated for all guest architectures):
+         program counter at the last syscall insn (int 0x80/81/82,
+         sysenter, syscall, svc).  Used when backing up to restart a
+         syscall that has been interrupted by a signal. */
+      /* 124 */
+      UInt guest_IP_AT_SYSCALL;
+
+      /* VFP state.  D0 .. D15 must be 8-aligned. */
+      /* 128 */
+      ULong guest_D0;
+      ULong guest_D1;
+      ULong guest_D2;
+      ULong guest_D3;
+      ULong guest_D4;
+      ULong guest_D5;
+      ULong guest_D6;
+      ULong guest_D7;
+      ULong guest_D8;
+      ULong guest_D9;
+      ULong guest_D10;
+      ULong guest_D11;
+      ULong guest_D12;
+      ULong guest_D13;
+      ULong guest_D14;
+      ULong guest_D15;
+      ULong guest_D16;
+      ULong guest_D17;
+      ULong guest_D18;
+      ULong guest_D19;
+      ULong guest_D20;
+      ULong guest_D21;
+      ULong guest_D22;
+      ULong guest_D23;
+      ULong guest_D24;
+      ULong guest_D25;
+      ULong guest_D26;
+      ULong guest_D27;
+      ULong guest_D28;
+      ULong guest_D29;
+      ULong guest_D30;
+      ULong guest_D31;
+      UInt  guest_FPSCR;
+
+      /* Not a town in Cornwall, but instead the TPIDRURO, on of the
+         Thread ID registers present in CP15 (the system control
+         coprocessor), register set "c13", register 3 (the User
+         Read-only Thread ID Register).  arm-linux apparently uses it
+         to hold the TLS pointer for the thread.  It's read-only in
+         user space.  On Linux it is set in user space by various
+         thread-related syscalls. */
+      UInt guest_TPIDRURO;
+
+      /* Representation of the Thumb IT state.  ITSTATE is a 32-bit
+         value with 4 8-bit lanes.  [7:0] pertain to the next insn to
+         execute, [15:8] for the one after that, etc.  The per-insn
+         update to ITSTATE is to unsignedly shift it right 8 bits,
+         hence introducing a zero byte for the furthest ahead
+         instruction.  As per the next para, a zero byte denotes the
+         condition ALWAYS.
+
+         Each byte lane has one of the two following formats:
+
+         cccc 0001  for an insn which is part of an IT block.  cccc is
+                    the guarding condition (standard ARM condition
+                    code) XORd with 0xE, so as to cause 'cccc == 0'
+                    to encode the condition ALWAYS.
+
+         0000 0000  for an insn which is not part of an IT block.
+
+         If the bottom 4 bits are zero then the top 4 must be too.
+
+         Given the byte lane for an instruction, the guarding
+         condition for the instruction is (((lane >> 4) & 0xF) ^ 0xE).
+         This is not as stupid as it sounds, because the front end
+         elides the shift.  And the am-I-in-an-IT-block check is
+         (lane != 0).
+
+         In the case where (by whatever means) we know at JIT time
+         that an instruction is not in an IT block, we can prefix its
+         IR with assignments ITSTATE = 0 and hence have iropt fold out
+         the testing code.
+
+         The condition "is outside or last in IT block" corresponds
+         to the top 24 bits of ITSTATE being zero.
+      */
+      UInt guest_ITSTATE;
+
+      /* Padding to make it have an 16-aligned size */
+      UInt padding1;
+   }
+   VexGuestARMState;
+
+
+/*---------------------------------------------------------------*/
+/*--- Utility functions for ARM guest stuff.                  ---*/
+/*---------------------------------------------------------------*/
+
+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
+
+/* Initialise all guest ARM state. */
+
+extern
+void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state );
+
+/* Calculate the ARM flag state from the saved data. */
+
+extern
+UInt LibVEX_GuestARM_get_cpsr ( /*IN*/const VexGuestARMState* vex_state );
+
+
+#endif /* ndef __LIBVEX_PUB_GUEST_ARM_H */
+
+
+/*---------------------------------------------------------------*/
+/*---                                      libvex_guest_arm.h ---*/
+/*---------------------------------------------------------------*/

pyvex/include/libvex_guest_arm64.h

@@ -0,0 +1,203 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin                              libvex_guest_arm64.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright (C) 2013-2015 OpenWorks
+      info@open-works.net
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __LIBVEX_PUB_GUEST_ARM64_H
+#define __LIBVEX_PUB_GUEST_ARM64_H
+
+#include "libvex_basictypes.h"
+
+
+/*---------------------------------------------------------------*/
+/*--- Vex's representation of the ARM64 CPU state.            ---*/
+/*---------------------------------------------------------------*/
+
+typedef
+   struct {
+      /* Event check fail addr and counter. */
+      /* 0 */  ULong host_EvC_FAILADDR;
+      /* 8 */  UInt  host_EvC_COUNTER;
+      /* 12 */ UInt  pad0;
+      /* 16 */
+      ULong guest_X0;
+      ULong guest_X1;
+      ULong guest_X2;
+      ULong guest_X3;
+      ULong guest_X4;
+      ULong guest_X5;
+      ULong guest_X6;
+      ULong guest_X7;
+      ULong guest_X8;
+      ULong guest_X9;
+      ULong guest_X10;
+      ULong guest_X11;
+      ULong guest_X12;
+      ULong guest_X13;
+      ULong guest_X14;
+      ULong guest_X15;
+      ULong guest_X16;
+      ULong guest_X17;
+      ULong guest_X18;
+      ULong guest_X19;
+      ULong guest_X20;
+      ULong guest_X21;
+      ULong guest_X22;
+      ULong guest_X23;
+      ULong guest_X24;
+      ULong guest_X25;
+      ULong guest_X26;
+      ULong guest_X27;
+      ULong guest_X28;
+      ULong guest_X29;
+      ULong guest_X30;     /* link register */
+      ULong guest_XSP;
+      ULong guest_PC;
+
+      /* 4-word thunk used to calculate N(sign) Z(zero) C(carry,
+         unsigned overflow) and V(signed overflow) flags. */
+      ULong guest_CC_OP;
+      ULong guest_CC_DEP1;
+      ULong guest_CC_DEP2;
+      ULong guest_CC_NDEP;
+
+      /* User-space thread register? */
+      ULong guest_TPIDR_EL0;
+
+      /* FP/SIMD state */
+      U128 guest_Q0;
+      U128 guest_Q1;
+      U128 guest_Q2;
+      U128 guest_Q3;
+      U128 guest_Q4;
+      U128 guest_Q5;
+      U128 guest_Q6;
+      U128 guest_Q7;
+      U128 guest_Q8;
+      U128 guest_Q9;
+      U128 guest_Q10;
+      U128 guest_Q11;
+      U128 guest_Q12;
+      U128 guest_Q13;
+      U128 guest_Q14;
+      U128 guest_Q15;
+      U128 guest_Q16;
+      U128 guest_Q17;
+      U128 guest_Q18;
+      U128 guest_Q19;
+      U128 guest_Q20;
+      U128 guest_Q21;
+      U128 guest_Q22;
+      U128 guest_Q23;
+      U128 guest_Q24;
+      U128 guest_Q25;
+      U128 guest_Q26;
+      U128 guest_Q27;
+      U128 guest_Q28;
+      U128 guest_Q29;
+      U128 guest_Q30;
+      U128 guest_Q31;
+
+      /* A 128-bit value which is used to represent the FPSR.QC (sticky
+         saturation) flag, when necessary.  If the value stored here
+         is zero, FPSR.QC is currently zero.  If it is any other value,
+         FPSR.QC is currently one.  We don't currently represent any 
+         other bits of FPSR, so this is all that that is for FPSR. */
+      U128 guest_QCFLAG;
+
+      /* Various pseudo-regs mandated by Vex or Valgrind. */
+      /* Emulation notes */
+      UInt guest_EMNOTE;
+
+      /* For clflush/clinval: record start and length of area */
+      ULong guest_CMSTART;
+      ULong guest_CMLEN;
+
+      /* Used to record the unredirected guest address at the start of
+         a translation whose start has been redirected.  By reading
+         this pseudo-register shortly afterwards, the translation can
+         find out what the corresponding no-redirection address was.
+         Note, this is only set for wrap-style redirects, not for
+         replace-style ones. */
+      ULong guest_NRADDR;
+
+      /* Needed for Darwin (but mandated for all guest architectures):
+         program counter at the last syscall insn (int 0x80/81/82,
+         sysenter, syscall, svc).  Used when backing up to restart a
+         syscall that has been interrupted by a signal. */
+      ULong guest_IP_AT_SYSCALL;
+
+      /* The complete FPCR.  Default value seems to be zero.  We
+         ignore all bits except 23 and 22, which are the rounding
+         mode.  The guest is unconstrained in what values it can write
+         to and read from this register, but the emulation only takes
+         note of bits 23 and 22. */
+      UInt  guest_FPCR;
+
+      /* Padding to make it have an 16-aligned size */
+      /* UInt  pad_end_0; */
+      /* ULong pad_end_1; */
+   }
+   VexGuestARM64State;
+
+
+/*---------------------------------------------------------------*/
+/*--- Utility functions for ARM64 guest stuff.                ---*/
+/*---------------------------------------------------------------*/
+
+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
+
+/* Initialise all guest ARM64 state. */
+
+extern
+void LibVEX_GuestARM64_initialise ( /*OUT*/VexGuestARM64State* vex_state );
+
+/* Calculate the ARM64 flag state from the saved data, in the format
+   32x0:n:z:c:v:28x0. */
+extern
+ULong LibVEX_GuestARM64_get_nzcv ( /*IN*/
+                                   const VexGuestARM64State* vex_state );
+
+/* Calculate the ARM64 FPSR state from the saved data, in the format
+   36x0:qc:27x0 */
+extern
+ULong LibVEX_GuestARM64_get_fpsr ( /*IN*/
+                                   const VexGuestARM64State* vex_state );
+
+/* Set the ARM64 FPSR representation from the given FPSR value. */
+extern
+void LibVEX_GuestARM64_set_fpsr ( /*MOD*/VexGuestARM64State* vex_state,
+                                  ULong fpsr );
+                                  
+
+#endif /* ndef __LIBVEX_PUB_GUEST_ARM64_H */
+
+
+/*---------------------------------------------------------------*/
+/*---                                    libvex_guest_arm64.h ---*/
+/*---------------------------------------------------------------*/

pyvex/include/libvex_guest_mips32.h

@@ -0,0 +1,175 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin                             libvex_guest_mips32.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright (C) 2010-2015 RT-RK
+      mips-valgrind@rt-rk.com
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __LIBVEX_PUB_GUEST_MIPS32_H
+#define __LIBVEX_PUB_GUEST_MIPS32_H
+
+#include "libvex_basictypes.h"
+
+
+/*---------------------------------------------------------------*/
+/*--- Vex's representation of the MIPS32 CPU state.           ---*/
+/*---------------------------------------------------------------*/
+
+typedef
+   struct {
+      /*    0 */ UInt host_EvC_FAILADDR;
+      /*    4 */ UInt host_EvC_COUNTER;
+
+      /* CPU Registers */
+      /*    8 */ UInt guest_r0;   /* Hardwired to 0. */
+      /*   12 */ UInt guest_r1;   /* Assembler temporary */
+      /*   16 */ UInt guest_r2;   /* Values for function returns ...*/
+      /*   20 */ UInt guest_r3;   /* ... and expression evaluation */
+      /*   24 */ UInt guest_r4;   /* Function arguments */
+      /*   28 */ UInt guest_r5;
+      /*   32 */ UInt guest_r6;
+      /*   36 */ UInt guest_r7;
+      /*   40 */ UInt guest_r8;   /* Temporaries */
+      /*   44 */ UInt guest_r9;
+      /*   48 */ UInt guest_r10;
+      /*   52 */ UInt guest_r11;
+      /*   56 */ UInt guest_r12;
+      /*   60 */ UInt guest_r13;
+      /*   64 */ UInt guest_r14;
+      /*   68 */ UInt guest_r15;
+      /*   72 */ UInt guest_r16;  /* Saved temporaries */
+      /*   76 */ UInt guest_r17;
+      /*   80 */ UInt guest_r18;
+      /*   84 */ UInt guest_r19;
+      /*   88 */ UInt guest_r20;
+      /*   92 */ UInt guest_r21;
+      /*   96 */ UInt guest_r22;
+      /*  100 */ UInt guest_r23;
+      /*  104 */ UInt guest_r24;  /* Temporaries */
+      /*  108 */ UInt guest_r25;
+      /*  112 */ UInt guest_r26;  /* Reserved for OS kernel */
+      /*  116 */ UInt guest_r27;
+      /*  120 */ UInt guest_r28;  /* Global pointer */
+      /*  124 */ UInt guest_r29;  /* Stack pointer */
+      /*  128 */ UInt guest_r30;  /* Frame pointer */
+      /*  132 */ UInt guest_r31;  /* Return address */
+      /*  136 */ UInt guest_PC;   /* Program counter */
+      /*  140 */ UInt guest_HI;   /* Multiply and divide reg higher result */
+      /*  144 */ UInt guest_LO;   /* Multiply and divide reg lower result */
+      /*  148 */ UInt _padding1;
+
+      /* FPU Registers */
+      /*  152 */ ULong guest_f0;  /* Floating point general purpose registers */
+      /*  160 */ ULong guest_f1;
+      /*  168 */ ULong guest_f2;
+      /*  176 */ ULong guest_f3;
+      /*  184 */ ULong guest_f4;
+      /*  192 */ ULong guest_f5;
+      /*  200 */ ULong guest_f6;
+      /*  208 */ ULong guest_f7;
+      /*  216 */ ULong guest_f8;
+      /*  224 */ ULong guest_f9;
+      /*  232 */ ULong guest_f10;
+      /*  240 */ ULong guest_f11;
+      /*  248 */ ULong guest_f12;
+      /*  256 */ ULong guest_f13;
+      /*  264 */ ULong guest_f14;
+      /*  272 */ ULong guest_f15;
+      /*  280 */ ULong guest_f16;
+      /*  288 */ ULong guest_f17;
+      /*  296 */ ULong guest_f18;
+      /*  304 */ ULong guest_f19;
+      /*  312 */ ULong guest_f20;
+      /*  320 */ ULong guest_f21;
+      /*  328 */ ULong guest_f22;
+      /*  336 */ ULong guest_f23;
+      /*  344 */ ULong guest_f24;
+      /*  352 */ ULong guest_f25;
+      /*  360 */ ULong guest_f26;
+      /*  368 */ ULong guest_f27;
+      /*  376 */ ULong guest_f28;
+      /*  384 */ ULong guest_f29;
+      /*  392 */ ULong guest_f30;
+      /*  400 */ ULong guest_f31;
+
+      /*  408 */ UInt guest_FIR;
+      /*  412 */ UInt guest_FCCR;
+      /*  416 */ UInt guest_FEXR;
+      /*  420 */ UInt guest_FENR;
+      /*  424 */ UInt guest_FCSR;
+
+      /* TLS pointer for the thread. It's read-only in user space.
+         On Linux it is set in user space by various thread-related
+         syscalls.
+         User Local Register.
+         This register provides read access to the coprocessor 0
+         UserLocal register, if it is implemented. In some operating
+         environments, the UserLocal register is a pointer to a
+         thread-specific storage block.
+      */
+      /*  428 */ UInt guest_ULR;
+
+      /* Emulation notes */
+      /*  432 */ UInt guest_EMNOTE;
+
+      /* For clflush: record start and length of area to invalidate. */
+      /*  436 */ UInt guest_CMSTART;
+      /*  440 */ UInt guest_CMLEN;
+      /*  444 */ UInt guest_NRADDR;
+
+      /*  448 */ UInt guest_COND;
+
+      /* MIPS32 DSP ASE(r2) specific registers. */
+      /*  452 */ UInt guest_DSPControl;
+      /*  456 */ ULong guest_ac0;
+      /*  464 */ ULong guest_ac1;
+      /*  472 */ ULong guest_ac2;
+      /*  480 */ ULong guest_ac3;
+
+      /*  488 */ UInt guest_CP0_status;
+
+      /*  492 */ UInt guest_IP_AT_SYSCALL;
+} VexGuestMIPS32State;
+/*---------------------------------------------------------------*/
+/*--- Utility functions for MIPS32 guest stuff.               ---*/
+/*---------------------------------------------------------------*/
+
+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT. */
+
+/* Initialise all guest MIPS32 state. */
+
+extern
+void LibVEX_GuestMIPS32_initialise ( /*OUT*/VexGuestMIPS32State* vex_state );
+
+/* FR bit of CP0_STATUS_FR register */
+#define MIPS_CP0_STATUS_FR (1ul << 26)
+
+#endif /* ndef __LIBVEX_PUB_GUEST_MIPS32_H */
+
+
+/*---------------------------------------------------------------*/
+/*---                                   libvex_guest_mips32.h ---*/
+/*---------------------------------------------------------------*/