pyvex 9.2.189__cp312-cp312-win_amd64.whl

pyvex/const.py

@@ -0,0 +1,426 @@
+# pylint:disable=missing-class-docstring,raise-missing-from,not-callable
+import re
+from abc import ABC
+
+from .enums import VEXObject, get_enum_from_int
+from .errors import PyVEXError
+from .native import ffi, pvc
+
+
+# IRConst hierarchy
+class IRConst(VEXObject, ABC):
+    __slots__ = ["_value"]
+
+    type: str
+    size: int
+    tag: str
+    c_constructor = None
+    _value: int
+
+    def pp(self):
+        print(str(self))
+
+    @property
+    def value(self) -> int:
+        return self._value
+
+    @staticmethod
+    def _from_c(c_const):
+        if c_const[0] == ffi.NULL:
+            return None
+
+        tag = get_enum_from_int(c_const.tag)
+
+        try:
+            return tag_to_const_class(tag)._from_c(c_const)
+        except KeyError:
+            raise PyVEXError("Unknown/unsupported IRConstTag %s\n" % tag)
+
+    _translate = _from_c
+
+    @classmethod
+    def _to_c(cls, const):
+        # libvex throws an exception when constructing a U1 with a value other than 0 or 1
+        if const.tag == "Ico_U1" and const.value not in (0, 1):
+            raise PyVEXError("Invalid U1 value: %d" % const.value)
+
+        try:
+            return cls.c_constructor(const.value)
+        except KeyError:
+            raise PyVEXError("Unknown/unsupported IRConstTag %s]n" % const.tag)
+
+    def __eq__(self, other):
+        if not isinstance(other, type(self)):
+            return False
+        return self._value == other._value
+
+    def __hash__(self):
+        return hash((type(self), self._value))
+
+
+class U1(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_I1"
+    size = 1
+    tag = "Ico_U1"
+    op_format = "1"
+    c_constructor = pvc.IRConst_U1
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "%d" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        return U1(c_const.Ico.U1)
+
+
+class U8(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_I8"
+    size = 8
+    tag = "Ico_U8"
+    op_format = "8"
+    c_constructor = pvc.IRConst_U8
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "0x%02x" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        return _U8_POOL[c_const.Ico.U8]
+
+
+_U8_POOL = [U8(i) for i in range(256)]
+
+
+class U16(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_I16"
+    size = 16
+    tag = "Ico_U16"
+    op_format = "16"
+    c_constructor = pvc.IRConst_U16
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "0x%04x" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        val = c_const.Ico.U16
+        if val < 1024:
+            return _U16_POOL[val]
+        if val >= 0xFC00:
+            return _U16_POOL[val - 0xFC00 + 1024]
+        return U16(val)
+
+
+_U16_POOL = [U16(i) for i in range(1024)] + [U16(i) for i in range(0xFC00, 0xFFFF + 1)]
+
+
+class U32(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_I32"
+    size = 32
+    tag = "Ico_U32"
+    op_format = "32"
+    c_constructor = pvc.IRConst_U32
+
+    def __init__(self, value: int):
+        self._value = value
+
+    def __str__(self):
+        return "0x%08x" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        val = c_const.Ico.U32
+        if val < 1024:
+            return _U32_POOL[val]
+        if val >= 0xFFFFFC00:
+            return _U32_POOL[val - 0xFFFFFC00 + 1024]
+        return U32(val)
+
+
+_U32_POOL = [U32(i) for i in range(1024)] + [U32(i) for i in range(0xFFFFFC00, 0xFFFFFFFF + 1)]
+
+
+class U64(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_I64"
+    size = 64
+    tag = "Ico_U64"
+    op_format = "64"
+    c_constructor = pvc.IRConst_U64
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "0x%016x" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        val = c_const.Ico.U64
+        if val < 1024:
+            return _U64_POOL[val]
+        if val >= 0xFFFFFFFFFFFFFC00:
+            return _U64_POOL[val - 0xFFFFFFFFFFFFFC00 + 1024]
+        return U64(val)
+
+
+_U64_POOL = [U64(i) for i in range(1024)] + [U64(i) for i in range(0xFFFFFFFFFFFFFC00, 0xFFFFFFFFFFFFFFFF + 1)]
+
+# Integer Type Imagination
+class_cache = {1: U1, 8: U8, 16: U16, 32: U32, 64: U64}
+
+
+def vex_int_class(size):
+    try:
+        return class_cache[size]
+    except KeyError:
+
+        class VexInt(IRConst):
+            type = "Ity_I%d" % size
+            tag = "Ico_U%d" % size
+            op_format = str(size)
+
+            def __init__(self, value):
+                IRConst.__init__(self)
+                self._value = value
+
+            def __str__(self):
+                return f"(0x{self.value:x} :: {self.type})"
+
+        VexInt.__name__ = "U%d" % size
+        class_cache[size] = VexInt
+        return VexInt
+
+
+class F32(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_F32"
+    tag = "Ico_F32"
+    op_format = "F32"
+    c_constructor = pvc.IRConst_F32
+    size = 32
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "%f" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        return F32(c_const.Ico.F32)
+
+
+class F32i(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_F32"
+    tag = "Ico_F32i"
+    op_format = "F32"
+    c_constructor = pvc.IRConst_F32i
+    size = 32
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "%f" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        return F32i(c_const.Ico.F32)
+
+
+class F64(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_F64"
+    tag = "Ico_F64"
+    op_format = "F64"
+    c_constructor = pvc.IRConst_F64
+    size = 64
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "%f" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        return F64(c_const.Ico.F64)
+
+
+class F64i(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_F64"
+    tag = "Ico_F64i"
+    op_format = "F64"
+    c_constructor = pvc.IRConst_F64i
+    size = 64
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "%f" % self.value
+
+    @staticmethod
+    def _from_c(c_const):
+        return F64i(c_const.Ico.F64)
+
+
+class V128(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_V128"
+    tag = "Ico_V128"
+    op_format = "V128"
+    c_constructor = pvc.IRConst_V128
+    size = 128
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "%x" % self.value
+
+    # vex doesn't store a full 128 bit constant, instead it stores 1 bit per 8 bits of data
+    # and duplicates each bit 8 times
+    @staticmethod
+    def _from_c(c_const):
+        base_const = c_const.Ico.V128
+        real_const = 0
+        for i in range(16):
+            if (base_const >> i) & 1 == 1:
+                real_const |= 0xFF << (8 * i)
+        return V128(real_const)
+
+
+class V256(IRConst):
+    __slots__: list[str] = []
+
+    type = "Ity_V256"
+    tag = "Ico_V256"
+    op_format = "V256"
+    c_constructor = pvc.IRConst_V256
+    size = 256
+
+    def __init__(self, value):
+        self._value = value
+
+    def __str__(self):
+        return "%x" % self.value
+
+    # see above
+    @staticmethod
+    def _from_c(c_const):
+        base_const = c_const.Ico.V256
+        real_const = 0
+        for i in range(32):
+            if (base_const >> i) & 1 == 1:
+                real_const |= 0xFF << (8 * i)
+        return V256(real_const)
+
+
+predefined_types = [U1, U8, U16, U32, U64, F32, F32i, F64, F64i, V128, V256]
+predefined_types_map = {c.type: c for c in predefined_types}
+predefined_classes_map = {c.tag: c for c in predefined_types}
+
+# precompiled regexes
+int_ty_re = re.compile(r"Ity_I\d+")
+int_tag_re = re.compile(r"Ico_U\d+")
+tag_size_re = re.compile(r"Ico_[UFV](?P<size>\d+)i?")
+
+
+def is_int_ty(ty):
+    m = int_ty_re.match(ty)
+    return m is not None
+
+
+def is_int_tag(tag):
+    m = int_tag_re.match(tag)
+    return m is not None
+
+
+def get_tag_size(tag):
+    m = tag_size_re.match(tag)
+    if m is None:
+        raise ValueError("Tag %s does not have size" % tag)
+    return int(m.group("size"))
+
+
+type_str_re = re.compile(r"Ity_[IFDV](?P<size>\d+)")
+type_tag_str_re = re.compile(r"[IFDV]?(?P<size>\d+)[SU]?")
+
+
+def get_type_size(ty):
+    """
+    Returns the size, in BITS, of a VEX type specifier
+    e.g., Ity_I16 -> 16
+
+    :param ty:
+    :return:
+    """
+    m = type_str_re.match(ty)
+    if m is None:
+        raise ValueError("Type %s does not have size" % ty)
+    return int(m.group("size"))
+
+
+def get_type_spec_size(ty):
+    """
+    Get the width of a "type specifier"
+    like I16U
+    or F16
+    or just 16
+    (Yes, this really just takes the int out.  If we must special-case, do it here.
+    :param tyspec:
+    :return:
+    """
+    m = type_tag_str_re.match(ty)
+    if m is None:
+        raise ValueError("Type specifier %s does not have size" % ty)
+    return int(m.group("size"))
+
+
+def ty_to_const_class(ty):
+    try:
+        return predefined_types_map[ty]
+    except KeyError:
+        if is_int_ty(ty):
+            size = get_type_size(ty)
+            return vex_int_class(size)
+        else:
+            raise ValueError("Type %s does not exist" % ty)
+
+
+def tag_to_const_class(tag):
+    try:
+        return predefined_classes_map[tag]
+    except KeyError:
+        if is_int_tag(tag):
+            size = get_tag_size(tag)
+            return vex_int_class(size)
+        else:
+            raise ValueError("Tag %s does not exist" % tag)

pyvex/const_val.py

@@ -0,0 +1,26 @@
+class ConstVal:
+    """
+    A constant value object. Indicates a constant value assignment to a VEX tmp variable.
+
+    :ivar tmp:          The tmp variable being assigned to.
+    :ivar value:        The value of the tmp variable.
+    :ivar stmt_idx:     The IRSB statement index containing the data access
+    """
+
+    __slots__ = (
+        "tmp",
+        "value",
+        "stmt_idx",
+    )
+
+    def __init__(self, tmp: int, value: int, stmt_idx: int):
+        self.tmp = tmp
+        self.value = value
+        self.stmt_idx = stmt_idx
+
+    def __repr__(self):
+        return f"<ConstVal {self.tmp} = {self.value:#x} @ {self.stmt_idx}>"
+
+    @classmethod
+    def from_c(cls, r):
+        return cls(r.tmp, r.value, r.stmt_idx)

pyvex/data_ref.py

@@ -0,0 +1,55 @@
+def data_ref_type_str(dref_enum):
+    """
+    Translate an ``enum DataRefTypes`` value into a string representation.
+    """
+    if dref_enum == 0x9000:
+        return "unknown"
+    elif dref_enum == 0x9001:
+        return "integer"
+    elif dref_enum == 0x9002:
+        return "fp"
+    elif dref_enum == 0x9003:
+        return "integer(store)"
+    else:
+        return "INVALID"
+
+
+class DataRef:
+    """
+    A data reference object. Indicates a data access in an IRSB.
+
+    :ivar data_addr:    The address of the data being accessed
+    :ivar data_size:    The size of the data being accessed, in bytes
+    :ivar data_type:    The type of the data, a DataRefTypes enum.
+    :ivar stmt_idx:     The IRSB statement index containing the data access
+    :ivar ins_addr:     The address of the instruction performing the data access
+    """
+
+    __slots__ = ("data_addr", "data_size", "data_type", "stmt_idx", "ins_addr")
+
+    def __init__(self, data_addr, data_size, data_type, stmt_idx, ins_addr):
+        self.data_addr = data_addr
+        self.data_size = data_size
+        self.data_type = data_type
+        self.stmt_idx = stmt_idx
+        self.ins_addr = ins_addr
+
+    @property
+    def data_type_str(self):
+        """
+        The data ref type as a string, "unknown" "integer" "fp" or "INVALID"
+        """
+        return data_ref_type_str(self.data_type)
+
+    def __repr__(self):
+        return "<DataRef accessing %#x %s:%d at %#x:%d>" % (
+            self.data_addr,
+            data_ref_type_str(self.data_type),
+            self.data_size,
+            self.ins_addr,
+            self.stmt_idx,
+        )
+
+    @classmethod
+    def from_c(cls, r):
+        return cls(r.data_addr, r.size, r.data_type, r.stmt_idx, r.ins_addr)

pyvex/enums.py

@@ -0,0 +1,156 @@
+from typing import Any
+
+from .native import ffi, pvc
+from .utils import stable_hash
+
+
+class VEXObject:
+    """
+    The base class for Vex types.
+    """
+
+    __slots__: list[str] = []
+
+    def __eq__(self, other):
+        if not isinstance(other, type(self)):
+            return False
+        # compare values in slots
+        for slot in self.__slots__:
+            if getattr(self, slot) != getattr(other, slot):
+                return False
+        return True
+
+    def __hash__(self):
+        values = [getattr(self, slot) for slot in self.__slots__]
+        for i, lst_val in enumerate(values):
+            if isinstance(lst_val, list):
+                values[i] = tuple(lst_val)
+        return stable_hash(tuple([type(self)] + values))
+
+
+class IRCallee(VEXObject):
+    """
+    Describes a helper function to call.
+    """
+
+    __slots__ = ["regparms", "name", "mcx_mask"]
+
+    def __init__(self, regparms, name, mcx_mask):
+        VEXObject.__init__(self)
+        self.regparms = regparms
+        self.name = name
+        self.mcx_mask = mcx_mask
+
+    def __str__(self):
+        return str(self.name)
+
+    @staticmethod
+    def _from_c(c_callee):
+        return IRCallee(
+            c_callee.regparms,
+            ffi.string(c_callee.name).decode(),
+            # NO. #int(ffi.cast("unsigned long long", c_callee.addr)),
+            c_callee.mcx_mask,
+        )
+
+    @staticmethod
+    def _to_c(callee):  # pylint: disable=unused-argument
+        raise TypeError(
+            "This doesn't work! Please invent a way to get the correct address for the named function from pyvex_c."
+        )
+        # c_callee = pvc.mkIRCallee(callee.regparms,
+        #                          callee.name.encode(),
+        #                          ffi.cast("void *", callee.addr))
+        # c_callee.mcx_mask = callee.mcx_mask
+        # return c_callee
+
+
+class IRRegArray(VEXObject):
+    """
+    A section of the guest state that we want te be able to index at run time, so as to be able to describe indexed or
+    rotating register files on the guest.
+
+    :ivar int base:     The offset into the state that this array starts
+    :ivar str elemTy:   The types of the elements in this array, as VEX enum strings
+    :ivar int nElems:   The number of elements in this array
+    """
+
+    __slots__ = ["base", "elemTy", "nElems"]
+
+    def __init__(self, base, elemTy, nElems):
+        VEXObject.__init__(self)
+        self.base = base
+        self.elemTy = elemTy
+        self.nElems = nElems
+
+    def __str__(self):
+        return "%s:%sx%d" % (self.base, self.elemTy[4:], self.nElems)
+
+    @staticmethod
+    def _from_c(c_arr):
+        return IRRegArray(c_arr.base, ints_to_enums[c_arr.elemTy], c_arr.nElems)
+
+    @staticmethod
+    def _to_c(arr):
+        return pvc.mkIRRegArray(arr.base, get_int_from_enum(arr.elemTy), arr.nElems)
+
+
+ints_to_enums: dict[int, str] = {}
+enums_to_ints: dict[str, int] = {}
+irop_enums_to_ints: dict[str, int] = {}
+will_be_overwritten = ["Ircr_GT", "Ircr_LT"]
+
+
+def get_enum_from_int(i):
+    return ints_to_enums[i]
+
+
+def get_int_from_enum(e):
+    return enums_to_ints[e]
+
+
+_add_enum_counter = 0
+
+
+def _add_enum(s, i=None):  # TODO get rid of this
+    global _add_enum_counter  # pylint: disable=global-statement
+    if i is None:
+        while _add_enum_counter in ints_to_enums:
+            _add_enum_counter += 1
+        i = _add_enum_counter
+        _add_enum_counter += 1  # Update for the next iteration
+    if i in ints_to_enums:
+        if ints_to_enums[i] not in will_be_overwritten:
+            raise ValueError("Enum with intkey %d already present" % i)
+    enums_to_ints[s] = i
+    ints_to_enums[i] = s
+    if s.startswith("Iop_"):
+        irop_enums_to_ints[s] = i
+
+
+for attr in dir(pvc):
+    if attr[0] in "ABCDEFGHIJKLMNOPQRSTUVWXYZ" and hasattr(pvc, attr) and isinstance(getattr(pvc, attr), int):
+        _add_enum(attr, getattr(pvc, attr))
+
+
+def vex_endness_from_string(endness_str):
+    return getattr(pvc, endness_str)
+
+
+def default_vex_archinfo() -> dict[str, Any]:
+    return {
+        "hwcaps": 0,
+        "endness": vex_endness_from_string("VexEndnessLE"),
+        "ppc_icache_line_szB": 0,
+        "ppc_dcbz_szB": 0,
+        "ppc_dcbzl_szB": 0,
+        "arm64_dMinLine_lg2_szB": 0,
+        "arm64_iMinLine_lg2_szB": 0,
+        "hwcache_info": {
+            "num_levels": 0,
+            "num_caches": 0,
+            "caches": None,
+            "icaches_maintain_coherence": True,
+        },
+        "x86_cr0": 0xFFFFFFFF,
+    }

pyvex/errors.py

@@ -0,0 +1,31 @@
+class PyVEXError(Exception):
+    pass
+
+
+class SkipStatementsError(PyVEXError):
+    pass
+
+
+#
+# Exceptions and notifications that post-processors can raise
+#
+
+
+class LiftingException(Exception):
+    pass
+
+
+class NeedStatementsNotification(LiftingException):
+    """
+    A post-processor may raise a NeedStatementsNotification if it needs to work with statements, but the current IRSB
+    is generated without any statement available (skip_stmts=True). The lifter will re-lift the current block with
+    skip_stmts=False upon catching a NeedStatementsNotification, and re-run the post-processors.
+
+    It's worth noting that if a post-processor always raises this notification for every basic block without statements,
+    it will essentially disable the skipping statement optimization, and it is bad for performance (especially for
+    CFGFast, which heavily relies on this optimization). Post-processor authors are encouraged to at least filter the
+    IRSBs based on available properties (jumpkind, next, etc.). If a post-processor must work with statements for the
+    majority of IRSBs, the author should implement it in PyVEX in C for the sake of a better performance.
+    """
+
+    pass