pyvex 9.2.189__cp312-cp312-win_amd64.whl

pyvex/include/libvex_s390x_common.h

@@ -0,0 +1,123 @@
+/* -*- mode: C; c-basic-offset: 3; -*- */
+
+/*--------------------------------------------------------------------*/
+/*--- Common defs for s390x                  libvex_s390x_common.h ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright IBM Corp. 2010-2017
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/
+
+#ifndef __LIBVEX_PUB_S390X_H
+#define __LIBVEX_PUB_S390X_H
+
+/* This file includes definitions for s390.
+
+   It must be suitable for inclusion in assembler source files. */
+
+
+/*--------------------------------------------------------------*/
+/*--- Dedicated registers                                    ---*/
+/*--------------------------------------------------------------*/
+
+#define S390_REGNO_RETURN_VALUE         2
+#define S390_REGNO_TCHAIN_SCRATCH      12
+#define S390_REGNO_GUEST_STATE_POINTER 13
+#define S390_REGNO_LINK_REGISTER       14
+#define S390_REGNO_STACK_POINTER       15
+
+
+/*--------------------------------------------------------------*/
+/*--- Offsets in the stack frame allocated by the dispatcher ---*/
+/*--------------------------------------------------------------*/
+
+/* Dispatcher will save 8 FPRs at offsets 160 + 0 ... 160 + 56 */
+
+/* Where the dispatcher saves the r2 contents. */
+#define S390_OFFSET_SAVED_R2 160+80
+
+/* Where client's FPC register is saved. */
+#define S390_OFFSET_SAVED_FPC_C 160+72
+
+/* Where valgrind's FPC register is saved. */
+#define S390_OFFSET_SAVED_FPC_V 160+64
+
+/* Size of frame allocated by VG_(disp_run_translations)
+   Need size for
+       8 FPRs
+     + 1 GPR  (SAVED_R2)
+     + 2 FPCs (SAVED_FPC_C and SAVED_FPC_V).
+
+   Additionally, we need a standard frame for helper functions being called
+   from client code. (See figure 1-16 in zSeries ABI) */
+#define S390_INNERLOOP_FRAME_SIZE ((8+1+2)*8 + 160)
+
+
+/*--------------------------------------------------------------*/
+/*--- Facility bits                                          ---*/
+/*--------------------------------------------------------------*/
+
+/* The value of the macro is the number of the facility bit as per POP. */
+#define S390_FAC_MSA     17  // message-security-assist
+#define S390_FAC_LDISP   18  // long displacement
+#define S390_FAC_HFPMAS  20  // HFP multiply-and-add-subtract
+#define S390_FAC_EIMM    21  // extended immediate
+#define S390_FAC_HFPUNX  23  // HFP unnormalized extension
+#define S390_FAC_ETF2    24  // ETF2-enhancement
+#define S390_FAC_STCKF   25  // store clock fast insn
+#define S390_FAC_PENH    26  // parsing-enhancement
+#define S390_FAC_ETF3    30  // ETF3-enhancement
+#define S390_FAC_XCPUT   31  // extract-CPU-time
+#define S390_FAC_GIE     34  // general insn extension
+#define S390_FAC_EXEXT   35  // execute extension
+#define S390_FAC_FPEXT   37  // floating-point extension
+#define S390_FAC_FPSE    41  // floating-point support enhancement
+#define S390_FAC_DFP     42  // decimal floating point
+#define S390_FAC_PFPO    44  // perform floating point operation insn
+#define S390_FAC_HIGHW   45  // high-word extension
+#define S390_FAC_LSC     45  // load/store on condition
+#define S390_FAC_DFPZC   48  // DFP zoned-conversion
+#define S390_FAC_MISC    49  // miscellaneous insn
+#define S390_FAC_CTREXE  50  // constrained transactional execution
+#define S390_FAC_LSC2    53  // load/store on condition 2 and load and zero rightmost byte
+#define S390_FAC_MSA5    57  // message-security-assist 5
+#define S390_FAC_TREXE   73  // transactional execution
+#define S390_FAC_MSA4    77  // message-security-assist 4
+#define S390_FAC_VX      129 // vector facility
+
+
+/*--------------------------------------------------------------*/
+/*--- Miscellaneous                                          ---*/
+/*--------------------------------------------------------------*/
+
+/* Number of arguments that can be passed in registers */
+#define S390_NUM_GPRPARMS 5
+
+/* Number of double words needed to store all facility bits. */
+#define S390_NUM_FACILITY_DW 3
+
+#endif /* __LIBVEX_PUB_S390X_H */
+
+/*--------------------------------------------------------------------*/
+/*--- end                                    libvex_s390x_common.h ---*/
+/*--------------------------------------------------------------------*/

pyvex/include/libvex_trc_values.h

@@ -0,0 +1,99 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin                               libvex_trc_values.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright (C) 2004-2015 OpenWorks LLP
+      info@open-works.net
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+
+   Neither the names of the U.S. Department of Energy nor the
+   University of California nor the names of its contributors may be
+   used to endorse or promote products derived from this software
+   without prior written permission.
+*/
+
+#ifndef __LIBVEX_TRC_VALUES_H
+#define __LIBVEX_TRC_VALUES_H
+
+
+/* Magic values that the guest state pointer might be set to when
+   returning to the dispatcher.  The only other legitimate value is to
+   point to the start of the thread's VEX guest state.
+
+   This file may get included in assembly code, so do not put
+   C-specific constructs in it.
+
+   These values should be 61 or above so as not to conflict
+   with Valgrind's VG_TRC_ values, which are 60 or below.
+*/
+
+#define VEX_TRC_JMP_INVALICACHE 61  /* invalidate icache (translations)
+                                       before continuing */
+#define VEX_TRC_JMP_FLUSHDCACHE 103 /* flush dcache before continuing */
+
+#define VEX_TRC_JMP_NOREDIR    81  /* jump to undirected guest addr */
+#define VEX_TRC_JMP_SIGTRAP    85  /* deliver trap (SIGTRAP) before
+                                      continuing */
+#define VEX_TRC_JMP_SIGSEGV    87  /* deliver segv (SIGSEGV) before
+                                      continuing */
+#define VEX_TRC_JMP_SIGBUS     93  /* deliver SIGBUS before continuing */
+#define VEX_TRC_JMP_SIGFPE    105  /* deliver SIGFPE before continuing */
+
+#define VEX_TRC_JMP_SIGFPE_INTDIV     97  /* deliver SIGFPE (integer divide
+                                             by zero) before continuing */
+
+#define VEX_TRC_JMP_SIGFPE_INTOVF     99  /* deliver SIGFPE (integer overflow)
+                                             before continuing */
+
+#define VEX_TRC_JMP_SIGILL     101  /* deliver SIGILL (Illegal instruction)
+                                       before continuing */
+
+#define VEX_TRC_JMP_EMWARN     63  /* deliver emulation warning before
+                                      continuing */
+#define VEX_TRC_JMP_EMFAIL     83  /* emulation fatal error; abort system */
+
+#define VEX_TRC_JMP_CLIENTREQ  65  /* do a client req before continuing */
+#define VEX_TRC_JMP_YIELD      67  /* yield to thread sched 
+                                      before continuing */
+#define VEX_TRC_JMP_NODECODE   69  /* next instruction is not decodable */
+#define VEX_TRC_JMP_MAPFAIL    71  /* address translation failed */
+
+#define VEX_TRC_JMP_SYS_SYSCALL  73 /* do syscall before continuing */
+#define VEX_TRC_JMP_SYS_INT32    75 /* do syscall before continuing */
+#define VEX_TRC_JMP_SYS_INT128   77 /* do syscall before continuing */
+#define VEX_TRC_JMP_SYS_INT129   89 /* do syscall before continuing */
+#define VEX_TRC_JMP_SYS_INT130   91 /* do syscall before continuing */
+#define VEX_TRC_JMP_SYS_INT145  111 /* do syscall before continuing */
+#define VEX_TRC_JMP_SYS_INT210  113 /* do syscall before continuing */
+
+#define VEX_TRC_JMP_SYS_SYSENTER 79 /* do syscall before continuing */
+
+#define VEX_TRC_JMP_BORING       95 /* return to sched, but just 
+                                       keep going; no special action */
+
+#endif /* ndef __LIBVEX_TRC_VALUES_H */
+
+/*---------------------------------------------------------------*/
+/*---                                     libvex_trc_values.h ---*/
+/*---------------------------------------------------------------*/

pyvex/include/pyvex.h

@@ -0,0 +1,96 @@
+// This code is GPLed by Yan Shoshitaishvili
+
+#ifndef __VEXIR_H
+#define __VEXIR_H
+
+#include <libvex.h>
+
+// Some info required for translation
+extern int log_level;
+extern VexTranslateArgs    vta;
+
+extern char *msg_buffer;
+extern size_t msg_current_size;
+void clear_log(void);
+
+//
+// Initializes VEX. This function must be called before vex_lift
+// can be used.
+//
+int vex_init(void);
+
+typedef struct _ExitInfo {
+	Int stmt_idx;
+	Addr ins_addr;
+	IRStmt *stmt;
+} ExitInfo;
+
+typedef enum {
+	Dt_Unknown = 0x9000,
+	Dt_Integer,
+	Dt_FP,
+	Dt_StoreInteger
+} DataRefTypes;
+
+typedef struct _DataRef {
+	Addr data_addr;
+	Int size;
+	DataRefTypes data_type;
+	Int stmt_idx;
+	Addr ins_addr;
+} DataRef;
+
+typedef struct _ConstVal {
+	Int tmp;
+	Int stmt_idx;
+	ULong value;  // 64-bit max
+} ConstVal;
+
+#define MAX_EXITS 400
+#define MAX_DATA_REFS 2000
+#define MAX_CONST_VALS 1000
+
+typedef struct _VEXLiftResult {
+	IRSB* irsb;
+	Int size;
+	Bool is_noop_block;
+	// Conditional exits
+	Int exit_count;
+	ExitInfo exits[MAX_EXITS];
+	// The default exit
+	Int is_default_exit_constant;
+	Addr default_exit;
+	// Instruction addresses
+	Int insts;
+	Addr inst_addrs[200];
+	// Data references
+	Int data_ref_count;
+	DataRef data_refs[MAX_DATA_REFS];
+	// Constant propagation
+	Int const_val_count;
+	ConstVal const_vals[MAX_CONST_VALS];
+} VEXLiftResult;
+
+VEXLiftResult *vex_lift(
+		VexArch guest,
+		VexArchInfo archinfo,
+		unsigned char *insn_start,
+		unsigned long long insn_addr,
+		unsigned int max_insns,
+		unsigned int max_bytes,
+		int opt_level,
+		int traceflags,
+		int allow_arch_optimizations,
+		int strict_block_end,
+		int collect_data_refs,
+		int load_from_ro_regions,
+		int const_prop,
+		VexRegisterUpdates px_control,
+		unsigned int lookback_amount);
+
+Bool register_readonly_region(ULong start, ULong size, unsigned char* content);
+void deregister_all_readonly_regions();
+Bool register_initial_register_value(UInt offset, UInt size, ULong value);
+Bool reset_initial_register_values();
+
+#endif

pyvex/lifting/__init__.py

@@ -0,0 +1,18 @@
+from .gym import AARCH64Spotter, AMD64Spotter, ARMSpotter, X86Spotter
+from .libvex import LIBVEX_SUPPORTED_ARCHES, LibVEXLifter
+from .lift_function import lift, lifters, register
+from .lifter import Lifter
+from .post_processor import Postprocessor
+from .zerodivision import ZeroDivisionPostProcessor
+
+for arch in LIBVEX_SUPPORTED_ARCHES:
+    register(LibVEXLifter, arch)
+register(AARCH64Spotter, "AARCH64")
+register(ARMSpotter, "ARM")
+register(ARMSpotter, "ARMEL")
+register(ARMSpotter, "ARMHF")
+register(ARMSpotter, "ARMCortexM")
+register(AMD64Spotter, "AMD64")
+register(X86Spotter, "X86")
+
+__all__ = ["Lifter", "Postprocessor", "lift", "register", "lifters", "ZeroDivisionPostProcessor"]

pyvex/lifting/gym/README.md

@@ -0,0 +1,7 @@
+# The Gym
+
+This is where we're putting non-libvex lifters that we feel should be included with the pyvex distribution.
+
+These will probably be mostly "spotters", which correct for gaps in libvex's instruction support.
+
+

pyvex/lifting/gym/__init__.py

@@ -0,0 +1,5 @@
+from .aarch64_spotter import AARCH64Spotter
+from .arm_spotter import ARMSpotter
+from .x86_spotter import AMD64Spotter, X86Spotter
+
+__all__ = ("ARMSpotter", "AARCH64Spotter", "X86Spotter", "AMD64Spotter")

pyvex/lifting/gym/aarch64_spotter.py

@@ -0,0 +1,40 @@
+import logging
+
+from pyvex.lifting.util.instr_helper import Instruction
+from pyvex.lifting.util.lifter_helper import GymratLifter
+
+log = logging.getLogger(__name__)
+
+
+class Aarch64Instruction(Instruction):  # pylint: disable=abstract-method
+    # NOTE: WARNING: There is no MRS, MSR, SYSL in VEX's ARM implementation
+    # You must use straight nasty hacks instead.
+    pass
+
+
+class Instruction_SYSL(Aarch64Instruction):
+    name = "SYSL"
+    bin_format = "1101010100101qqqnnnnmmmmppprrrrr"
+
+    def compute_result(self):  # pylint: disable=arguments-differ
+        log.debug("Ignoring SYSL instruction at %#x.", self.addr)
+
+
+class Instruction_MSR(Aarch64Instruction):
+    name = "MSR"
+    bin_format = "11010101000ioqqqnnnnmmmmppprrrrr"
+
+    def compute_result(self):  # pylint: disable=arguments-differ
+        log.debug("Ignoring MSR instruction at %#x.", self.addr)
+
+
+class Instruction_MRS(Aarch64Instruction):
+    name = "MRS"
+    bin_format = "110101010011opppnnnnmmmmppprrrrr"
+
+    def compute_result(self):  # pylint: disable=arguments-differ
+        log.debug("Ignoring MRS instruction at %#x.", self.addr)
+
+
+class AARCH64Spotter(GymratLifter):
+    instrs = [Instruction_MRS, Instruction_MSR, Instruction_SYSL]