v86 0.3.7 → 0.5.10

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (386) hide show
  1. package/Readme.md +64 -108
  2. package/build/libv86-debug.js +12677 -0
  3. package/build/libv86-debug.mjs +732 -0
  4. package/build/libv86.js +710 -0
  5. package/build/libv86.mjs +636 -0
  6. package/build/v86-debug.wasm +0 -0
  7. package/build/v86-fallback.wasm +0 -0
  8. package/build/v86.wasm +0 -0
  9. package/package.json +12 -35
  10. package/bios/.gitignore +0 -1
  11. package/bios/COPYING.LESSER +0 -165
  12. package/bios/bochs-bios.bin +0 -0
  13. package/bios/bochs-vgabios.bin +0 -0
  14. package/bios/fetch-and-build-seabios.sh +0 -13
  15. package/bios/seabios/.config +0 -113
  16. package/bios/seabios/.config.old +0 -114
  17. package/bios/seabios/.gitignore +0 -4
  18. package/bios/seabios/COPYING +0 -674
  19. package/bios/seabios/COPYING.LESSER +0 -165
  20. package/bios/seabios/Makefile +0 -286
  21. package/bios/seabios/README +0 -17
  22. package/bios/seabios/docs/Build_overview.md +0 -104
  23. package/bios/seabios/docs/Contributing.md +0 -20
  24. package/bios/seabios/docs/Debugging.md +0 -111
  25. package/bios/seabios/docs/Developer_Documentation.md +0 -25
  26. package/bios/seabios/docs/Developer_links.md +0 -86
  27. package/bios/seabios/docs/Download.md +0 -27
  28. package/bios/seabios/docs/Execution_and_code_flow.md +0 -178
  29. package/bios/seabios/docs/Linking_overview.md +0 -160
  30. package/bios/seabios/docs/Mailinglist.md +0 -8
  31. package/bios/seabios/docs/Memory_Model.md +0 -253
  32. package/bios/seabios/docs/README +0 -5
  33. package/bios/seabios/docs/Releases.md +0 -482
  34. package/bios/seabios/docs/Runtime_config.md +0 -193
  35. package/bios/seabios/docs/SeaBIOS.md +0 -17
  36. package/bios/seabios/docs/SeaVGABIOS.md +0 -39
  37. package/bios/seabios/out/autoconf.h +0 -117
  38. package/bios/seabios/out/include/config/acpi/dsdt.h +0 -0
  39. package/bios/seabios/out/include/config/acpi.h +0 -0
  40. package/bios/seabios/out/include/config/ahci.h +0 -0
  41. package/bios/seabios/out/include/config/apmbios.h +0 -0
  42. package/bios/seabios/out/include/config/ata/dma.h +0 -0
  43. package/bios/seabios/out/include/config/ata/pio32.h +0 -0
  44. package/bios/seabios/out/include/config/ata.h +0 -0
  45. package/bios/seabios/out/include/config/auto.conf +0 -69
  46. package/bios/seabios/out/include/config/auto.conf.cmd +0 -9
  47. package/bios/seabios/out/include/config/boot.h +0 -0
  48. package/bios/seabios/out/include/config/bootorder.h +0 -0
  49. package/bios/seabios/out/include/config/build/vgabios.h +0 -0
  50. package/bios/seabios/out/include/config/call32/smm.h +0 -0
  51. package/bios/seabios/out/include/config/cdrom/boot.h +0 -0
  52. package/bios/seabios/out/include/config/cdrom/emu.h +0 -0
  53. package/bios/seabios/out/include/config/debug/level.h +0 -0
  54. package/bios/seabios/out/include/config/drives.h +0 -0
  55. package/bios/seabios/out/include/config/entry/extrastack.h +0 -0
  56. package/bios/seabios/out/include/config/esp/scsi.h +0 -0
  57. package/bios/seabios/out/include/config/flash/floppy.h +0 -0
  58. package/bios/seabios/out/include/config/floppy.h +0 -0
  59. package/bios/seabios/out/include/config/fw/romfile/load.h +0 -0
  60. package/bios/seabios/out/include/config/hardware/irq.h +0 -0
  61. package/bios/seabios/out/include/config/kbd/call/int15/4f.h +0 -0
  62. package/bios/seabios/out/include/config/keyboard.h +0 -0
  63. package/bios/seabios/out/include/config/lpt.h +0 -0
  64. package/bios/seabios/out/include/config/lsi/scsi.h +0 -0
  65. package/bios/seabios/out/include/config/malloc/uppermemory.h +0 -0
  66. package/bios/seabios/out/include/config/megasas.h +0 -0
  67. package/bios/seabios/out/include/config/mouse.h +0 -0
  68. package/bios/seabios/out/include/config/mpt/scsi.h +0 -0
  69. package/bios/seabios/out/include/config/mptable.h +0 -0
  70. package/bios/seabios/out/include/config/mtrr/init.h +0 -0
  71. package/bios/seabios/out/include/config/optionroms.h +0 -0
  72. package/bios/seabios/out/include/config/override/pci/id.h +0 -0
  73. package/bios/seabios/out/include/config/pcibios.h +0 -0
  74. package/bios/seabios/out/include/config/pirtable.h +0 -0
  75. package/bios/seabios/out/include/config/pmm.h +0 -0
  76. package/bios/seabios/out/include/config/pmtimer.h +0 -0
  77. package/bios/seabios/out/include/config/pnpbios.h +0 -0
  78. package/bios/seabios/out/include/config/ps2port.h +0 -0
  79. package/bios/seabios/out/include/config/pvscsi.h +0 -0
  80. package/bios/seabios/out/include/config/qemu/hardware.h +0 -0
  81. package/bios/seabios/out/include/config/qemu.h +0 -0
  82. package/bios/seabios/out/include/config/rom/size.h +0 -0
  83. package/bios/seabios/out/include/config/rtc/timer.h +0 -0
  84. package/bios/seabios/out/include/config/s3/resume.h +0 -0
  85. package/bios/seabios/out/include/config/sdcard.h +0 -0
  86. package/bios/seabios/out/include/config/serial.h +0 -0
  87. package/bios/seabios/out/include/config/tcgbios.h +0 -0
  88. package/bios/seabios/out/include/config/threads.h +0 -0
  89. package/bios/seabios/out/include/config/tristate.conf +0 -4
  90. package/bios/seabios/out/include/config/tsc/timer.h +0 -0
  91. package/bios/seabios/out/include/config/use/smm.h +0 -0
  92. package/bios/seabios/out/include/config/vga/allocate/extra/stack.h +0 -0
  93. package/bios/seabios/out/include/config/vga/bochs/stdvga.h +0 -0
  94. package/bios/seabios/out/include/config/vga/bochs.h +0 -0
  95. package/bios/seabios/out/include/config/vga/did.h +0 -0
  96. package/bios/seabios/out/include/config/vga/extra/stack/size.h +0 -0
  97. package/bios/seabios/out/include/config/vga/fixup/asm.h +0 -0
  98. package/bios/seabios/out/include/config/vga/pci.h +0 -0
  99. package/bios/seabios/out/include/config/vga/stdvga/ports.h +0 -0
  100. package/bios/seabios/out/include/config/vga/vbe.h +0 -0
  101. package/bios/seabios/out/include/config/vga/vid.h +0 -0
  102. package/bios/seabios/out/include/config/vgahooks.h +0 -0
  103. package/bios/seabios/out/include/config/virtio/blk.h +0 -0
  104. package/bios/seabios/out/include/config/virtio/scsi.h +0 -0
  105. package/bios/seabios/out/include/config/xen.h +0 -0
  106. package/bios/seabios/out/scripts/kconfig/conf +0 -0
  107. package/bios/seabios/out/scripts/kconfig/conf.o +0 -0
  108. package/bios/seabios/out/scripts/kconfig/zconf.hash.c +0 -289
  109. package/bios/seabios/out/scripts/kconfig/zconf.lex.c +0 -2420
  110. package/bios/seabios/out/scripts/kconfig/zconf.tab.c +0 -2538
  111. package/bios/seabios/out/scripts/kconfig/zconf.tab.o +0 -0
  112. package/bios/seabios/scripts/acpi_extract.py +0 -366
  113. package/bios/seabios/scripts/acpi_extract_preprocess.py +0 -41
  114. package/bios/seabios/scripts/buildrom.py +0 -56
  115. package/bios/seabios/scripts/buildversion.py +0 -134
  116. package/bios/seabios/scripts/checkrom.py +0 -95
  117. package/bios/seabios/scripts/checkstack.py +0 -226
  118. package/bios/seabios/scripts/checksum.py +0 -16
  119. package/bios/seabios/scripts/encodeint.py +0 -21
  120. package/bios/seabios/scripts/gen-offsets.sh +0 -17
  121. package/bios/seabios/scripts/kconfig/.gitignore +0 -22
  122. package/bios/seabios/scripts/kconfig/Makefile +0 -331
  123. package/bios/seabios/scripts/kconfig/POTFILES.in +0 -12
  124. package/bios/seabios/scripts/kconfig/check.sh +0 -13
  125. package/bios/seabios/scripts/kconfig/conf.c +0 -718
  126. package/bios/seabios/scripts/kconfig/confdata.c +0 -1250
  127. package/bios/seabios/scripts/kconfig/expr.c +0 -1168
  128. package/bios/seabios/scripts/kconfig/expr.h +0 -241
  129. package/bios/seabios/scripts/kconfig/gconf.c +0 -1542
  130. package/bios/seabios/scripts/kconfig/gconf.glade +0 -661
  131. package/bios/seabios/scripts/kconfig/images.c +0 -326
  132. package/bios/seabios/scripts/kconfig/kxgettext.c +0 -235
  133. package/bios/seabios/scripts/kconfig/lex.zconf.c +0 -2430
  134. package/bios/seabios/scripts/kconfig/list.h +0 -131
  135. package/bios/seabios/scripts/kconfig/lkc.h +0 -200
  136. package/bios/seabios/scripts/kconfig/lkc_proto.h +0 -57
  137. package/bios/seabios/scripts/kconfig/lxdialog/.gitignore +0 -4
  138. package/bios/seabios/scripts/kconfig/lxdialog/BIG.FAT.WARNING +0 -4
  139. package/bios/seabios/scripts/kconfig/lxdialog/check-lxdialog.sh +0 -87
  140. package/bios/seabios/scripts/kconfig/lxdialog/checklist.c +0 -332
  141. package/bios/seabios/scripts/kconfig/lxdialog/dialog.h +0 -257
  142. package/bios/seabios/scripts/kconfig/lxdialog/inputbox.c +0 -301
  143. package/bios/seabios/scripts/kconfig/lxdialog/menubox.c +0 -437
  144. package/bios/seabios/scripts/kconfig/lxdialog/textbox.c +0 -408
  145. package/bios/seabios/scripts/kconfig/lxdialog/util.c +0 -713
  146. package/bios/seabios/scripts/kconfig/lxdialog/yesno.c +0 -114
  147. package/bios/seabios/scripts/kconfig/mconf.c +0 -1036
  148. package/bios/seabios/scripts/kconfig/menu.c +0 -697
  149. package/bios/seabios/scripts/kconfig/merge_config.sh +0 -150
  150. package/bios/seabios/scripts/kconfig/nconf.c +0 -1556
  151. package/bios/seabios/scripts/kconfig/nconf.gui.c +0 -656
  152. package/bios/seabios/scripts/kconfig/nconf.h +0 -96
  153. package/bios/seabios/scripts/kconfig/qconf.cc +0 -1795
  154. package/bios/seabios/scripts/kconfig/qconf.h +0 -338
  155. package/bios/seabios/scripts/kconfig/streamline_config.pl +0 -647
  156. package/bios/seabios/scripts/kconfig/symbol.c +0 -1373
  157. package/bios/seabios/scripts/kconfig/util.c +0 -157
  158. package/bios/seabios/scripts/kconfig/zconf.gperf +0 -48
  159. package/bios/seabios/scripts/kconfig/zconf.hash.c_shipped +0 -289
  160. package/bios/seabios/scripts/kconfig/zconf.l +0 -363
  161. package/bios/seabios/scripts/kconfig/zconf.lex.c_shipped +0 -2420
  162. package/bios/seabios/scripts/kconfig/zconf.tab.c_shipped +0 -2538
  163. package/bios/seabios/scripts/kconfig/zconf.y +0 -733
  164. package/bios/seabios/scripts/layoutrom.py +0 -705
  165. package/bios/seabios/scripts/python23compat.py +0 -14
  166. package/bios/seabios/scripts/readserial.py +0 -190
  167. package/bios/seabios/scripts/tarball.sh +0 -36
  168. package/bios/seabios/scripts/test-build.sh +0 -90
  169. package/bios/seabios/scripts/transdump.py +0 -53
  170. package/bios/seabios/scripts/vgafixup.py +0 -96
  171. package/bios/seabios/src/Kconfig +0 -579
  172. package/bios/seabios/src/apm.c +0 -215
  173. package/bios/seabios/src/asm-offsets.c +0 -23
  174. package/bios/seabios/src/biosvar.h +0 -130
  175. package/bios/seabios/src/block.c +0 -623
  176. package/bios/seabios/src/block.h +0 -121
  177. package/bios/seabios/src/bmp.c +0 -117
  178. package/bios/seabios/src/boot.c +0 -793
  179. package/bios/seabios/src/bootsplash.c +0 -255
  180. package/bios/seabios/src/bregs.h +0 -80
  181. package/bios/seabios/src/byteorder.h +0 -71
  182. package/bios/seabios/src/cdrom.c +0 -322
  183. package/bios/seabios/src/clock.c +0 -506
  184. package/bios/seabios/src/code16gcc.s +0 -1
  185. package/bios/seabios/src/config.h +0 -108
  186. package/bios/seabios/src/cp437.c +0 -275
  187. package/bios/seabios/src/cp437.h +0 -1
  188. package/bios/seabios/src/disk.c +0 -779
  189. package/bios/seabios/src/e820map.c +0 -152
  190. package/bios/seabios/src/e820map.h +0 -26
  191. package/bios/seabios/src/entryfuncs.S +0 -165
  192. package/bios/seabios/src/farptr.h +0 -208
  193. package/bios/seabios/src/font.c +0 -139
  194. package/bios/seabios/src/fw/acpi-dsdt-cpu-hotplug.dsl +0 -78
  195. package/bios/seabios/src/fw/acpi-dsdt-dbug.dsl +0 -26
  196. package/bios/seabios/src/fw/acpi-dsdt-hpet.dsl +0 -36
  197. package/bios/seabios/src/fw/acpi-dsdt-isa.dsl +0 -102
  198. package/bios/seabios/src/fw/acpi-dsdt-pci-crs.dsl +0 -90
  199. package/bios/seabios/src/fw/acpi-dsdt.dsl +0 -342
  200. package/bios/seabios/src/fw/acpi-dsdt.hex +0 -554
  201. package/bios/seabios/src/fw/acpi.c +0 -685
  202. package/bios/seabios/src/fw/biostables.c +0 -491
  203. package/bios/seabios/src/fw/coreboot.c +0 -569
  204. package/bios/seabios/src/fw/csm.c +0 -347
  205. package/bios/seabios/src/fw/dev-pci.h +0 -52
  206. package/bios/seabios/src/fw/dev-piix.h +0 -29
  207. package/bios/seabios/src/fw/dev-q35.h +0 -52
  208. package/bios/seabios/src/fw/lzmadecode.c +0 -398
  209. package/bios/seabios/src/fw/lzmadecode.h +0 -67
  210. package/bios/seabios/src/fw/mptable.c +0 -197
  211. package/bios/seabios/src/fw/mtrr.c +0 -105
  212. package/bios/seabios/src/fw/multiboot.c +0 -111
  213. package/bios/seabios/src/fw/paravirt.c +0 -624
  214. package/bios/seabios/src/fw/paravirt.h +0 -63
  215. package/bios/seabios/src/fw/pciinit.c +0 -1187
  216. package/bios/seabios/src/fw/pirtable.c +0 -103
  217. package/bios/seabios/src/fw/q35-acpi-dsdt.dsl +0 -450
  218. package/bios/seabios/src/fw/romfile_loader.c +0 -259
  219. package/bios/seabios/src/fw/romfile_loader.h +0 -91
  220. package/bios/seabios/src/fw/shadow.c +0 -208
  221. package/bios/seabios/src/fw/smbios.c +0 -585
  222. package/bios/seabios/src/fw/smm.c +0 -269
  223. package/bios/seabios/src/fw/smp.c +0 -194
  224. package/bios/seabios/src/fw/ssdt-misc.dsl +0 -104
  225. package/bios/seabios/src/fw/ssdt-misc.hex +0 -88
  226. package/bios/seabios/src/fw/ssdt-pcihp.dsl +0 -36
  227. package/bios/seabios/src/fw/ssdt-pcihp.hex +0 -38
  228. package/bios/seabios/src/fw/ssdt-proc.dsl +0 -48
  229. package/bios/seabios/src/fw/ssdt-proc.hex +0 -35
  230. package/bios/seabios/src/fw/xen.c +0 -149
  231. package/bios/seabios/src/fw/xen.h +0 -125
  232. package/bios/seabios/src/gen-defs.h +0 -19
  233. package/bios/seabios/src/hw/ahci.c +0 -697
  234. package/bios/seabios/src/hw/ahci.h +0 -201
  235. package/bios/seabios/src/hw/ata.c +0 -1046
  236. package/bios/seabios/src/hw/ata.h +0 -163
  237. package/bios/seabios/src/hw/blockcmd.c +0 -372
  238. package/bios/seabios/src/hw/blockcmd.h +0 -114
  239. package/bios/seabios/src/hw/dma.c +0 -67
  240. package/bios/seabios/src/hw/esp-scsi.c +0 -241
  241. package/bios/seabios/src/hw/esp-scsi.h +0 -8
  242. package/bios/seabios/src/hw/floppy.c +0 -741
  243. package/bios/seabios/src/hw/lsi-scsi.c +0 -221
  244. package/bios/seabios/src/hw/lsi-scsi.h +0 -8
  245. package/bios/seabios/src/hw/megasas.c +0 -405
  246. package/bios/seabios/src/hw/megasas.h +0 -8
  247. package/bios/seabios/src/hw/mpt-scsi.c +0 -319
  248. package/bios/seabios/src/hw/mpt-scsi.h +0 -8
  249. package/bios/seabios/src/hw/nvme-int.h +0 -199
  250. package/bios/seabios/src/hw/nvme.c +0 -708
  251. package/bios/seabios/src/hw/nvme.h +0 -17
  252. package/bios/seabios/src/hw/pci.c +0 -133
  253. package/bios/seabios/src/hw/pci.h +0 -47
  254. package/bios/seabios/src/hw/pci_ids.h +0 -2632
  255. package/bios/seabios/src/hw/pci_regs.h +0 -556
  256. package/bios/seabios/src/hw/pcidevice.c +0 -192
  257. package/bios/seabios/src/hw/pcidevice.h +0 -76
  258. package/bios/seabios/src/hw/pic.c +0 -115
  259. package/bios/seabios/src/hw/pic.h +0 -60
  260. package/bios/seabios/src/hw/ps2port.c +0 -543
  261. package/bios/seabios/src/hw/ps2port.h +0 -67
  262. package/bios/seabios/src/hw/pvscsi.c +0 -333
  263. package/bios/seabios/src/hw/pvscsi.h +0 -8
  264. package/bios/seabios/src/hw/ramdisk.c +0 -108
  265. package/bios/seabios/src/hw/rtc.c +0 -100
  266. package/bios/seabios/src/hw/rtc.h +0 -75
  267. package/bios/seabios/src/hw/sdcard.c +0 -572
  268. package/bios/seabios/src/hw/serialio.c +0 -113
  269. package/bios/seabios/src/hw/serialio.h +0 -29
  270. package/bios/seabios/src/hw/timer.c +0 -259
  271. package/bios/seabios/src/hw/tpm_drivers.c +0 -636
  272. package/bios/seabios/src/hw/tpm_drivers.h +0 -127
  273. package/bios/seabios/src/hw/usb-ehci.c +0 -650
  274. package/bios/seabios/src/hw/usb-ehci.h +0 -177
  275. package/bios/seabios/src/hw/usb-hid.c +0 -442
  276. package/bios/seabios/src/hw/usb-hid.h +0 -29
  277. package/bios/seabios/src/hw/usb-hub.c +0 -205
  278. package/bios/seabios/src/hw/usb-hub.h +0 -64
  279. package/bios/seabios/src/hw/usb-msc.c +0 -222
  280. package/bios/seabios/src/hw/usb-msc.h +0 -10
  281. package/bios/seabios/src/hw/usb-ohci.c +0 -568
  282. package/bios/seabios/src/hw/usb-ohci.h +0 -144
  283. package/bios/seabios/src/hw/usb-uas.c +0 -289
  284. package/bios/seabios/src/hw/usb-uas.h +0 -9
  285. package/bios/seabios/src/hw/usb-uhci.c +0 -571
  286. package/bios/seabios/src/hw/usb-uhci.h +0 -128
  287. package/bios/seabios/src/hw/usb-xhci.c +0 -1161
  288. package/bios/seabios/src/hw/usb-xhci.h +0 -133
  289. package/bios/seabios/src/hw/usb.c +0 -499
  290. package/bios/seabios/src/hw/usb.h +0 -254
  291. package/bios/seabios/src/hw/virtio-blk.c +0 -211
  292. package/bios/seabios/src/hw/virtio-blk.h +0 -43
  293. package/bios/seabios/src/hw/virtio-pci.c +0 -501
  294. package/bios/seabios/src/hw/virtio-pci.h +0 -151
  295. package/bios/seabios/src/hw/virtio-ring.c +0 -147
  296. package/bios/seabios/src/hw/virtio-ring.h +0 -121
  297. package/bios/seabios/src/hw/virtio-scsi.c +0 -220
  298. package/bios/seabios/src/hw/virtio-scsi.h +0 -47
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@@ -1,650 +0,0 @@
1
- // Code for handling EHCI USB controllers.
2
- //
3
- // Copyright (C) 2010-2013 Kevin O'Connor <kevin@koconnor.net>
4
- //
5
- // This file may be distributed under the terms of the GNU LGPLv3 license.
6
-
7
- #include "biosvar.h" // GET_LOWFLAT
8
- #include "config.h" // CONFIG_*
9
- #include "output.h" // dprintf
10
- #include "malloc.h" // free
11
- #include "memmap.h" // PAGE_SIZE
12
- #include "pcidevice.h" // foreachpci
13
- #include "pci_ids.h" // PCI_CLASS_SERIAL_USB_UHCI
14
- #include "pci_regs.h" // PCI_BASE_ADDRESS_0
15
- #include "string.h" // memset
16
- #include "usb.h" // struct usb_s
17
- #include "usb-ehci.h" // struct ehci_qh
18
- #include "util.h" // msleep
19
- #include "x86.h" // readl
20
-
21
- struct usb_ehci_s {
22
- struct usb_s usb;
23
- struct ehci_caps *caps;
24
- struct ehci_regs *regs;
25
- struct ehci_qh *async_qh;
26
- int checkports;
27
- };
28
-
29
- struct ehci_pipe {
30
- struct ehci_qh qh;
31
- struct ehci_qtd *next_td, *tds;
32
- void *data;
33
- struct usb_pipe pipe;
34
- };
35
-
36
- static int PendingEHCI;
37
-
38
-
39
- /****************************************************************
40
- * Root hub
41
- ****************************************************************/
42
-
43
- #define EHCI_TIME_POSTPOWER 20
44
- #define EHCI_TIME_POSTRESET 2
45
-
46
- // Check if device attached to port
47
- static int
48
- ehci_hub_detect(struct usbhub_s *hub, u32 port)
49
- {
50
- struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
51
- u32 *portreg = &cntl->regs->portsc[port];
52
- u32 portsc = readl(portreg);
53
-
54
- if (!(portsc & PORT_CONNECT))
55
- // No device present
56
- return 0;
57
-
58
- if ((portsc & PORT_LINESTATUS_MASK) == PORT_LINESTATUS_KSTATE) {
59
- // low speed device
60
- writel(portreg, portsc | PORT_OWNER);
61
- return -1;
62
- }
63
-
64
- // XXX - if just powered up, need to wait for USB_TIME_ATTDB?
65
-
66
- // Begin reset on port
67
- portsc = (portsc & ~PORT_PE) | PORT_RESET;
68
- writel(portreg, portsc);
69
- msleep(USB_TIME_DRSTR);
70
- return 1;
71
- }
72
-
73
- // Reset device on port
74
- static int
75
- ehci_hub_reset(struct usbhub_s *hub, u32 port)
76
- {
77
- struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
78
- u32 *portreg = &cntl->regs->portsc[port];
79
- u32 portsc = readl(portreg);
80
-
81
- // Finish reset on port
82
- portsc &= ~PORT_RESET;
83
- writel(portreg, portsc);
84
- msleep(EHCI_TIME_POSTRESET);
85
-
86
- portsc = readl(portreg);
87
- if (!(portsc & PORT_CONNECT))
88
- // No longer connected
89
- return -1;
90
- if (!(portsc & PORT_PE)) {
91
- // full speed device
92
- writel(portreg, portsc | PORT_OWNER);
93
- return -1;
94
- }
95
-
96
- return USB_HIGHSPEED;
97
- }
98
-
99
- // Disable port
100
- static void
101
- ehci_hub_disconnect(struct usbhub_s *hub, u32 port)
102
- {
103
- struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
104
- u32 *portreg = &cntl->regs->portsc[port];
105
- u32 portsc = readl(portreg);
106
- writel(portreg, portsc & ~PORT_PE);
107
- }
108
-
109
- static struct usbhub_op_s ehci_HubOp = {
110
- .detect = ehci_hub_detect,
111
- .reset = ehci_hub_reset,
112
- .disconnect = ehci_hub_disconnect,
113
- };
114
-
115
- // Find any devices connected to the root hub.
116
- static int
117
- check_ehci_ports(struct usb_ehci_s *cntl)
118
- {
119
- // Power up ports.
120
- int i;
121
- for (i=0; i<cntl->checkports; i++) {
122
- u32 *portreg = &cntl->regs->portsc[i];
123
- u32 portsc = readl(portreg);
124
- if (!(portsc & PORT_POWER)) {
125
- portsc |= PORT_POWER;
126
- writel(portreg, portsc);
127
- }
128
- }
129
- msleep(EHCI_TIME_POSTPOWER);
130
-
131
- struct usbhub_s hub;
132
- memset(&hub, 0, sizeof(hub));
133
- hub.cntl = &cntl->usb;
134
- hub.portcount = cntl->checkports;
135
- hub.op = &ehci_HubOp;
136
- usb_enumerate(&hub);
137
- return hub.devcount;
138
- }
139
-
140
-
141
- /****************************************************************
142
- * Setup
143
- ****************************************************************/
144
-
145
- // Wait for next USB async frame to start - for ensuring safe memory release.
146
- static void
147
- ehci_waittick(struct usb_ehci_s *cntl)
148
- {
149
- if (MODE16) {
150
- msleep(10);
151
- return;
152
- }
153
- // Wait for access to "doorbell"
154
- barrier();
155
- u32 cmd, sts;
156
- u32 end = timer_calc(100);
157
- for (;;) {
158
- sts = readl(&cntl->regs->usbsts);
159
- if (!(sts & STS_IAA)) {
160
- cmd = readl(&cntl->regs->usbcmd);
161
- if (!(cmd & CMD_IAAD))
162
- break;
163
- }
164
- if (timer_check(end)) {
165
- warn_timeout();
166
- return;
167
- }
168
- yield();
169
- }
170
- // Ring "doorbell"
171
- writel(&cntl->regs->usbcmd, cmd | CMD_IAAD);
172
- // Wait for completion
173
- for (;;) {
174
- sts = readl(&cntl->regs->usbsts);
175
- if (sts & STS_IAA)
176
- break;
177
- if (timer_check(end)) {
178
- warn_timeout();
179
- return;
180
- }
181
- yield();
182
- }
183
- // Ack completion
184
- writel(&cntl->regs->usbsts, STS_IAA);
185
- }
186
-
187
- static void
188
- ehci_free_pipes(struct usb_ehci_s *cntl)
189
- {
190
- dprintf(7, "ehci_free_pipes %p\n", cntl);
191
-
192
- struct ehci_qh *start = cntl->async_qh;
193
- struct ehci_qh *pos = start;
194
- for (;;) {
195
- struct ehci_qh *next = (void*)(pos->next & ~EHCI_PTR_BITS);
196
- if (next == start)
197
- break;
198
- struct ehci_pipe *pipe = container_of(next, struct ehci_pipe, qh);
199
- if (usb_is_freelist(&cntl->usb, &pipe->pipe))
200
- pos->next = next->next;
201
- else
202
- pos = next;
203
- }
204
- ehci_waittick(cntl);
205
- for (;;) {
206
- struct usb_pipe *usbpipe = cntl->usb.freelist;
207
- if (!usbpipe)
208
- break;
209
- cntl->usb.freelist = usbpipe->freenext;
210
- struct ehci_pipe *pipe = container_of(usbpipe, struct ehci_pipe, pipe);
211
- free(pipe);
212
- }
213
- }
214
-
215
- static void
216
- configure_ehci(void *data)
217
- {
218
- struct usb_ehci_s *cntl = data;
219
-
220
- // Allocate ram for schedule storage
221
- struct ehci_framelist *fl = memalign_high(sizeof(*fl), sizeof(*fl));
222
- struct ehci_qh *intr_qh = memalign_high(EHCI_QH_ALIGN, sizeof(*intr_qh));
223
- struct ehci_qh *async_qh = memalign_high(EHCI_QH_ALIGN, sizeof(*async_qh));
224
- if (!fl || !intr_qh || !async_qh) {
225
- warn_noalloc();
226
- PendingEHCI--;
227
- goto fail;
228
- }
229
-
230
- // XXX - check for halted?
231
-
232
- // Reset the HC
233
- u32 cmd = readl(&cntl->regs->usbcmd);
234
- writel(&cntl->regs->usbcmd, (cmd & ~(CMD_ASE | CMD_PSE)) | CMD_HCRESET);
235
- u32 end = timer_calc(250);
236
- for (;;) {
237
- cmd = readl(&cntl->regs->usbcmd);
238
- if (!(cmd & CMD_HCRESET))
239
- break;
240
- if (timer_check(end)) {
241
- warn_timeout();
242
- PendingEHCI--;
243
- goto fail;
244
- }
245
- yield();
246
- }
247
-
248
- // Disable interrupts (just to be safe).
249
- writel(&cntl->regs->usbintr, 0);
250
-
251
- // Set schedule to point to primary intr queue head
252
- memset(intr_qh, 0, sizeof(*intr_qh));
253
- intr_qh->next = EHCI_PTR_TERM;
254
- intr_qh->info2 = (0x01 << QH_SMASK_SHIFT);
255
- intr_qh->token = QTD_STS_HALT;
256
- intr_qh->qtd_next = intr_qh->alt_next = EHCI_PTR_TERM;
257
- int i;
258
- for (i=0; i<ARRAY_SIZE(fl->links); i++)
259
- fl->links[i] = (u32)intr_qh | EHCI_PTR_QH;
260
- writel(&cntl->regs->periodiclistbase, (u32)fl);
261
-
262
- // Set async list to point to primary async queue head
263
- memset(async_qh, 0, sizeof(*async_qh));
264
- async_qh->next = (u32)async_qh | EHCI_PTR_QH;
265
- async_qh->info1 = QH_HEAD;
266
- async_qh->token = QTD_STS_HALT;
267
- async_qh->qtd_next = async_qh->alt_next = EHCI_PTR_TERM;
268
- cntl->async_qh = async_qh;
269
- writel(&cntl->regs->asynclistbase, (u32)async_qh);
270
-
271
- // Enable queues
272
- writel(&cntl->regs->usbcmd, cmd | CMD_ASE | CMD_PSE | CMD_RUN);
273
-
274
- // Set default of high speed for root hub.
275
- writel(&cntl->regs->configflag, 1);
276
- PendingEHCI--;
277
-
278
- // Find devices
279
- int count = check_ehci_ports(cntl);
280
- ehci_free_pipes(cntl);
281
- if (count)
282
- // Success
283
- return;
284
-
285
- // No devices found - shutdown and free controller.
286
- writel(&cntl->regs->usbcmd, cmd & ~CMD_RUN);
287
- msleep(4); // 2ms to stop reading memory - XXX
288
- fail:
289
- free(fl);
290
- free(intr_qh);
291
- free(async_qh);
292
- free(cntl);
293
- }
294
-
295
- static void
296
- ehci_controller_setup(struct pci_device *pci)
297
- {
298
- struct ehci_caps *caps = pci_enable_membar(pci, PCI_BASE_ADDRESS_0);
299
- if (!caps)
300
- return;
301
- u32 hcc_params = readl(&caps->hccparams);
302
-
303
- struct usb_ehci_s *cntl = malloc_tmphigh(sizeof(*cntl));
304
- if (!cntl) {
305
- warn_noalloc();
306
- return;
307
- }
308
- memset(cntl, 0, sizeof(*cntl));
309
- cntl->usb.pci = pci;
310
- cntl->usb.type = USB_TYPE_EHCI;
311
- cntl->caps = caps;
312
- cntl->checkports = readl(&cntl->caps->hcsparams) & HCS_N_PORTS_MASK;
313
- cntl->regs = (void*)caps + readb(&caps->caplength);
314
- if (hcc_params & HCC_64BIT_ADDR)
315
- cntl->regs->ctrldssegment = 0;
316
- PendingEHCI++;
317
-
318
- dprintf(1, "EHCI init on dev %pP (regs=%p)\n", pci, cntl->regs);
319
-
320
- pci_enable_busmaster(pci);
321
-
322
- // XXX - check for and disable SMM control?
323
-
324
- run_thread(configure_ehci, cntl);
325
- }
326
-
327
- void
328
- ehci_setup(void)
329
- {
330
- if (! CONFIG_USB_EHCI)
331
- return;
332
- struct pci_device *pci;
333
- foreachpci(pci) {
334
- if (pci_classprog(pci) == PCI_CLASS_SERIAL_USB_EHCI)
335
- ehci_controller_setup(pci);
336
- }
337
- }
338
-
339
- // Wait for all EHCI controllers to initialize. This forces OHCI/UHCI
340
- // setup to always be after any EHCI ports are routed to EHCI.
341
- void
342
- ehci_wait_controllers(void)
343
- {
344
- while (CONFIG_USB_EHCI && CONFIG_THREADS && PendingEHCI)
345
- yield();
346
- }
347
-
348
-
349
- /****************************************************************
350
- * End point communication
351
- ****************************************************************/
352
-
353
- // Setup fields in qh
354
- static void
355
- ehci_desc2pipe(struct ehci_pipe *pipe, struct usbdevice_s *usbdev
356
- , struct usb_endpoint_descriptor *epdesc)
357
- {
358
- usb_desc2pipe(&pipe->pipe, usbdev, epdesc);
359
-
360
- pipe->qh.info1 = ((pipe->pipe.maxpacket << QH_MAXPACKET_SHIFT)
361
- | (pipe->pipe.speed << QH_SPEED_SHIFT)
362
- | (pipe->pipe.ep << QH_EP_SHIFT)
363
- | (pipe->pipe.devaddr << QH_DEVADDR_SHIFT));
364
-
365
- pipe->qh.info2 = (1 << QH_MULT_SHIFT);
366
- struct usbdevice_s *hubdev = usbdev->hub->usbdev;
367
- if (hubdev) {
368
- struct ehci_pipe *hpipe = container_of(
369
- hubdev->defpipe, struct ehci_pipe, pipe);
370
- if (hpipe->pipe.speed == USB_HIGHSPEED)
371
- pipe->qh.info2 |= (((usbdev->port+1) << QH_HUBPORT_SHIFT)
372
- | (hpipe->pipe.devaddr << QH_HUBADDR_SHIFT));
373
- else
374
- pipe->qh.info2 = hpipe->qh.info2;
375
- }
376
-
377
- u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
378
- if (eptype == USB_ENDPOINT_XFER_CONTROL)
379
- pipe->qh.info1 |= ((pipe->pipe.speed != USB_HIGHSPEED ? QH_CONTROL : 0)
380
- | QH_TOGGLECONTROL);
381
- else if (eptype == USB_ENDPOINT_XFER_INT)
382
- pipe->qh.info2 |= (0x01 << QH_SMASK_SHIFT) | (0x1c << QH_CMASK_SHIFT);
383
- }
384
-
385
- static struct usb_pipe *
386
- ehci_alloc_intr_pipe(struct usbdevice_s *usbdev
387
- , struct usb_endpoint_descriptor *epdesc)
388
- {
389
- struct usb_ehci_s *cntl = container_of(
390
- usbdev->hub->cntl, struct usb_ehci_s, usb);
391
- int frameexp = usb_get_period(usbdev, epdesc);
392
- dprintf(7, "ehci_alloc_intr_pipe %p %d\n", &cntl->usb, frameexp);
393
-
394
- if (frameexp > 10)
395
- frameexp = 10;
396
- int maxpacket = epdesc->wMaxPacketSize;
397
- // Determine number of entries needed for 2 timer ticks.
398
- int ms = 1<<frameexp;
399
- int count = DIV_ROUND_UP(ticks_to_ms(2), ms);
400
- struct ehci_pipe *pipe = memalign_low(EHCI_QH_ALIGN, sizeof(*pipe));
401
- struct ehci_qtd *tds = memalign_low(EHCI_QTD_ALIGN, sizeof(*tds) * count);
402
- void *data = malloc_low(maxpacket * count);
403
- if (!pipe || !tds || !data) {
404
- warn_noalloc();
405
- goto fail;
406
- }
407
- memset(pipe, 0, sizeof(*pipe));
408
- memset(tds, 0, sizeof(*tds) * count);
409
- memset(data, 0, maxpacket * count);
410
- ehci_desc2pipe(pipe, usbdev, epdesc);
411
- pipe->next_td = pipe->tds = tds;
412
- pipe->data = data;
413
- pipe->qh.qtd_next = (u32)tds;
414
-
415
- int i;
416
- for (i=0; i<count; i++) {
417
- struct ehci_qtd *td = &tds[i];
418
- td->qtd_next = (i==count-1 ? (u32)tds : (u32)&td[1]);
419
- td->alt_next = EHCI_PTR_TERM;
420
- td->token = (ehci_explen(maxpacket) | QTD_STS_ACTIVE
421
- | QTD_PID_IN | ehci_maxerr(3));
422
- td->buf[0] = (u32)data + maxpacket * i;
423
- }
424
-
425
- // Add to interrupt schedule.
426
- struct ehci_framelist *fl = (void*)readl(&cntl->regs->periodiclistbase);
427
- if (frameexp == 0) {
428
- // Add to existing interrupt entry.
429
- struct ehci_qh *intr_qh = (void*)(fl->links[0] & ~EHCI_PTR_BITS);
430
- pipe->qh.next = intr_qh->next;
431
- barrier();
432
- intr_qh->next = (u32)&pipe->qh | EHCI_PTR_QH;
433
- } else {
434
- int startpos = 1<<(frameexp-1);
435
- pipe->qh.next = fl->links[startpos];
436
- barrier();
437
- for (i=startpos; i<ARRAY_SIZE(fl->links); i+=ms)
438
- fl->links[i] = (u32)&pipe->qh | EHCI_PTR_QH;
439
- }
440
-
441
- return &pipe->pipe;
442
- fail:
443
- free(pipe);
444
- free(tds);
445
- free(data);
446
- return NULL;
447
- }
448
-
449
- struct usb_pipe *
450
- ehci_realloc_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe
451
- , struct usb_endpoint_descriptor *epdesc)
452
- {
453
- if (! CONFIG_USB_EHCI)
454
- return NULL;
455
- usb_add_freelist(upipe);
456
- if (!epdesc)
457
- return NULL;
458
- u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
459
- if (eptype == USB_ENDPOINT_XFER_INT)
460
- return ehci_alloc_intr_pipe(usbdev, epdesc);
461
- struct usb_ehci_s *cntl = container_of(
462
- usbdev->hub->cntl, struct usb_ehci_s, usb);
463
- dprintf(7, "ehci_alloc_async_pipe %p %d\n", &cntl->usb, eptype);
464
-
465
- struct usb_pipe *usbpipe = usb_get_freelist(&cntl->usb, eptype);
466
- if (usbpipe) {
467
- // Use previously allocated pipe.
468
- struct ehci_pipe *pipe = container_of(usbpipe, struct ehci_pipe, pipe);
469
- ehci_desc2pipe(pipe, usbdev, epdesc);
470
- pipe->qh.token = 0;
471
- return usbpipe;
472
- }
473
-
474
- // Allocate a new queue head.
475
- struct ehci_pipe *pipe;
476
- if (eptype == USB_ENDPOINT_XFER_CONTROL)
477
- pipe = memalign_tmphigh(EHCI_QH_ALIGN, sizeof(*pipe));
478
- else
479
- pipe = memalign_low(EHCI_QH_ALIGN, sizeof(*pipe));
480
- if (!pipe) {
481
- warn_noalloc();
482
- return NULL;
483
- }
484
- memset(pipe, 0, sizeof(*pipe));
485
- ehci_desc2pipe(pipe, usbdev, epdesc);
486
- pipe->qh.qtd_next = pipe->qh.alt_next = EHCI_PTR_TERM;
487
-
488
- // Add queue head to controller list.
489
- struct ehci_qh *async_qh = cntl->async_qh;
490
- pipe->qh.next = async_qh->next;
491
- barrier();
492
- async_qh->next = (u32)&pipe->qh | EHCI_PTR_QH;
493
- return &pipe->pipe;
494
- }
495
-
496
- static void
497
- ehci_reset_pipe(struct ehci_pipe *pipe)
498
- {
499
- SET_LOWFLAT(pipe->qh.qtd_next, EHCI_PTR_TERM);
500
- SET_LOWFLAT(pipe->qh.alt_next, EHCI_PTR_TERM);
501
- barrier();
502
- SET_LOWFLAT(pipe->qh.token, GET_LOWFLAT(pipe->qh.token) & QTD_TOGGLE);
503
- }
504
-
505
- static int
506
- ehci_wait_td(struct ehci_pipe *pipe, struct ehci_qtd *td, u32 end)
507
- {
508
- u32 status;
509
- for (;;) {
510
- status = td->token;
511
- if (!(status & QTD_STS_ACTIVE))
512
- break;
513
- if (timer_check(end)) {
514
- u32 cur = GET_LOWFLAT(pipe->qh.current);
515
- u32 tok = GET_LOWFLAT(pipe->qh.token);
516
- u32 next = GET_LOWFLAT(pipe->qh.qtd_next);
517
- warn_timeout();
518
- dprintf(1, "ehci pipe=%p cur=%08x tok=%08x next=%x td=%p status=%x\n"
519
- , pipe, cur, tok, next, td, status);
520
- ehci_reset_pipe(pipe);
521
- struct usb_ehci_s *cntl = container_of(
522
- GET_LOWFLAT(pipe->pipe.cntl), struct usb_ehci_s, usb);
523
- ehci_waittick(cntl);
524
- return -1;
525
- }
526
- yield();
527
- }
528
- if (status & QTD_STS_HALT) {
529
- dprintf(1, "ehci_wait_td error - status=%x\n", status);
530
- ehci_reset_pipe(pipe);
531
- return -2;
532
- }
533
- return 0;
534
- }
535
-
536
- static void
537
- ehci_fill_tdbuf(struct ehci_qtd *td, u32 dest, int transfer)
538
- {
539
- u32 *pos = td->buf, end = dest + transfer;
540
- for (; dest < end; dest = ALIGN_DOWN(dest + PAGE_SIZE, PAGE_SIZE))
541
- *pos++ = dest;
542
- }
543
-
544
- #define STACKQTDS 6
545
-
546
- int
547
- ehci_send_pipe(struct usb_pipe *p, int dir, const void *cmd
548
- , void *data, int datasize)
549
- {
550
- if (! CONFIG_USB_EHCI)
551
- return -1;
552
- struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
553
- dprintf(7, "ehci_send_pipe qh=%p dir=%d data=%p size=%d\n"
554
- , &pipe->qh, dir, data, datasize);
555
-
556
- // Allocate tds on stack (with required alignment)
557
- u8 tdsbuf[sizeof(struct ehci_qtd) * STACKQTDS + EHCI_QTD_ALIGN - 1];
558
- struct ehci_qtd *tds = (void*)ALIGN((u32)tdsbuf, EHCI_QTD_ALIGN), *td = tds;
559
- memset(tds, 0, sizeof(*tds) * STACKQTDS);
560
-
561
- // Setup transfer descriptors
562
- u16 maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket);
563
- u32 toggle = 0;
564
- if (cmd) {
565
- // Send setup pid on control transfers
566
- td->qtd_next = (u32)MAKE_FLATPTR(GET_SEG(SS), td+1);
567
- td->alt_next = EHCI_PTR_TERM;
568
- td->token = (ehci_explen(USB_CONTROL_SETUP_SIZE) | QTD_STS_ACTIVE
569
- | QTD_PID_SETUP | ehci_maxerr(3));
570
- ehci_fill_tdbuf(td, (u32)cmd, USB_CONTROL_SETUP_SIZE);
571
- td++;
572
- toggle = QTD_TOGGLE;
573
- }
574
- u32 dest = (u32)data, dataend = dest + datasize;
575
- while (dest < dataend) {
576
- // Send data pids
577
- if (td >= &tds[STACKQTDS]) {
578
- warn_noalloc();
579
- return -1;
580
- }
581
- int maxtransfer = 5*PAGE_SIZE - (dest & (PAGE_SIZE-1));
582
- int transfer = dataend - dest;
583
- if (transfer > maxtransfer)
584
- transfer = ALIGN_DOWN(maxtransfer, maxpacket);
585
- td->qtd_next = (u32)MAKE_FLATPTR(GET_SEG(SS), td+1);
586
- td->alt_next = EHCI_PTR_TERM;
587
- td->token = (ehci_explen(transfer) | toggle | QTD_STS_ACTIVE
588
- | (dir ? QTD_PID_IN : QTD_PID_OUT) | ehci_maxerr(3));
589
- ehci_fill_tdbuf(td, dest, transfer);
590
- td++;
591
- dest += transfer;
592
- }
593
- if (cmd) {
594
- // Send status pid on control transfers
595
- if (td >= &tds[STACKQTDS]) {
596
- warn_noalloc();
597
- return -1;
598
- }
599
- td->qtd_next = EHCI_PTR_TERM;
600
- td->alt_next = EHCI_PTR_TERM;
601
- td->token = (QTD_TOGGLE | QTD_STS_ACTIVE
602
- | (dir ? QTD_PID_OUT : QTD_PID_IN) | ehci_maxerr(3));
603
- td++;
604
- }
605
-
606
- // Transfer data
607
- (td-1)->qtd_next = EHCI_PTR_TERM;
608
- barrier();
609
- SET_LOWFLAT(pipe->qh.qtd_next, (u32)MAKE_FLATPTR(GET_SEG(SS), tds));
610
- u32 end = timer_calc(usb_xfer_time(p, datasize));
611
- int i;
612
- for (i=0, td=tds; i<STACKQTDS; i++, td++) {
613
- int ret = ehci_wait_td(pipe, td, end);
614
- if (ret)
615
- return -1;
616
- }
617
-
618
- return 0;
619
- }
620
-
621
- int
622
- ehci_poll_intr(struct usb_pipe *p, void *data)
623
- {
624
- ASSERT16();
625
- if (! CONFIG_USB_EHCI)
626
- return -1;
627
- struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
628
- struct ehci_qtd *td = GET_LOWFLAT(pipe->next_td);
629
- u32 token = GET_LOWFLAT(td->token);
630
- if (token & QTD_STS_ACTIVE)
631
- // No intrs found.
632
- return -1;
633
- // XXX - check for errors.
634
-
635
- // Copy data.
636
- int maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket);
637
- int pos = td - GET_LOWFLAT(pipe->tds);
638
- void *tddata = GET_LOWFLAT(pipe->data) + maxpacket * pos;
639
- memcpy_far(GET_SEG(SS), data, SEG_LOW, LOWFLAT2LOW(tddata), maxpacket);
640
-
641
- // Reenable this td.
642
- struct ehci_qtd *next = (void*)(GET_LOWFLAT(td->qtd_next) & ~EHCI_PTR_BITS);
643
- SET_LOWFLAT(pipe->next_td, next);
644
- SET_LOWFLAT(td->buf[0], (u32)tddata);
645
- barrier();
646
- SET_LOWFLAT(td->token, (ehci_explen(maxpacket) | QTD_STS_ACTIVE
647
- | QTD_PID_IN | ehci_maxerr(3)));
648
-
649
- return 0;
650
- }