rp2040js 0.17.17 → 0.18.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/cjs/clock/clock.d.ts +11 -11
- package/dist/cjs/clock/clock.js +2 -2
- package/dist/cjs/clock/mock-clock.d.ts +17 -17
- package/dist/cjs/clock/mock-clock.js +52 -52
- package/dist/cjs/clock/realtime-clock.d.ts +23 -23
- package/dist/cjs/clock/realtime-clock.js +73 -73
- package/dist/cjs/cortex-m0-core.d.ts +87 -87
- package/dist/cjs/cortex-m0-core.js +1251 -1251
- package/dist/cjs/gdb/gdb-connection.d.ts +11 -11
- package/dist/cjs/gdb/gdb-connection.js +57 -57
- package/dist/cjs/gdb/gdb-server.d.ts +23 -23
- package/dist/cjs/gdb/gdb-server.js +232 -232
- package/dist/cjs/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/cjs/gdb/gdb-tcp-server.js +34 -34
- package/dist/cjs/gdb/gdb-utils.d.ts +9 -9
- package/dist/cjs/gdb/gdb-utils.js +48 -48
- package/dist/cjs/gpio-pin.d.ts +56 -56
- package/dist/cjs/gpio-pin.js +216 -216
- package/dist/cjs/index.d.ts +11 -11
- package/dist/cjs/index.js +36 -36
- package/dist/cjs/interpolator.d.ts +36 -36
- package/dist/cjs/interpolator.js +150 -150
- package/dist/cjs/irq.d.ts +29 -29
- package/dist/cjs/irq.js +33 -33
- package/dist/cjs/peripherals/adc.d.ts +52 -52
- package/dist/cjs/peripherals/adc.js +261 -261
- package/dist/cjs/peripherals/busctrl.d.ts +10 -10
- package/dist/cjs/peripherals/busctrl.js +84 -84
- package/dist/cjs/peripherals/clocks.d.ts +9 -9
- package/dist/cjs/peripherals/clocks.js +42 -42
- package/dist/cjs/peripherals/dma.d.ts +109 -109
- package/dist/cjs/peripherals/dma.js +520 -520
- package/dist/cjs/peripherals/i2c.d.ts +54 -54
- package/dist/cjs/peripherals/i2c.js +458 -458
- package/dist/cjs/peripherals/io.d.ts +11 -11
- package/dist/cjs/peripherals/io.js +100 -100
- package/dist/cjs/peripherals/pads.d.ts +13 -13
- package/dist/cjs/peripherals/pads.js +58 -58
- package/dist/cjs/peripherals/peripheral.d.ts +22 -22
- package/dist/cjs/peripherals/peripheral.js +61 -61
- package/dist/cjs/peripherals/pio.d.ts +120 -120
- package/dist/cjs/peripherals/pio.js +1086 -1086
- package/dist/cjs/peripherals/ppb.d.ts +25 -25
- package/dist/cjs/peripherals/ppb.js +229 -229
- package/dist/cjs/peripherals/pwm.d.ts +65 -65
- package/dist/cjs/peripherals/pwm.js +372 -372
- package/dist/cjs/peripherals/reset.d.ts +8 -8
- package/dist/cjs/peripherals/reset.js +40 -40
- package/dist/cjs/peripherals/rtc.d.ts +10 -10
- package/dist/cjs/peripherals/rtc.js +74 -74
- package/dist/cjs/peripherals/spi.d.ts +38 -38
- package/dist/cjs/peripherals/spi.js +240 -240
- package/dist/cjs/peripherals/ssi.d.ts +6 -6
- package/dist/cjs/peripherals/ssi.js +43 -43
- package/dist/cjs/peripherals/syscfg.d.ts +5 -5
- package/dist/cjs/peripherals/syscfg.js +26 -26
- package/dist/cjs/peripherals/sysinfo.d.ts +4 -4
- package/dist/cjs/peripherals/sysinfo.js +22 -22
- package/dist/cjs/peripherals/tbman.d.ts +4 -4
- package/dist/cjs/peripherals/tbman.js +17 -17
- package/dist/cjs/peripherals/timer.d.ts +18 -18
- package/dist/cjs/peripherals/timer.js +156 -156
- package/dist/cjs/peripherals/uart.d.ts +31 -31
- package/dist/cjs/peripherals/uart.js +132 -132
- package/dist/cjs/peripherals/usb.d.ts +29 -29
- package/dist/cjs/peripherals/usb.js +309 -309
- package/dist/cjs/rp2040.d.ts +71 -71
- package/dist/cjs/rp2040.js +361 -361
- package/dist/cjs/sio.d.ts +21 -21
- package/dist/cjs/sio.js +425 -425
- package/dist/cjs/usb/cdc.d.ts +20 -20
- package/dist/cjs/usb/cdc.js +126 -126
- package/dist/cjs/usb/interfaces.d.ts +47 -47
- package/dist/cjs/usb/interfaces.js +46 -46
- package/dist/cjs/usb/setup.d.ts +5 -5
- package/dist/cjs/usb/setup.js +53 -53
- package/dist/cjs/utils/assembler.d.ts +79 -79
- package/dist/cjs/utils/assembler.js +328 -328
- package/dist/cjs/utils/bit.d.ts +3 -3
- package/dist/cjs/utils/bit.js +15 -15
- package/dist/cjs/utils/fifo.d.ts +15 -15
- package/dist/cjs/utils/fifo.js +56 -56
- package/dist/cjs/utils/logging.d.ts +23 -23
- package/dist/cjs/utils/logging.js +48 -48
- package/dist/cjs/utils/pio-assembler.d.ts +45 -45
- package/dist/cjs/utils/pio-assembler.js +87 -87
- package/dist/cjs/utils/time.d.ts +2 -2
- package/dist/cjs/utils/time.js +32 -32
- package/dist/cjs/utils/timer32.d.ts +57 -57
- package/dist/cjs/utils/timer32.js +208 -208
- package/dist/esm/clock/clock.d.ts +11 -11
- package/dist/esm/clock/clock.js +1 -1
- package/dist/esm/clock/mock-clock.d.ts +17 -17
- package/dist/esm/clock/mock-clock.js +47 -47
- package/dist/esm/clock/realtime-clock.d.ts +23 -23
- package/dist/esm/clock/realtime-clock.js +68 -68
- package/dist/esm/cortex-m0-core.d.ts +87 -87
- package/dist/esm/cortex-m0-core.js +1247 -1247
- package/dist/esm/gdb/gdb-connection.d.ts +11 -11
- package/dist/esm/gdb/gdb-connection.js +53 -53
- package/dist/esm/gdb/gdb-server.d.ts +23 -23
- package/dist/esm/gdb/gdb-server.js +228 -228
- package/dist/esm/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/esm/gdb/gdb-tcp-server.js +30 -30
- package/dist/esm/gdb/gdb-utils.d.ts +9 -9
- package/dist/esm/gdb/gdb-utils.js +36 -36
- package/dist/esm/gpio-pin.d.ts +56 -56
- package/dist/esm/gpio-pin.js +212 -212
- package/dist/esm/index.d.ts +11 -11
- package/dist/esm/index.js +11 -11
- package/dist/esm/interpolator.d.ts +36 -36
- package/dist/esm/interpolator.js +145 -145
- package/dist/esm/irq.d.ts +29 -29
- package/dist/esm/irq.js +30 -30
- package/dist/esm/peripherals/adc.d.ts +52 -52
- package/dist/esm/peripherals/adc.js +257 -257
- package/dist/esm/peripherals/busctrl.d.ts +10 -10
- package/dist/esm/peripherals/busctrl.js +80 -80
- package/dist/esm/peripherals/clocks.d.ts +9 -9
- package/dist/esm/peripherals/clocks.js +38 -38
- package/dist/esm/peripherals/dma.d.ts +109 -109
- package/dist/esm/peripherals/dma.js +515 -515
- package/dist/esm/peripherals/i2c.d.ts +54 -54
- package/dist/esm/peripherals/i2c.js +454 -454
- package/dist/esm/peripherals/io.d.ts +11 -11
- package/dist/esm/peripherals/io.js +96 -96
- package/dist/esm/peripherals/pads.d.ts +13 -13
- package/dist/esm/peripherals/pads.js +54 -54
- package/dist/esm/peripherals/peripheral.d.ts +22 -22
- package/dist/esm/peripherals/peripheral.js +55 -55
- package/dist/esm/peripherals/pio.d.ts +120 -120
- package/dist/esm/peripherals/pio.js +1081 -1081
- package/dist/esm/peripherals/ppb.d.ts +25 -25
- package/dist/esm/peripherals/ppb.js +225 -225
- package/dist/esm/peripherals/pwm.d.ts +65 -65
- package/dist/esm/peripherals/pwm.js +368 -368
- package/dist/esm/peripherals/reset.d.ts +8 -8
- package/dist/esm/peripherals/reset.js +36 -36
- package/dist/esm/peripherals/rtc.d.ts +10 -10
- package/dist/esm/peripherals/rtc.js +70 -70
- package/dist/esm/peripherals/spi.d.ts +38 -38
- package/dist/esm/peripherals/spi.js +236 -236
- package/dist/esm/peripherals/ssi.d.ts +6 -6
- package/dist/esm/peripherals/ssi.js +39 -39
- package/dist/esm/peripherals/syscfg.d.ts +5 -5
- package/dist/esm/peripherals/syscfg.js +22 -22
- package/dist/esm/peripherals/sysinfo.d.ts +4 -4
- package/dist/esm/peripherals/sysinfo.js +18 -18
- package/dist/esm/peripherals/tbman.d.ts +4 -4
- package/dist/esm/peripherals/tbman.js +13 -13
- package/dist/esm/peripherals/timer.d.ts +18 -18
- package/dist/esm/peripherals/timer.js +152 -152
- package/dist/esm/peripherals/uart.d.ts +31 -31
- package/dist/esm/peripherals/uart.js +128 -128
- package/dist/esm/peripherals/usb.d.ts +29 -29
- package/dist/esm/peripherals/usb.js +305 -305
- package/dist/esm/rp2040.d.ts +71 -71
- package/dist/esm/rp2040.js +357 -357
- package/dist/esm/sio.d.ts +21 -21
- package/dist/esm/sio.js +421 -421
- package/dist/esm/usb/cdc.d.ts +20 -20
- package/dist/esm/usb/cdc.js +121 -121
- package/dist/esm/usb/interfaces.d.ts +47 -47
- package/dist/esm/usb/interfaces.js +43 -43
- package/dist/esm/usb/setup.d.ts +5 -5
- package/dist/esm/usb/setup.js +46 -46
- package/dist/esm/utils/assembler.d.ts +79 -79
- package/dist/esm/utils/assembler.js +245 -245
- package/dist/esm/utils/bit.d.ts +3 -3
- package/dist/esm/utils/bit.js +9 -9
- package/dist/esm/utils/fifo.d.ts +15 -15
- package/dist/esm/utils/fifo.js +52 -52
- package/dist/esm/utils/logging.d.ts +23 -23
- package/dist/esm/utils/logging.js +44 -44
- package/dist/esm/utils/pio-assembler.d.ts +45 -45
- package/dist/esm/utils/pio-assembler.js +75 -75
- package/dist/esm/utils/time.d.ts +2 -2
- package/dist/esm/utils/time.js +27 -27
- package/dist/esm/utils/timer32.d.ts +57 -57
- package/dist/esm/utils/timer32.js +203 -203
- package/package.json +38 -27
- package/dist/esm/package.json +0 -1
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export declare function opcodeADCS(Rdn: number, Rm: number): number;
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export declare function opcodeADDS1(Rd: number, Rn: number, imm3: number): number;
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export declare function opcodeADDS2(Rdn: number, imm8: number): number;
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export declare function opcodeADDspPlusImm(Rd: number, imm8: number): number;
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export declare function opcodeADDsp2(imm: number): number;
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export declare function opcodeADDSreg(Rd: number, Rn: number, Rm: number): number;
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export declare function opcodeADDreg(Rdn: number, Rm: number): number;
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export declare function opcodeADR(Rd: number, imm8: number): number;
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export declare function opcodeANDS(Rn: number, Rm: number): number;
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export declare function opcodeASRS(Rd: number, Rm: number, imm5: number): number;
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export declare function opcodeASRSreg(Rdn: number, Rm: number): number;
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export declare function opcodeBT1(cond: number, imm8: number): number;
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export declare function opcodeBT2(imm11: number): number;
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export declare function opcodeBICS(Rdn: number, Rm: number): number;
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export declare function opcodeBL(imm: number): number;
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export declare function opcodeBLX(Rm: number): number;
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export declare function opcodeBX(Rm: number): number;
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export declare function opcodeCMN(Rn: number, Rm: number): number;
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export declare function opcodeCMPimm(Rn: number, Imm8: number): number;
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export declare function opcodeCMPregT1(Rn: number, Rm: number): number;
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export declare function opcodeCMPregT2(Rn: number, Rm: number): number;
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export declare function opcodeDMBSY(): number;
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export declare function opcodeDSBSY(): number;
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export declare function opcodeEORS(Rdn: number, Rm: number): number;
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export declare function opcodeISBSY(): number;
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export declare function opcodeLDMIA(Rn: number, registers: number): number;
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export declare function opcodeLDRreg(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeLDRimm(Rt: number, Rn: number, imm5: number): number;
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export declare function opcodeLDRlit(Rt: number, imm8: number): number;
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export declare function opcodeLDRB(Rt: number, Rn: number, imm5: number): number;
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export declare function opcodeLDRsp(Rt: number, imm8: number): number;
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export declare function opcodeLDRBreg(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeLDRH(Rt: number, Rn: number, imm5: number): number;
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export declare function opcodeLDRHreg(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeLDRSB(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeLDRSH(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeLSLSreg(Rdn: number, Rm: number): number;
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export declare function opcodeLSLSimm(Rd: number, Rm: number, Imm5: number): number;
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export declare function opcodeLSRS(Rd: number, Rm: number, imm5: number): number;
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export declare function opcodeLSRSreg(Rdn: number, Rm: number): number;
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export declare function opcodeMOV(Rd: number, Rm: number): number;
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export declare function opcodeMOVS(Rd: number, imm8: number): number;
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export declare function opcodeMOVSreg(Rd: number, Rm: number): number;
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export declare function opcodeMRS(Rd: number, specReg: number): number;
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export declare function opcodeMSR(specReg: number, Rn: number): number;
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export declare function opcodeMULS(Rn: number, Rdm: number): number;
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export declare function opcodeMVNS(Rd: number, Rm: number): number;
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export declare function opcodeNOP(): number;
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export declare function opcodeORRS(Rn: number, Rm: number): number;
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export declare function opcodePOP(P: boolean, registerList: number): number;
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export declare function opcodePUSH(M: boolean, registerList: number): number;
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export declare function opcodeREV(Rd: number, Rn: number): number;
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export declare function opcodeREV16(Rd: number, Rn: number): number;
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export declare function opcodeREVSH(Rd: number, Rn: number): number;
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export declare function opcodeROR(Rdn: number, Rm: number): number;
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export declare function opcodeRSBS(Rd: number, Rn: number): number;
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export declare function opcodeSBCS(Rn: number, Rm: number): number;
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export declare function opcodeSTMIA(Rn: number, registers: number): number;
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export declare function opcodeSTR(Rt: number, Rm: number, imm5: number): number;
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export declare function opcodeSTRsp(Rt: number, imm8: number): number;
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export declare function opcodeSTRreg(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeSTRB(Rt: number, Rm: number, imm5: number): number;
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export declare function opcodeSTRBreg(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeSTRH(Rt: number, Rm: number, imm5: number): number;
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export declare function opcodeSTRHreg(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeSUBS1(Rd: number, Rn: number, imm3: number): number;
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export declare function opcodeSUBS2(Rdn: number, imm8: number): number;
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export declare function opcodeSUBSreg(Rd: number, Rn: number, Rm: number): number;
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export declare function opcodeSUBsp(imm: number): number;
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export declare function opcodeSVC(imm8: number): number;
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export declare function opcodeSXTB(Rd: number, Rm: number): number;
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export declare function opcodeSXTH(Rd: number, Rm: number): number;
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export declare function opcodeTST(Rm: number, Rn: number): number;
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export declare function opcodeUXTB(Rd: number, Rm: number): number;
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export declare function opcodeUDF(imm8: number): number;
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export declare function opcodeUDF2(imm16: number): number;
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export declare function opcodeUXTH(Rd: number, Rm: number): number;
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export declare function opcodeWFI(): number;
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export declare function opcodeYIELD(): number;
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export declare function opcodeADCS(Rdn: number, Rm: number): number;
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export declare function opcodeADDS1(Rd: number, Rn: number, imm3: number): number;
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export declare function opcodeADDS2(Rdn: number, imm8: number): number;
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export declare function opcodeADDspPlusImm(Rd: number, imm8: number): number;
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export declare function opcodeADDsp2(imm: number): number;
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export declare function opcodeADDSreg(Rd: number, Rn: number, Rm: number): number;
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export declare function opcodeADDreg(Rdn: number, Rm: number): number;
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export declare function opcodeADR(Rd: number, imm8: number): number;
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export declare function opcodeANDS(Rn: number, Rm: number): number;
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export declare function opcodeASRS(Rd: number, Rm: number, imm5: number): number;
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export declare function opcodeASRSreg(Rdn: number, Rm: number): number;
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export declare function opcodeBT1(cond: number, imm8: number): number;
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export declare function opcodeBT2(imm11: number): number;
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export declare function opcodeBICS(Rdn: number, Rm: number): number;
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export declare function opcodeBL(imm: number): number;
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export declare function opcodeBLX(Rm: number): number;
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export declare function opcodeBX(Rm: number): number;
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export declare function opcodeCMN(Rn: number, Rm: number): number;
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export declare function opcodeCMPimm(Rn: number, Imm8: number): number;
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export declare function opcodeCMPregT1(Rn: number, Rm: number): number;
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export declare function opcodeCMPregT2(Rn: number, Rm: number): number;
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export declare function opcodeDMBSY(): number;
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export declare function opcodeDSBSY(): number;
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export declare function opcodeEORS(Rdn: number, Rm: number): number;
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export declare function opcodeISBSY(): number;
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export declare function opcodeLDMIA(Rn: number, registers: number): number;
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export declare function opcodeLDRreg(Rt: number, Rn: number, Rm: number): number;
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export declare function opcodeLDRimm(Rt: number, Rn: number, imm5: number): number;
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export declare function opcodeLDRlit(Rt: number, imm8: number): number;
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export declare function opcodeLDRB(Rt: number, Rn: number, imm5: number): number;
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export declare function opcodeLDRsp(Rt: number, imm8: number): number;
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|
+
export declare function opcodeLDRBreg(Rt: number, Rn: number, Rm: number): number;
|
|
33
|
+
export declare function opcodeLDRH(Rt: number, Rn: number, imm5: number): number;
|
|
34
|
+
export declare function opcodeLDRHreg(Rt: number, Rn: number, Rm: number): number;
|
|
35
|
+
export declare function opcodeLDRSB(Rt: number, Rn: number, Rm: number): number;
|
|
36
|
+
export declare function opcodeLDRSH(Rt: number, Rn: number, Rm: number): number;
|
|
37
|
+
export declare function opcodeLSLSreg(Rdn: number, Rm: number): number;
|
|
38
|
+
export declare function opcodeLSLSimm(Rd: number, Rm: number, Imm5: number): number;
|
|
39
|
+
export declare function opcodeLSRS(Rd: number, Rm: number, imm5: number): number;
|
|
40
|
+
export declare function opcodeLSRSreg(Rdn: number, Rm: number): number;
|
|
41
|
+
export declare function opcodeMOV(Rd: number, Rm: number): number;
|
|
42
|
+
export declare function opcodeMOVS(Rd: number, imm8: number): number;
|
|
43
|
+
export declare function opcodeMOVSreg(Rd: number, Rm: number): number;
|
|
44
|
+
export declare function opcodeMRS(Rd: number, specReg: number): number;
|
|
45
|
+
export declare function opcodeMSR(specReg: number, Rn: number): number;
|
|
46
|
+
export declare function opcodeMULS(Rn: number, Rdm: number): number;
|
|
47
|
+
export declare function opcodeMVNS(Rd: number, Rm: number): number;
|
|
48
|
+
export declare function opcodeNOP(): number;
|
|
49
|
+
export declare function opcodeORRS(Rn: number, Rm: number): number;
|
|
50
|
+
export declare function opcodePOP(P: boolean, registerList: number): number;
|
|
51
|
+
export declare function opcodePUSH(M: boolean, registerList: number): number;
|
|
52
|
+
export declare function opcodeREV(Rd: number, Rn: number): number;
|
|
53
|
+
export declare function opcodeREV16(Rd: number, Rn: number): number;
|
|
54
|
+
export declare function opcodeREVSH(Rd: number, Rn: number): number;
|
|
55
|
+
export declare function opcodeROR(Rdn: number, Rm: number): number;
|
|
56
|
+
export declare function opcodeRSBS(Rd: number, Rn: number): number;
|
|
57
|
+
export declare function opcodeSBCS(Rn: number, Rm: number): number;
|
|
58
|
+
export declare function opcodeSTMIA(Rn: number, registers: number): number;
|
|
59
|
+
export declare function opcodeSTR(Rt: number, Rm: number, imm5: number): number;
|
|
60
|
+
export declare function opcodeSTRsp(Rt: number, imm8: number): number;
|
|
61
|
+
export declare function opcodeSTRreg(Rt: number, Rn: number, Rm: number): number;
|
|
62
|
+
export declare function opcodeSTRB(Rt: number, Rm: number, imm5: number): number;
|
|
63
|
+
export declare function opcodeSTRBreg(Rt: number, Rn: number, Rm: number): number;
|
|
64
|
+
export declare function opcodeSTRH(Rt: number, Rm: number, imm5: number): number;
|
|
65
|
+
export declare function opcodeSTRHreg(Rt: number, Rn: number, Rm: number): number;
|
|
66
|
+
export declare function opcodeSUBS1(Rd: number, Rn: number, imm3: number): number;
|
|
67
|
+
export declare function opcodeSUBS2(Rdn: number, imm8: number): number;
|
|
68
|
+
export declare function opcodeSUBSreg(Rd: number, Rn: number, Rm: number): number;
|
|
69
|
+
export declare function opcodeSUBsp(imm: number): number;
|
|
70
|
+
export declare function opcodeSVC(imm8: number): number;
|
|
71
|
+
export declare function opcodeSXTB(Rd: number, Rm: number): number;
|
|
72
|
+
export declare function opcodeSXTH(Rd: number, Rm: number): number;
|
|
73
|
+
export declare function opcodeTST(Rm: number, Rn: number): number;
|
|
74
|
+
export declare function opcodeUXTB(Rd: number, Rm: number): number;
|
|
75
|
+
export declare function opcodeUDF(imm8: number): number;
|
|
76
|
+
export declare function opcodeUDF2(imm16: number): number;
|
|
77
|
+
export declare function opcodeUXTH(Rd: number, Rm: number): number;
|
|
78
|
+
export declare function opcodeWFI(): number;
|
|
79
|
+
export declare function opcodeYIELD(): number;
|
|
@@ -1,245 +1,245 @@
|
|
|
1
|
-
export function opcodeADCS(Rdn, Rm) {
|
|
2
|
-
return (0b0100000101 << 6) | ((Rm & 7) << 3) | (Rdn & 7);
|
|
3
|
-
}
|
|
4
|
-
export function opcodeADDS1(Rd, Rn, imm3) {
|
|
5
|
-
return (0b0001110 << 9) | ((imm3 & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
6
|
-
}
|
|
7
|
-
export function opcodeADDS2(Rdn, imm8) {
|
|
8
|
-
return (0b00110 << 11) | ((Rdn & 7) << 8) | (imm8 & 0xff);
|
|
9
|
-
}
|
|
10
|
-
export function opcodeADDspPlusImm(Rd, imm8) {
|
|
11
|
-
return (0b10101 << 11) | ((Rd & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
12
|
-
}
|
|
13
|
-
export function opcodeADDsp2(imm) {
|
|
14
|
-
return (0b101100000 << 7) | ((imm >> 2) & 0x7f);
|
|
15
|
-
}
|
|
16
|
-
export function opcodeADDSreg(Rd, Rn, Rm) {
|
|
17
|
-
return (0b0001100 << 9) | ((Rm & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
18
|
-
}
|
|
19
|
-
export function opcodeADDreg(Rdn, Rm) {
|
|
20
|
-
return (0b01000100 << 8) | ((Rdn & 0x8) << 4) | ((Rm & 0xf) << 3) | (Rdn & 0x7);
|
|
21
|
-
}
|
|
22
|
-
export function opcodeADR(Rd, imm8) {
|
|
23
|
-
return (0b10100 << 11) | ((Rd & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
24
|
-
}
|
|
25
|
-
export function opcodeANDS(Rn, Rm) {
|
|
26
|
-
return (0b0100000000 << 6) | ((Rm & 7) << 3) | (Rn & 0x7);
|
|
27
|
-
}
|
|
28
|
-
export function opcodeASRS(Rd, Rm, imm5) {
|
|
29
|
-
return (0b00010 << 11) | ((imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
30
|
-
}
|
|
31
|
-
export function opcodeASRSreg(Rdn, Rm) {
|
|
32
|
-
return (0b0100000100 << 6) | ((Rm & 0x7) << 3) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
33
|
-
}
|
|
34
|
-
export function opcodeBT1(cond, imm8) {
|
|
35
|
-
return (0b1101 << 12) | ((cond & 0xf) << 8) | ((imm8 >> 1) & 0x1ff);
|
|
36
|
-
}
|
|
37
|
-
export function opcodeBT2(imm11) {
|
|
38
|
-
return (0b11100 << 11) | ((imm11 >> 1) & 0x7ff);
|
|
39
|
-
}
|
|
40
|
-
export function opcodeBICS(Rdn, Rm) {
|
|
41
|
-
return (0b0100001110 << 6) | ((Rm & 7) << 3) | (Rdn & 7);
|
|
42
|
-
}
|
|
43
|
-
export function opcodeBL(imm) {
|
|
44
|
-
const imm11 = (imm >> 1) & 0x7ff;
|
|
45
|
-
const imm10 = (imm >> 12) & 0x3ff;
|
|
46
|
-
const s = imm < 0 ? 1 : 0;
|
|
47
|
-
const j2 = 1 - (((imm >> 22) & 0x1) ^ s);
|
|
48
|
-
const j1 = 1 - (((imm >> 23) & 0x1) ^ s);
|
|
49
|
-
const opcode = (0b1101 << 28) | (j1 << 29) | (j2 << 27) | (imm11 << 16) | (0b11110 << 11) | (s << 10) | imm10;
|
|
50
|
-
return opcode >>> 0;
|
|
51
|
-
}
|
|
52
|
-
export function opcodeBLX(Rm) {
|
|
53
|
-
return (0b010001111 << 7) | (Rm << 3);
|
|
54
|
-
}
|
|
55
|
-
export function opcodeBX(Rm) {
|
|
56
|
-
return (0b010001110 << 7) | (Rm << 3);
|
|
57
|
-
}
|
|
58
|
-
export function opcodeCMN(Rn, Rm) {
|
|
59
|
-
return (0b0100001011 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
60
|
-
}
|
|
61
|
-
export function opcodeCMPimm(Rn, Imm8) {
|
|
62
|
-
return (0b00101 << 11) | ((Rn & 0x7) << 8) | (Imm8 & 0xff);
|
|
63
|
-
}
|
|
64
|
-
export function opcodeCMPregT1(Rn, Rm) {
|
|
65
|
-
return (0b0100001010 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
66
|
-
}
|
|
67
|
-
export function opcodeCMPregT2(Rn, Rm) {
|
|
68
|
-
return (0b01000101 << 8) | (((Rn >> 3) & 0x1) << 7) | ((Rm & 0xf) << 3) | (Rn & 0x7);
|
|
69
|
-
}
|
|
70
|
-
export function opcodeDMBSY() {
|
|
71
|
-
return 0x8f50f3bf;
|
|
72
|
-
}
|
|
73
|
-
export function opcodeDSBSY() {
|
|
74
|
-
return 0x8f4ff3bf;
|
|
75
|
-
}
|
|
76
|
-
export function opcodeEORS(Rdn, Rm) {
|
|
77
|
-
return (0b0100000001 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
78
|
-
}
|
|
79
|
-
export function opcodeISBSY() {
|
|
80
|
-
return 0x8f6ff3bf;
|
|
81
|
-
}
|
|
82
|
-
export function opcodeLDMIA(Rn, registers) {
|
|
83
|
-
return (0b11001 << 11) | ((Rn & 0x7) << 8) | (registers & 0xff);
|
|
84
|
-
}
|
|
85
|
-
export function opcodeLDRreg(Rt, Rn, Rm) {
|
|
86
|
-
return (0b0101100 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
87
|
-
}
|
|
88
|
-
export function opcodeLDRimm(Rt, Rn, imm5) {
|
|
89
|
-
return (0b01101 << 11) | (((imm5 >> 2) & 0x1f) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
90
|
-
}
|
|
91
|
-
export function opcodeLDRlit(Rt, imm8) {
|
|
92
|
-
return (0b01001 << 11) | ((imm8 >> 2) & 0xff) | ((Rt & 0x7) << 8);
|
|
93
|
-
}
|
|
94
|
-
export function opcodeLDRB(Rt, Rn, imm5) {
|
|
95
|
-
return (0b01111 << 11) | ((imm5 & 0x1f) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
96
|
-
}
|
|
97
|
-
export function opcodeLDRsp(Rt, imm8) {
|
|
98
|
-
return (0b10011 << 11) | ((Rt & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
99
|
-
}
|
|
100
|
-
export function opcodeLDRBreg(Rt, Rn, Rm) {
|
|
101
|
-
return (0b0101110 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
102
|
-
}
|
|
103
|
-
export function opcodeLDRH(Rt, Rn, imm5) {
|
|
104
|
-
return (0b10001 << 11) | (((imm5 >> 1) & 0xf) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
105
|
-
}
|
|
106
|
-
export function opcodeLDRHreg(Rt, Rn, Rm) {
|
|
107
|
-
return (0b0101101 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
108
|
-
}
|
|
109
|
-
export function opcodeLDRSB(Rt, Rn, Rm) {
|
|
110
|
-
return (0b0101011 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
111
|
-
}
|
|
112
|
-
export function opcodeLDRSH(Rt, Rn, Rm) {
|
|
113
|
-
return (0b0101111 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
114
|
-
}
|
|
115
|
-
export function opcodeLSLSreg(Rdn, Rm) {
|
|
116
|
-
return (0b0100000010 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
117
|
-
}
|
|
118
|
-
export function opcodeLSLSimm(Rd, Rm, Imm5) {
|
|
119
|
-
return (0b00000 << 11) | ((Imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
120
|
-
}
|
|
121
|
-
export function opcodeLSRS(Rd, Rm, imm5) {
|
|
122
|
-
return (0b00001 << 11) | ((imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
123
|
-
}
|
|
124
|
-
export function opcodeLSRSreg(Rdn, Rm) {
|
|
125
|
-
return (0b0100000011 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
126
|
-
}
|
|
127
|
-
export function opcodeMOV(Rd, Rm) {
|
|
128
|
-
return (0b01000110 << 8) | ((Rd & 0x8 ? 1 : 0) << 7) | (Rm << 3) | (Rd & 0x7);
|
|
129
|
-
}
|
|
130
|
-
export function opcodeMOVS(Rd, imm8) {
|
|
131
|
-
return (0b00100 << 11) | ((Rd & 0x7) << 8) | (imm8 & 0xff);
|
|
132
|
-
}
|
|
133
|
-
export function opcodeMOVSreg(Rd, Rm) {
|
|
134
|
-
return (0b000000000 << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
135
|
-
}
|
|
136
|
-
export function opcodeMRS(Rd, specReg) {
|
|
137
|
-
return (((0b1000 << 28) | ((Rd & 0xf) << 24) | ((specReg & 0xff) << 16) | 0b1111001111101111) >>> 0);
|
|
138
|
-
}
|
|
139
|
-
export function opcodeMSR(specReg, Rn) {
|
|
140
|
-
return ((0b10001000 << 24) | ((specReg & 0xff) << 16) | (0b111100111000 << 4) | (Rn & 0xf)) >>> 0;
|
|
141
|
-
}
|
|
142
|
-
export function opcodeMULS(Rn, Rdm) {
|
|
143
|
-
return (0b0100001101 << 6) | ((Rn & 7) << 3) | (Rdm & 7);
|
|
144
|
-
}
|
|
145
|
-
export function opcodeMVNS(Rd, Rm) {
|
|
146
|
-
return (0b0100001111 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
147
|
-
}
|
|
148
|
-
export function opcodeNOP() {
|
|
149
|
-
return 0b1011111100000000;
|
|
150
|
-
}
|
|
151
|
-
export function opcodeORRS(Rn, Rm) {
|
|
152
|
-
return (0b0100001100 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
153
|
-
}
|
|
154
|
-
export function opcodePOP(P, registerList) {
|
|
155
|
-
return (0b1011110 << 9) | ((P ? 1 : 0) << 8) | registerList;
|
|
156
|
-
}
|
|
157
|
-
export function opcodePUSH(M, registerList) {
|
|
158
|
-
return (0b1011010 << 9) | ((M ? 1 : 0) << 8) | registerList;
|
|
159
|
-
}
|
|
160
|
-
export function opcodeREV(Rd, Rn) {
|
|
161
|
-
return (0b1011101000 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
162
|
-
}
|
|
163
|
-
export function opcodeREV16(Rd, Rn) {
|
|
164
|
-
return (0b1011101001 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
165
|
-
}
|
|
166
|
-
export function opcodeREVSH(Rd, Rn) {
|
|
167
|
-
return (0b1011101011 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
168
|
-
}
|
|
169
|
-
export function opcodeROR(Rdn, Rm) {
|
|
170
|
-
return (0b0100000111 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
171
|
-
}
|
|
172
|
-
export function opcodeRSBS(Rd, Rn) {
|
|
173
|
-
return (0b0100001001 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
174
|
-
}
|
|
175
|
-
export function opcodeSBCS(Rn, Rm) {
|
|
176
|
-
return (0b0100000110 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
177
|
-
}
|
|
178
|
-
export function opcodeSTMIA(Rn, registers) {
|
|
179
|
-
return (0b11000 << 11) | ((Rn & 0x7) << 8) | (registers & 0xff);
|
|
180
|
-
}
|
|
181
|
-
export function opcodeSTR(Rt, Rm, imm5) {
|
|
182
|
-
return (0b01100 << 11) | (((imm5 >> 2) & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rt & 0x7);
|
|
183
|
-
}
|
|
184
|
-
export function opcodeSTRsp(Rt, imm8) {
|
|
185
|
-
return (0b10010 << 11) | ((Rt & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
186
|
-
}
|
|
187
|
-
export function opcodeSTRreg(Rt, Rn, Rm) {
|
|
188
|
-
return (0b0101000 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
189
|
-
}
|
|
190
|
-
export function opcodeSTRB(Rt, Rm, imm5) {
|
|
191
|
-
return (0b01110 << 11) | ((imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rt & 0x7);
|
|
192
|
-
}
|
|
193
|
-
export function opcodeSTRBreg(Rt, Rn, Rm) {
|
|
194
|
-
return (0b0101010 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
195
|
-
}
|
|
196
|
-
export function opcodeSTRH(Rt, Rm, imm5) {
|
|
197
|
-
return (0b10000 << 11) | (((imm5 >> 1) & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rt & 0x7);
|
|
198
|
-
}
|
|
199
|
-
export function opcodeSTRHreg(Rt, Rn, Rm) {
|
|
200
|
-
return (0b0101001 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
201
|
-
}
|
|
202
|
-
export function opcodeSUBS1(Rd, Rn, imm3) {
|
|
203
|
-
return (0b0001111 << 9) | ((imm3 & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
204
|
-
}
|
|
205
|
-
export function opcodeSUBS2(Rdn, imm8) {
|
|
206
|
-
return (0b00111 << 11) | ((Rdn & 7) << 8) | (imm8 & 0xff);
|
|
207
|
-
}
|
|
208
|
-
export function opcodeSUBSreg(Rd, Rn, Rm) {
|
|
209
|
-
return (0b0001101 << 9) | ((Rm & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
210
|
-
}
|
|
211
|
-
export function opcodeSUBsp(imm) {
|
|
212
|
-
return (0b101100001 << 7) | ((imm >> 2) & 0x7f);
|
|
213
|
-
}
|
|
214
|
-
export function opcodeSVC(imm8) {
|
|
215
|
-
return (0b11011111 << 8) | (imm8 & 0xff);
|
|
216
|
-
}
|
|
217
|
-
export function opcodeSXTB(Rd, Rm) {
|
|
218
|
-
return (0b1011001001 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
219
|
-
}
|
|
220
|
-
export function opcodeSXTH(Rd, Rm) {
|
|
221
|
-
return (0b1011001000 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
222
|
-
}
|
|
223
|
-
export function opcodeTST(Rm, Rn) {
|
|
224
|
-
return (0b0100001000 << 6) | ((Rn & 7) << 3) | (Rm & 7);
|
|
225
|
-
}
|
|
226
|
-
export function opcodeUXTB(Rd, Rm) {
|
|
227
|
-
return (0b1011001011 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
228
|
-
}
|
|
229
|
-
export function opcodeUDF(imm8) {
|
|
230
|
-
return ((0b11011110 << 8) | (imm8 & 0xff)) >>> 0;
|
|
231
|
-
}
|
|
232
|
-
export function opcodeUDF2(imm16) {
|
|
233
|
-
const imm12 = imm16 & 0xfff;
|
|
234
|
-
const imm4 = (imm16 >> 12) & 0xf;
|
|
235
|
-
return ((0b111101111111 << 4) | imm4 | (0b1010 << 28) | (imm12 << 16)) >>> 0;
|
|
236
|
-
}
|
|
237
|
-
export function opcodeUXTH(Rd, Rm) {
|
|
238
|
-
return (0b1011001010 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
239
|
-
}
|
|
240
|
-
export function opcodeWFI() {
|
|
241
|
-
return 0b1011111100110000;
|
|
242
|
-
}
|
|
243
|
-
export function opcodeYIELD() {
|
|
244
|
-
return 0b1011111100010000;
|
|
245
|
-
}
|
|
1
|
+
export function opcodeADCS(Rdn, Rm) {
|
|
2
|
+
return (0b0100000101 << 6) | ((Rm & 7) << 3) | (Rdn & 7);
|
|
3
|
+
}
|
|
4
|
+
export function opcodeADDS1(Rd, Rn, imm3) {
|
|
5
|
+
return (0b0001110 << 9) | ((imm3 & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
6
|
+
}
|
|
7
|
+
export function opcodeADDS2(Rdn, imm8) {
|
|
8
|
+
return (0b00110 << 11) | ((Rdn & 7) << 8) | (imm8 & 0xff);
|
|
9
|
+
}
|
|
10
|
+
export function opcodeADDspPlusImm(Rd, imm8) {
|
|
11
|
+
return (0b10101 << 11) | ((Rd & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
12
|
+
}
|
|
13
|
+
export function opcodeADDsp2(imm) {
|
|
14
|
+
return (0b101100000 << 7) | ((imm >> 2) & 0x7f);
|
|
15
|
+
}
|
|
16
|
+
export function opcodeADDSreg(Rd, Rn, Rm) {
|
|
17
|
+
return (0b0001100 << 9) | ((Rm & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
18
|
+
}
|
|
19
|
+
export function opcodeADDreg(Rdn, Rm) {
|
|
20
|
+
return (0b01000100 << 8) | ((Rdn & 0x8) << 4) | ((Rm & 0xf) << 3) | (Rdn & 0x7);
|
|
21
|
+
}
|
|
22
|
+
export function opcodeADR(Rd, imm8) {
|
|
23
|
+
return (0b10100 << 11) | ((Rd & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
24
|
+
}
|
|
25
|
+
export function opcodeANDS(Rn, Rm) {
|
|
26
|
+
return (0b0100000000 << 6) | ((Rm & 7) << 3) | (Rn & 0x7);
|
|
27
|
+
}
|
|
28
|
+
export function opcodeASRS(Rd, Rm, imm5) {
|
|
29
|
+
return (0b00010 << 11) | ((imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
30
|
+
}
|
|
31
|
+
export function opcodeASRSreg(Rdn, Rm) {
|
|
32
|
+
return (0b0100000100 << 6) | ((Rm & 0x7) << 3) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
33
|
+
}
|
|
34
|
+
export function opcodeBT1(cond, imm8) {
|
|
35
|
+
return (0b1101 << 12) | ((cond & 0xf) << 8) | ((imm8 >> 1) & 0x1ff);
|
|
36
|
+
}
|
|
37
|
+
export function opcodeBT2(imm11) {
|
|
38
|
+
return (0b11100 << 11) | ((imm11 >> 1) & 0x7ff);
|
|
39
|
+
}
|
|
40
|
+
export function opcodeBICS(Rdn, Rm) {
|
|
41
|
+
return (0b0100001110 << 6) | ((Rm & 7) << 3) | (Rdn & 7);
|
|
42
|
+
}
|
|
43
|
+
export function opcodeBL(imm) {
|
|
44
|
+
const imm11 = (imm >> 1) & 0x7ff;
|
|
45
|
+
const imm10 = (imm >> 12) & 0x3ff;
|
|
46
|
+
const s = imm < 0 ? 1 : 0;
|
|
47
|
+
const j2 = 1 - (((imm >> 22) & 0x1) ^ s);
|
|
48
|
+
const j1 = 1 - (((imm >> 23) & 0x1) ^ s);
|
|
49
|
+
const opcode = (0b1101 << 28) | (j1 << 29) | (j2 << 27) | (imm11 << 16) | (0b11110 << 11) | (s << 10) | imm10;
|
|
50
|
+
return opcode >>> 0;
|
|
51
|
+
}
|
|
52
|
+
export function opcodeBLX(Rm) {
|
|
53
|
+
return (0b010001111 << 7) | (Rm << 3);
|
|
54
|
+
}
|
|
55
|
+
export function opcodeBX(Rm) {
|
|
56
|
+
return (0b010001110 << 7) | (Rm << 3);
|
|
57
|
+
}
|
|
58
|
+
export function opcodeCMN(Rn, Rm) {
|
|
59
|
+
return (0b0100001011 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
60
|
+
}
|
|
61
|
+
export function opcodeCMPimm(Rn, Imm8) {
|
|
62
|
+
return (0b00101 << 11) | ((Rn & 0x7) << 8) | (Imm8 & 0xff);
|
|
63
|
+
}
|
|
64
|
+
export function opcodeCMPregT1(Rn, Rm) {
|
|
65
|
+
return (0b0100001010 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
66
|
+
}
|
|
67
|
+
export function opcodeCMPregT2(Rn, Rm) {
|
|
68
|
+
return (0b01000101 << 8) | (((Rn >> 3) & 0x1) << 7) | ((Rm & 0xf) << 3) | (Rn & 0x7);
|
|
69
|
+
}
|
|
70
|
+
export function opcodeDMBSY() {
|
|
71
|
+
return 0x8f50f3bf;
|
|
72
|
+
}
|
|
73
|
+
export function opcodeDSBSY() {
|
|
74
|
+
return 0x8f4ff3bf;
|
|
75
|
+
}
|
|
76
|
+
export function opcodeEORS(Rdn, Rm) {
|
|
77
|
+
return (0b0100000001 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
78
|
+
}
|
|
79
|
+
export function opcodeISBSY() {
|
|
80
|
+
return 0x8f6ff3bf;
|
|
81
|
+
}
|
|
82
|
+
export function opcodeLDMIA(Rn, registers) {
|
|
83
|
+
return (0b11001 << 11) | ((Rn & 0x7) << 8) | (registers & 0xff);
|
|
84
|
+
}
|
|
85
|
+
export function opcodeLDRreg(Rt, Rn, Rm) {
|
|
86
|
+
return (0b0101100 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
87
|
+
}
|
|
88
|
+
export function opcodeLDRimm(Rt, Rn, imm5) {
|
|
89
|
+
return (0b01101 << 11) | (((imm5 >> 2) & 0x1f) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
90
|
+
}
|
|
91
|
+
export function opcodeLDRlit(Rt, imm8) {
|
|
92
|
+
return (0b01001 << 11) | ((imm8 >> 2) & 0xff) | ((Rt & 0x7) << 8);
|
|
93
|
+
}
|
|
94
|
+
export function opcodeLDRB(Rt, Rn, imm5) {
|
|
95
|
+
return (0b01111 << 11) | ((imm5 & 0x1f) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
96
|
+
}
|
|
97
|
+
export function opcodeLDRsp(Rt, imm8) {
|
|
98
|
+
return (0b10011 << 11) | ((Rt & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
99
|
+
}
|
|
100
|
+
export function opcodeLDRBreg(Rt, Rn, Rm) {
|
|
101
|
+
return (0b0101110 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
102
|
+
}
|
|
103
|
+
export function opcodeLDRH(Rt, Rn, imm5) {
|
|
104
|
+
return (0b10001 << 11) | (((imm5 >> 1) & 0xf) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
105
|
+
}
|
|
106
|
+
export function opcodeLDRHreg(Rt, Rn, Rm) {
|
|
107
|
+
return (0b0101101 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
108
|
+
}
|
|
109
|
+
export function opcodeLDRSB(Rt, Rn, Rm) {
|
|
110
|
+
return (0b0101011 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
111
|
+
}
|
|
112
|
+
export function opcodeLDRSH(Rt, Rn, Rm) {
|
|
113
|
+
return (0b0101111 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
114
|
+
}
|
|
115
|
+
export function opcodeLSLSreg(Rdn, Rm) {
|
|
116
|
+
return (0b0100000010 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
117
|
+
}
|
|
118
|
+
export function opcodeLSLSimm(Rd, Rm, Imm5) {
|
|
119
|
+
return (0b00000 << 11) | ((Imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
120
|
+
}
|
|
121
|
+
export function opcodeLSRS(Rd, Rm, imm5) {
|
|
122
|
+
return (0b00001 << 11) | ((imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
123
|
+
}
|
|
124
|
+
export function opcodeLSRSreg(Rdn, Rm) {
|
|
125
|
+
return (0b0100000011 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
126
|
+
}
|
|
127
|
+
export function opcodeMOV(Rd, Rm) {
|
|
128
|
+
return (0b01000110 << 8) | ((Rd & 0x8 ? 1 : 0) << 7) | (Rm << 3) | (Rd & 0x7);
|
|
129
|
+
}
|
|
130
|
+
export function opcodeMOVS(Rd, imm8) {
|
|
131
|
+
return (0b00100 << 11) | ((Rd & 0x7) << 8) | (imm8 & 0xff);
|
|
132
|
+
}
|
|
133
|
+
export function opcodeMOVSreg(Rd, Rm) {
|
|
134
|
+
return (0b000000000 << 6) | ((Rm & 0x7) << 3) | (Rd & 0x7);
|
|
135
|
+
}
|
|
136
|
+
export function opcodeMRS(Rd, specReg) {
|
|
137
|
+
return (((0b1000 << 28) | ((Rd & 0xf) << 24) | ((specReg & 0xff) << 16) | 0b1111001111101111) >>> 0);
|
|
138
|
+
}
|
|
139
|
+
export function opcodeMSR(specReg, Rn) {
|
|
140
|
+
return ((0b10001000 << 24) | ((specReg & 0xff) << 16) | (0b111100111000 << 4) | (Rn & 0xf)) >>> 0;
|
|
141
|
+
}
|
|
142
|
+
export function opcodeMULS(Rn, Rdm) {
|
|
143
|
+
return (0b0100001101 << 6) | ((Rn & 7) << 3) | (Rdm & 7);
|
|
144
|
+
}
|
|
145
|
+
export function opcodeMVNS(Rd, Rm) {
|
|
146
|
+
return (0b0100001111 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
147
|
+
}
|
|
148
|
+
export function opcodeNOP() {
|
|
149
|
+
return 0b1011111100000000;
|
|
150
|
+
}
|
|
151
|
+
export function opcodeORRS(Rn, Rm) {
|
|
152
|
+
return (0b0100001100 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
153
|
+
}
|
|
154
|
+
export function opcodePOP(P, registerList) {
|
|
155
|
+
return (0b1011110 << 9) | ((P ? 1 : 0) << 8) | registerList;
|
|
156
|
+
}
|
|
157
|
+
export function opcodePUSH(M, registerList) {
|
|
158
|
+
return (0b1011010 << 9) | ((M ? 1 : 0) << 8) | registerList;
|
|
159
|
+
}
|
|
160
|
+
export function opcodeREV(Rd, Rn) {
|
|
161
|
+
return (0b1011101000 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
162
|
+
}
|
|
163
|
+
export function opcodeREV16(Rd, Rn) {
|
|
164
|
+
return (0b1011101001 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
165
|
+
}
|
|
166
|
+
export function opcodeREVSH(Rd, Rn) {
|
|
167
|
+
return (0b1011101011 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
168
|
+
}
|
|
169
|
+
export function opcodeROR(Rdn, Rm) {
|
|
170
|
+
return (0b0100000111 << 6) | ((Rm & 0x7) << 3) | (Rdn & 0x7);
|
|
171
|
+
}
|
|
172
|
+
export function opcodeRSBS(Rd, Rn) {
|
|
173
|
+
return (0b0100001001 << 6) | ((Rn & 0x7) << 3) | (Rd & 0x7);
|
|
174
|
+
}
|
|
175
|
+
export function opcodeSBCS(Rn, Rm) {
|
|
176
|
+
return (0b0100000110 << 6) | ((Rm & 0x7) << 3) | (Rn & 0x7);
|
|
177
|
+
}
|
|
178
|
+
export function opcodeSTMIA(Rn, registers) {
|
|
179
|
+
return (0b11000 << 11) | ((Rn & 0x7) << 8) | (registers & 0xff);
|
|
180
|
+
}
|
|
181
|
+
export function opcodeSTR(Rt, Rm, imm5) {
|
|
182
|
+
return (0b01100 << 11) | (((imm5 >> 2) & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rt & 0x7);
|
|
183
|
+
}
|
|
184
|
+
export function opcodeSTRsp(Rt, imm8) {
|
|
185
|
+
return (0b10010 << 11) | ((Rt & 7) << 8) | ((imm8 >> 2) & 0xff);
|
|
186
|
+
}
|
|
187
|
+
export function opcodeSTRreg(Rt, Rn, Rm) {
|
|
188
|
+
return (0b0101000 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
189
|
+
}
|
|
190
|
+
export function opcodeSTRB(Rt, Rm, imm5) {
|
|
191
|
+
return (0b01110 << 11) | ((imm5 & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rt & 0x7);
|
|
192
|
+
}
|
|
193
|
+
export function opcodeSTRBreg(Rt, Rn, Rm) {
|
|
194
|
+
return (0b0101010 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
195
|
+
}
|
|
196
|
+
export function opcodeSTRH(Rt, Rm, imm5) {
|
|
197
|
+
return (0b10000 << 11) | (((imm5 >> 1) & 0x1f) << 6) | ((Rm & 0x7) << 3) | (Rt & 0x7);
|
|
198
|
+
}
|
|
199
|
+
export function opcodeSTRHreg(Rt, Rn, Rm) {
|
|
200
|
+
return (0b0101001 << 9) | ((Rm & 0x7) << 6) | ((Rn & 0x7) << 3) | (Rt & 0x7);
|
|
201
|
+
}
|
|
202
|
+
export function opcodeSUBS1(Rd, Rn, imm3) {
|
|
203
|
+
return (0b0001111 << 9) | ((imm3 & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
204
|
+
}
|
|
205
|
+
export function opcodeSUBS2(Rdn, imm8) {
|
|
206
|
+
return (0b00111 << 11) | ((Rdn & 7) << 8) | (imm8 & 0xff);
|
|
207
|
+
}
|
|
208
|
+
export function opcodeSUBSreg(Rd, Rn, Rm) {
|
|
209
|
+
return (0b0001101 << 9) | ((Rm & 0x7) << 6) | ((Rn & 7) << 3) | (Rd & 7);
|
|
210
|
+
}
|
|
211
|
+
export function opcodeSUBsp(imm) {
|
|
212
|
+
return (0b101100001 << 7) | ((imm >> 2) & 0x7f);
|
|
213
|
+
}
|
|
214
|
+
export function opcodeSVC(imm8) {
|
|
215
|
+
return (0b11011111 << 8) | (imm8 & 0xff);
|
|
216
|
+
}
|
|
217
|
+
export function opcodeSXTB(Rd, Rm) {
|
|
218
|
+
return (0b1011001001 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
219
|
+
}
|
|
220
|
+
export function opcodeSXTH(Rd, Rm) {
|
|
221
|
+
return (0b1011001000 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
222
|
+
}
|
|
223
|
+
export function opcodeTST(Rm, Rn) {
|
|
224
|
+
return (0b0100001000 << 6) | ((Rn & 7) << 3) | (Rm & 7);
|
|
225
|
+
}
|
|
226
|
+
export function opcodeUXTB(Rd, Rm) {
|
|
227
|
+
return (0b1011001011 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
228
|
+
}
|
|
229
|
+
export function opcodeUDF(imm8) {
|
|
230
|
+
return ((0b11011110 << 8) | (imm8 & 0xff)) >>> 0;
|
|
231
|
+
}
|
|
232
|
+
export function opcodeUDF2(imm16) {
|
|
233
|
+
const imm12 = imm16 & 0xfff;
|
|
234
|
+
const imm4 = (imm16 >> 12) & 0xf;
|
|
235
|
+
return ((0b111101111111 << 4) | imm4 | (0b1010 << 28) | (imm12 << 16)) >>> 0;
|
|
236
|
+
}
|
|
237
|
+
export function opcodeUXTH(Rd, Rm) {
|
|
238
|
+
return (0b1011001010 << 6) | ((Rm & 7) << 3) | (Rd & 7);
|
|
239
|
+
}
|
|
240
|
+
export function opcodeWFI() {
|
|
241
|
+
return 0b1011111100110000;
|
|
242
|
+
}
|
|
243
|
+
export function opcodeYIELD() {
|
|
244
|
+
return 0b1011111100010000;
|
|
245
|
+
}
|