rp2040js 0.17.17 → 0.18.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/cjs/clock/clock.d.ts +11 -11
- package/dist/cjs/clock/clock.js +2 -2
- package/dist/cjs/clock/mock-clock.d.ts +17 -17
- package/dist/cjs/clock/mock-clock.js +52 -52
- package/dist/cjs/clock/realtime-clock.d.ts +23 -23
- package/dist/cjs/clock/realtime-clock.js +73 -73
- package/dist/cjs/cortex-m0-core.d.ts +87 -87
- package/dist/cjs/cortex-m0-core.js +1251 -1251
- package/dist/cjs/gdb/gdb-connection.d.ts +11 -11
- package/dist/cjs/gdb/gdb-connection.js +57 -57
- package/dist/cjs/gdb/gdb-server.d.ts +23 -23
- package/dist/cjs/gdb/gdb-server.js +232 -232
- package/dist/cjs/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/cjs/gdb/gdb-tcp-server.js +34 -34
- package/dist/cjs/gdb/gdb-utils.d.ts +9 -9
- package/dist/cjs/gdb/gdb-utils.js +48 -48
- package/dist/cjs/gpio-pin.d.ts +56 -56
- package/dist/cjs/gpio-pin.js +216 -216
- package/dist/cjs/index.d.ts +11 -11
- package/dist/cjs/index.js +36 -36
- package/dist/cjs/interpolator.d.ts +36 -36
- package/dist/cjs/interpolator.js +150 -150
- package/dist/cjs/irq.d.ts +29 -29
- package/dist/cjs/irq.js +33 -33
- package/dist/cjs/peripherals/adc.d.ts +52 -52
- package/dist/cjs/peripherals/adc.js +261 -261
- package/dist/cjs/peripherals/busctrl.d.ts +10 -10
- package/dist/cjs/peripherals/busctrl.js +84 -84
- package/dist/cjs/peripherals/clocks.d.ts +9 -9
- package/dist/cjs/peripherals/clocks.js +42 -42
- package/dist/cjs/peripherals/dma.d.ts +109 -109
- package/dist/cjs/peripherals/dma.js +520 -520
- package/dist/cjs/peripherals/i2c.d.ts +54 -54
- package/dist/cjs/peripherals/i2c.js +458 -458
- package/dist/cjs/peripherals/io.d.ts +11 -11
- package/dist/cjs/peripherals/io.js +100 -100
- package/dist/cjs/peripherals/pads.d.ts +13 -13
- package/dist/cjs/peripherals/pads.js +58 -58
- package/dist/cjs/peripherals/peripheral.d.ts +22 -22
- package/dist/cjs/peripherals/peripheral.js +61 -61
- package/dist/cjs/peripherals/pio.d.ts +120 -120
- package/dist/cjs/peripherals/pio.js +1086 -1086
- package/dist/cjs/peripherals/ppb.d.ts +25 -25
- package/dist/cjs/peripherals/ppb.js +229 -229
- package/dist/cjs/peripherals/pwm.d.ts +65 -65
- package/dist/cjs/peripherals/pwm.js +372 -372
- package/dist/cjs/peripherals/reset.d.ts +8 -8
- package/dist/cjs/peripherals/reset.js +40 -40
- package/dist/cjs/peripherals/rtc.d.ts +10 -10
- package/dist/cjs/peripherals/rtc.js +74 -74
- package/dist/cjs/peripherals/spi.d.ts +38 -38
- package/dist/cjs/peripherals/spi.js +240 -240
- package/dist/cjs/peripherals/ssi.d.ts +6 -6
- package/dist/cjs/peripherals/ssi.js +43 -43
- package/dist/cjs/peripherals/syscfg.d.ts +5 -5
- package/dist/cjs/peripherals/syscfg.js +26 -26
- package/dist/cjs/peripherals/sysinfo.d.ts +4 -4
- package/dist/cjs/peripherals/sysinfo.js +22 -22
- package/dist/cjs/peripherals/tbman.d.ts +4 -4
- package/dist/cjs/peripherals/tbman.js +17 -17
- package/dist/cjs/peripherals/timer.d.ts +18 -18
- package/dist/cjs/peripherals/timer.js +156 -156
- package/dist/cjs/peripherals/uart.d.ts +31 -31
- package/dist/cjs/peripherals/uart.js +132 -132
- package/dist/cjs/peripherals/usb.d.ts +29 -29
- package/dist/cjs/peripherals/usb.js +309 -309
- package/dist/cjs/rp2040.d.ts +71 -71
- package/dist/cjs/rp2040.js +361 -361
- package/dist/cjs/sio.d.ts +21 -21
- package/dist/cjs/sio.js +425 -425
- package/dist/cjs/usb/cdc.d.ts +20 -20
- package/dist/cjs/usb/cdc.js +126 -126
- package/dist/cjs/usb/interfaces.d.ts +47 -47
- package/dist/cjs/usb/interfaces.js +46 -46
- package/dist/cjs/usb/setup.d.ts +5 -5
- package/dist/cjs/usb/setup.js +53 -53
- package/dist/cjs/utils/assembler.d.ts +79 -79
- package/dist/cjs/utils/assembler.js +328 -328
- package/dist/cjs/utils/bit.d.ts +3 -3
- package/dist/cjs/utils/bit.js +15 -15
- package/dist/cjs/utils/fifo.d.ts +15 -15
- package/dist/cjs/utils/fifo.js +56 -56
- package/dist/cjs/utils/logging.d.ts +23 -23
- package/dist/cjs/utils/logging.js +48 -48
- package/dist/cjs/utils/pio-assembler.d.ts +45 -45
- package/dist/cjs/utils/pio-assembler.js +87 -87
- package/dist/cjs/utils/time.d.ts +2 -2
- package/dist/cjs/utils/time.js +32 -32
- package/dist/cjs/utils/timer32.d.ts +57 -57
- package/dist/cjs/utils/timer32.js +208 -208
- package/dist/esm/clock/clock.d.ts +11 -11
- package/dist/esm/clock/clock.js +1 -1
- package/dist/esm/clock/mock-clock.d.ts +17 -17
- package/dist/esm/clock/mock-clock.js +47 -47
- package/dist/esm/clock/realtime-clock.d.ts +23 -23
- package/dist/esm/clock/realtime-clock.js +68 -68
- package/dist/esm/cortex-m0-core.d.ts +87 -87
- package/dist/esm/cortex-m0-core.js +1247 -1247
- package/dist/esm/gdb/gdb-connection.d.ts +11 -11
- package/dist/esm/gdb/gdb-connection.js +53 -53
- package/dist/esm/gdb/gdb-server.d.ts +23 -23
- package/dist/esm/gdb/gdb-server.js +228 -228
- package/dist/esm/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/esm/gdb/gdb-tcp-server.js +30 -30
- package/dist/esm/gdb/gdb-utils.d.ts +9 -9
- package/dist/esm/gdb/gdb-utils.js +36 -36
- package/dist/esm/gpio-pin.d.ts +56 -56
- package/dist/esm/gpio-pin.js +212 -212
- package/dist/esm/index.d.ts +11 -11
- package/dist/esm/index.js +11 -11
- package/dist/esm/interpolator.d.ts +36 -36
- package/dist/esm/interpolator.js +145 -145
- package/dist/esm/irq.d.ts +29 -29
- package/dist/esm/irq.js +30 -30
- package/dist/esm/peripherals/adc.d.ts +52 -52
- package/dist/esm/peripherals/adc.js +257 -257
- package/dist/esm/peripherals/busctrl.d.ts +10 -10
- package/dist/esm/peripherals/busctrl.js +80 -80
- package/dist/esm/peripherals/clocks.d.ts +9 -9
- package/dist/esm/peripherals/clocks.js +38 -38
- package/dist/esm/peripherals/dma.d.ts +109 -109
- package/dist/esm/peripherals/dma.js +515 -515
- package/dist/esm/peripherals/i2c.d.ts +54 -54
- package/dist/esm/peripherals/i2c.js +454 -454
- package/dist/esm/peripherals/io.d.ts +11 -11
- package/dist/esm/peripherals/io.js +96 -96
- package/dist/esm/peripherals/pads.d.ts +13 -13
- package/dist/esm/peripherals/pads.js +54 -54
- package/dist/esm/peripherals/peripheral.d.ts +22 -22
- package/dist/esm/peripherals/peripheral.js +55 -55
- package/dist/esm/peripherals/pio.d.ts +120 -120
- package/dist/esm/peripherals/pio.js +1081 -1081
- package/dist/esm/peripherals/ppb.d.ts +25 -25
- package/dist/esm/peripherals/ppb.js +225 -225
- package/dist/esm/peripherals/pwm.d.ts +65 -65
- package/dist/esm/peripherals/pwm.js +368 -368
- package/dist/esm/peripherals/reset.d.ts +8 -8
- package/dist/esm/peripherals/reset.js +36 -36
- package/dist/esm/peripherals/rtc.d.ts +10 -10
- package/dist/esm/peripherals/rtc.js +70 -70
- package/dist/esm/peripherals/spi.d.ts +38 -38
- package/dist/esm/peripherals/spi.js +236 -236
- package/dist/esm/peripherals/ssi.d.ts +6 -6
- package/dist/esm/peripherals/ssi.js +39 -39
- package/dist/esm/peripherals/syscfg.d.ts +5 -5
- package/dist/esm/peripherals/syscfg.js +22 -22
- package/dist/esm/peripherals/sysinfo.d.ts +4 -4
- package/dist/esm/peripherals/sysinfo.js +18 -18
- package/dist/esm/peripherals/tbman.d.ts +4 -4
- package/dist/esm/peripherals/tbman.js +13 -13
- package/dist/esm/peripherals/timer.d.ts +18 -18
- package/dist/esm/peripherals/timer.js +152 -152
- package/dist/esm/peripherals/uart.d.ts +31 -31
- package/dist/esm/peripherals/uart.js +128 -128
- package/dist/esm/peripherals/usb.d.ts +29 -29
- package/dist/esm/peripherals/usb.js +305 -305
- package/dist/esm/rp2040.d.ts +71 -71
- package/dist/esm/rp2040.js +357 -357
- package/dist/esm/sio.d.ts +21 -21
- package/dist/esm/sio.js +421 -421
- package/dist/esm/usb/cdc.d.ts +20 -20
- package/dist/esm/usb/cdc.js +121 -121
- package/dist/esm/usb/interfaces.d.ts +47 -47
- package/dist/esm/usb/interfaces.js +43 -43
- package/dist/esm/usb/setup.d.ts +5 -5
- package/dist/esm/usb/setup.js +46 -46
- package/dist/esm/utils/assembler.d.ts +79 -79
- package/dist/esm/utils/assembler.js +245 -245
- package/dist/esm/utils/bit.d.ts +3 -3
- package/dist/esm/utils/bit.js +9 -9
- package/dist/esm/utils/fifo.d.ts +15 -15
- package/dist/esm/utils/fifo.js +52 -52
- package/dist/esm/utils/logging.d.ts +23 -23
- package/dist/esm/utils/logging.js +44 -44
- package/dist/esm/utils/pio-assembler.d.ts +45 -45
- package/dist/esm/utils/pio-assembler.js +75 -75
- package/dist/esm/utils/time.d.ts +2 -2
- package/dist/esm/utils/time.js +27 -27
- package/dist/esm/utils/timer32.d.ts +57 -57
- package/dist/esm/utils/timer32.js +203 -203
- package/package.json +38 -27
- package/dist/esm/package.json +0 -1
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"use strict";
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Object.defineProperty(exports, "__esModule", { value: true });
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exports.RPI2C = exports.I2CSpeed = exports.I2CMode = void 0;
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const
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const
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const IC_CON = 0x00; // I2C Control Register
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const IC_TAR = 0x04; // I2C Target Address Register
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const IC_SAR = 0x08; // I2C Slave Address Register
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const IC_DATA_CMD = 0x10; // I2C Rx/Tx Data Buffer and Command Register
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const IC_SS_SCL_HCNT = 0x14; // Standard Speed I2C Clock SCL High Count Register
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const IC_SS_SCL_LCNT = 0x18; // Standard Speed I2C Clock SCL Low Count Register
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const IC_FS_SCL_HCNT = 0x1c; // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
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const IC_FS_SCL_LCNT = 0x20; // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
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const IC_INTR_STAT = 0x2c; // I2C Interrupt Status Register
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const IC_INTR_MASK = 0x30; // I2C Interrupt Mask Register
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const IC_RAW_INTR_STAT = 0x34; // I2C Raw Interrupt Status Register
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const IC_RX_TL = 0x38; // I2C Receive FIFO Threshold Register
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const IC_TX_TL = 0x3c; // I2C Transmit FIFO Threshold Register
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const IC_CLR_INTR = 0x40; // Clear Combined and Individual Interrupt Register
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const IC_CLR_RX_UNDER = 0x44; // Clear RX_UNDER Interrupt Register
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const IC_CLR_RX_OVER = 0x48; // Clear RX_OVER Interrupt Register
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const IC_CLR_TX_OVER = 0x4c; // Clear TX_OVER Interrupt Register
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const IC_CLR_RD_REQ = 0x50; // Clear RD_REQ Interrupt Register
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const IC_CLR_TX_ABRT = 0x54; // Clear TX_ABRT Interrupt Register
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const IC_CLR_RX_DONE = 0x58; // Clear RX_DONE Interrupt Register
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const IC_CLR_ACTIVITY = 0x5c; // Clear ACTIVITY Interrupt Register
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const IC_CLR_STOP_DET = 0x60; // Clear STOP_DET Interrupt Register
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const IC_CLR_START_DET = 0x64; // Clear START_DET Interrupt Register
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const IC_CLR_GEN_CALL = 0x68; // Clear GEN_CALL Interrupt Register
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const IC_ENABLE = 0x6c; // I2C ENABLE Register
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const IC_STATUS = 0x70; // I2C STATUS Register
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const IC_TXFLR = 0x74; // I2C Transmit FIFO Level Register
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const IC_RXFLR = 0x78; // I2C Receive FIFO Level Register
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const IC_SDA_HOLD = 0x7c; // I2C SDA Hold Time Length Register
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const IC_TX_ABRT_SOURCE = 0x80; // I2C Transmit Abort Source Register
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const IC_SLV_DATA_NACK_ONLY = 0x84; // Generate Slave Data NACK Register
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const IC_DMA_CR = 0x88; // DMA Control Register
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const IC_DMA_TDLR = 0x8c; // DMA Transmit Data Level Register
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const IC_DMA_RDLR = 0x90; // DMA Transmit Data Level Register
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const IC_SDA_SETUP = 0x94; // I2C SDA Setup Register
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const IC_ACK_GENERAL_CALL = 0x98; // I2C ACK General Call Register
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const IC_ENABLE_STATUS = 0x9c; // I2C Enable Status Register
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const IC_FS_SPKLEN = 0xa0; // I2C SS, FS or FM+ spike suppression limit
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const IC_CLR_RESTART_DET = 0xa8; // Clear RESTART_DET Interrupt Register
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const IC_COMP_PARAM_1 = 0xf4; // Component Parameter Register 1
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const IC_COMP_VERSION = 0xf8; // I2C Component Version Register
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const IC_COMP_TYPE = 0xfc; // I2C Component Type Register
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// IC_CON bits:
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const STOP_DET_IF_MASTER_ACTIVE = 1 << 10;
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const RX_FIFO_FULL_HLD_CTRL = 1 << 9;
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const TX_EMPTY_CTRL = 1 << 8;
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const STOP_DET_IFADDRESSED = 1 << 7;
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const IC_SLAVE_DISABLE = 1 << 6;
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const IC_RESTART_EN = 1 << 5;
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const IC_10BITADDR_MASTER = 1 << 4;
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const IC_10BITADDR_SLAVE = 1 << 3;
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const SPEED_SHIFT = 1;
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const SPEED_MASK = 0x3;
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const MASTER_MODE = 1 << 0;
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// IC_TAR bits:
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const SPECIAL = 1 << 11;
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const GC_OR_START = 1 << 10;
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// IC_STATUS bits:
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const SLV_ACTIVITY = 1 << 6;
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const MST_ACTIVITY = 1 << 5;
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const RFF = 1 << 4;
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const RFNE = 1 << 3;
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const TFE = 1 << 2;
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const TFNF = 1 << 1;
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const ACTIVITY = 1 << 0;
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// IC_ENABLE bits:
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const TX_CMD_BLOCK = 1 << 2;
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const ABORT = 1 << 1;
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const ENABLE = 1 << 0;
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// IC_TX_ABRT_SOURCE bits:
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const TX_FLUSH_CNT_MASK = 0x1ff;
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const TX_FLUSH_CNT_SHIFT = 23;
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const ABRT_USER_ABRT = 1 << 16;
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const ABRT_SLVRD_INT = 1 << 15;
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const ABRT_SLV_ARBLOST = 1 << 14;
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const ABRT_SLVFLUSH_TXFIFO = 1 << 13;
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const ARB_LOST = 1 << 12;
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const ABRT_MASTER_DIS = 1 << 11;
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const ABRT_10B_RD_NORSTRT = 1 << 10;
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const ABRT_SBYTE_NORSTRT = 1 << 9;
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const ABRT_HS_NORSTRT = 1 << 8;
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const ABRT_SBYTE_ACKDET = 1 << 7;
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const ABRT_HS_ACKDET = 1 << 6;
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const ABRT_GCALL_READ = 1 << 5;
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const ABRT_GCALL_NOACK = 1 << 4;
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const ABRT_TXDATA_NOACK = 1 << 3;
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const ABRT_10ADDR2_NOACK = 1 << 2;
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const ABRT_10ADDR1_NOACK = 1 << 1;
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const ABRT_7B_ADDR_NOACK = 1 << 0;
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/* Connection parameters */
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var I2CMode;
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(function (I2CMode) {
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I2CMode[I2CMode["Write"] = 0] = "Write";
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I2CMode[I2CMode["Read"] = 1] = "Read";
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})(I2CMode
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var I2CSpeed;
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(function (I2CSpeed) {
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I2CSpeed[I2CSpeed["Invalid"] = 0] = "Invalid";
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/* standard mode (100 kbit/s) */
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I2CSpeed[I2CSpeed["Standard"] = 1] = "Standard";
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/* fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) */
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I2CSpeed[I2CSpeed["FastMode"] = 2] = "FastMode";
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/* high speed mode (3.4 Mbit/s) */
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I2CSpeed[I2CSpeed["HighSpeedMode"] = 3] = "HighSpeedMode";
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})(I2CSpeed
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var I2CState;
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(function (I2CState) {
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I2CState[I2CState["Idle"] = 0] = "Idle";
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I2CState[I2CState["Start"] = 1] = "Start";
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I2CState[I2CState["Connect"] = 2] = "Connect";
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I2CState[I2CState["Connected"] = 3] = "Connected";
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I2CState[I2CState["Stop"] = 4] = "Stop";
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})(I2CState || (I2CState = {}));
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// Interrupts
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const R_RESTART_DET = 1 << 12; // Slave mode only
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const R_GEN_CALL = 1 << 11;
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const R_START_DET = 1 << 10;
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const R_STOP_DET = 1 << 9;
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const R_ACTIVITY = 1 << 8;
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const R_RX_DONE = 1 << 7;
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const R_TX_ABRT = 1 << 6;
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const R_RD_REQ = 1 << 5;
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128
|
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const R_TX_EMPTY = 1 << 4;
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129
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const R_TX_OVER = 1 << 3;
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130
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const R_RX_FULL = 1 << 2;
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131
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const R_RX_OVER = 1 << 1;
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132
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const R_RX_UNDER = 1 << 0;
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133
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// FIFO entry bits
|
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134
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const FIRST_DATA_BYTE = 1 << 10;
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135
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const RESTART = 1 << 10;
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136
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const STOP = 1 << 9;
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137
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const CMD = 1 << 8; // 0 for write, 1 for read
|
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138
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class RPI2C extends
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139
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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this.
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}
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174
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checkInterrupts() {
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175
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this.rp2040.setInterrupt(this.irq, !!this.intStatus);
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176
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}
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177
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clearInterrupts(mask) {
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178
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if (this.intRaw & mask) {
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179
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this.intRaw &= ~mask;
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180
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this.checkInterrupts();
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181
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return 1;
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182
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}
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else {
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return 0;
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185
|
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}
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186
|
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}
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187
|
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setInterrupts(mask) {
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188
|
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if (!(this.intRaw & mask)) {
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189
|
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this.intRaw |= mask;
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190
|
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this.checkInterrupts();
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191
|
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}
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192
|
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}
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193
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abort(reason) {
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194
|
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this.abortSource &= ~TX_FLUSH_CNT_MASK;
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195
|
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this.abortSource |= reason | (this.txFIFO.itemCount << TX_FLUSH_CNT_SHIFT);
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196
|
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this.txFIFO.reset();
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197
|
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this.setInterrupts(R_TX_ABRT);
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198
|
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}
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199
|
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nextCommand() {
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200
|
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const enabled = this.enable & ENABLE;
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201
|
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const blocked = this.enable & TX_CMD_BLOCK;
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202
|
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if (this.txFIFO.empty || this.busy || blocked || !enabled) {
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203
|
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return;
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|
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}
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205
|
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this.busy = true;
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206
|
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const restart = !!(this.txFIFO.peek() & RESTART) && !this.pendingRestart && !this.stop;
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207
|
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if (this.state === I2CState.Idle || restart) {
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|
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this.pendingRestart = restart;
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209
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this.stop = false;
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210
|
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this.state = I2CState.Start;
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211
|
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this.onStart(restart);
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212
|
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return;
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213
|
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}
|
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214
|
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this.pendingRestart = false;
|
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215
|
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const cmd = this.txFIFO.pull();
|
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216
|
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const readMode = !!(cmd & CMD);
|
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217
|
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this.stop = !!(cmd & STOP);
|
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218
|
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if (readMode) {
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219
|
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this.onReadByte(!this.stop);
|
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220
|
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}
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221
|
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else {
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222
|
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this.onWriteByte(cmd & 0xff);
|
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223
|
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}
|
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224
|
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if (this.txFIFO.itemCount <= this.txThreshold) {
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225
|
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this.setInterrupts(R_TX_EMPTY);
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226
|
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}
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227
|
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}
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228
|
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pushRX(value) {
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229
|
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if (this.rxFIFO.full) {
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230
|
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this.setInterrupts(R_RX_OVER);
|
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231
|
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return;
|
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232
|
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}
|
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233
|
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this.rxFIFO.push(value);
|
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234
|
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if (this.rxFIFO.itemCount > this.rxThreshold) {
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235
|
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this.setInterrupts(R_RX_FULL);
|
|
236
|
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}
|
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237
|
-
}
|
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238
|
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completeStart() {
|
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239
|
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if (this.txFIFO.empty || this.state !== I2CState.Start || this.stop) {
|
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240
|
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this.onStop();
|
|
241
|
-
return;
|
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242
|
-
}
|
|
243
|
-
const mode = this.txFIFO.peek() & CMD ? I2CMode.Read : I2CMode.Write;
|
|
244
|
-
this.state = I2CState.Connect;
|
|
245
|
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this.setInterrupts(R_START_DET);
|
|
246
|
-
const addressMask = this.masterBits === 10 ? 0x3ff : 0xff;
|
|
247
|
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this.onConnect(this.targetAddress & addressMask, mode);
|
|
248
|
-
}
|
|
249
|
-
completeConnect(ack, nackByte = 0) {
|
|
250
|
-
if (!ack || this.stop) {
|
|
251
|
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if (!ack) {
|
|
252
|
-
if (!this.targetAddress) {
|
|
253
|
-
this.abort(ABRT_GCALL_NOACK);
|
|
254
|
-
}
|
|
255
|
-
else if (this.control & IC_10BITADDR_MASTER) {
|
|
256
|
-
this.abort(nackByte === 0 ? ABRT_10ADDR1_NOACK : ABRT_10ADDR2_NOACK);
|
|
257
|
-
}
|
|
258
|
-
else {
|
|
259
|
-
this.abort(ABRT_7B_ADDR_NOACK);
|
|
260
|
-
}
|
|
261
|
-
}
|
|
262
|
-
this.state = I2CState.Stop;
|
|
263
|
-
this.onStop();
|
|
264
|
-
return;
|
|
265
|
-
}
|
|
266
|
-
this.state = I2CState.Connected;
|
|
267
|
-
this.busy = false;
|
|
268
|
-
this.firstByte = true;
|
|
269
|
-
this.nextCommand();
|
|
270
|
-
}
|
|
271
|
-
completeWrite(ack) {
|
|
272
|
-
if (!ack || this.stop) {
|
|
273
|
-
if (!ack) {
|
|
274
|
-
this.abort(ABRT_TXDATA_NOACK);
|
|
275
|
-
}
|
|
276
|
-
this.state = I2CState.Stop;
|
|
277
|
-
this.onStop();
|
|
278
|
-
return;
|
|
279
|
-
}
|
|
280
|
-
this.busy = false;
|
|
281
|
-
this.nextCommand();
|
|
282
|
-
}
|
|
283
|
-
completeRead(value) {
|
|
284
|
-
this.pushRX(value | (this.firstByte ? FIRST_DATA_BYTE : 0));
|
|
285
|
-
if (this.stop) {
|
|
286
|
-
this.state = I2CState.Stop;
|
|
287
|
-
this.onStop();
|
|
288
|
-
return;
|
|
289
|
-
}
|
|
290
|
-
this.firstByte = false;
|
|
291
|
-
this.busy = false;
|
|
292
|
-
this.nextCommand();
|
|
293
|
-
}
|
|
294
|
-
completeStop() {
|
|
295
|
-
this.state = I2CState.Idle;
|
|
296
|
-
this.setInterrupts(R_STOP_DET);
|
|
297
|
-
this.busy = false;
|
|
298
|
-
this.pendingRestart = false;
|
|
299
|
-
if (this.enable & ABORT) {
|
|
300
|
-
this.enable &= ~ABORT;
|
|
301
|
-
}
|
|
302
|
-
else {
|
|
303
|
-
this.nextCommand();
|
|
304
|
-
}
|
|
305
|
-
}
|
|
306
|
-
arbitrationLost() {
|
|
307
|
-
this.state = I2CState.Idle;
|
|
308
|
-
this.busy = false;
|
|
309
|
-
this.abort(ARB_LOST);
|
|
310
|
-
}
|
|
311
|
-
readUint32(offset) {
|
|
312
|
-
switch (offset) {
|
|
313
|
-
case IC_CON:
|
|
314
|
-
return this.control;
|
|
315
|
-
case IC_TAR:
|
|
316
|
-
return this.targetAddress;
|
|
317
|
-
case IC_SAR:
|
|
318
|
-
return this.slaveAddress;
|
|
319
|
-
case IC_DATA_CMD:
|
|
320
|
-
if (this.rxFIFO.empty) {
|
|
321
|
-
this.setInterrupts(R_RX_UNDER);
|
|
322
|
-
return 0;
|
|
323
|
-
}
|
|
324
|
-
this.clearInterrupts(R_RX_FULL);
|
|
325
|
-
return this.rxFIFO.pull();
|
|
326
|
-
case IC_INTR_STAT:
|
|
327
|
-
return this.intStatus;
|
|
328
|
-
case IC_INTR_MASK:
|
|
329
|
-
return this.intEnable;
|
|
330
|
-
case IC_RAW_INTR_STAT:
|
|
331
|
-
return this.intRaw;
|
|
332
|
-
case IC_RX_TL:
|
|
333
|
-
return this.rxThreshold;
|
|
334
|
-
case IC_TX_TL:
|
|
335
|
-
return this.txThreshold;
|
|
336
|
-
case IC_CLR_INTR:
|
|
337
|
-
this.abortSource &= ABRT_SBYTE_NORSTRT; // Clear IC_TX_ABRT_SOURCE, expect for bit 9
|
|
338
|
-
return this.clearInterrupts(R_RX_UNDER |
|
|
339
|
-
R_RX_OVER |
|
|
340
|
-
R_TX_OVER |
|
|
341
|
-
R_RD_REQ |
|
|
342
|
-
R_TX_ABRT |
|
|
343
|
-
R_RX_DONE |
|
|
344
|
-
R_ACTIVITY |
|
|
345
|
-
R_STOP_DET |
|
|
346
|
-
R_START_DET |
|
|
347
|
-
R_GEN_CALL);
|
|
348
|
-
case IC_CLR_RX_UNDER:
|
|
349
|
-
return this.clearInterrupts(R_RX_UNDER);
|
|
350
|
-
case IC_CLR_RX_OVER:
|
|
351
|
-
return this.clearInterrupts(R_RX_OVER);
|
|
352
|
-
case IC_CLR_TX_OVER:
|
|
353
|
-
return this.clearInterrupts(R_TX_OVER);
|
|
354
|
-
case IC_CLR_RD_REQ:
|
|
355
|
-
return this.clearInterrupts(R_RD_REQ);
|
|
356
|
-
case IC_CLR_TX_ABRT:
|
|
357
|
-
this.abortSource &= ABRT_SBYTE_NORSTRT; // Clear IC_TX_ABRT_SOURCE, expect for bit 9
|
|
358
|
-
return this.clearInterrupts(R_TX_ABRT);
|
|
359
|
-
case IC_CLR_RX_DONE:
|
|
360
|
-
return this.clearInterrupts(R_RX_DONE);
|
|
361
|
-
case IC_CLR_ACTIVITY:
|
|
362
|
-
return this.clearInterrupts(R_ACTIVITY);
|
|
363
|
-
case IC_CLR_STOP_DET:
|
|
364
|
-
return this.clearInterrupts(R_STOP_DET);
|
|
365
|
-
case IC_CLR_START_DET:
|
|
366
|
-
return this.clearInterrupts(R_START_DET);
|
|
367
|
-
case IC_CLR_GEN_CALL:
|
|
368
|
-
return this.clearInterrupts(R_GEN_CALL);
|
|
369
|
-
case IC_ENABLE:
|
|
370
|
-
return this.enable;
|
|
371
|
-
case IC_STATUS:
|
|
372
|
-
return ((this.state !== I2CState.Idle ? MST_ACTIVITY | ACTIVITY : 0) |
|
|
373
|
-
(this.rxFIFO.full ? RFF : 0) |
|
|
374
|
-
(!this.rxFIFO.empty ? RFNE : 0) |
|
|
375
|
-
(this.txFIFO.empty ? TFE : 0) |
|
|
376
|
-
(!this.txFIFO.full ? TFNF : 0));
|
|
377
|
-
case IC_TXFLR:
|
|
378
|
-
return this.txFIFO.itemCount;
|
|
379
|
-
case IC_RXFLR:
|
|
380
|
-
return this.rxFIFO.itemCount;
|
|
381
|
-
case IC_TX_ABRT_SOURCE: {
|
|
382
|
-
const value = this.abortSource;
|
|
383
|
-
this.abortSource &= ABRT_SBYTE_NORSTRT; // Clear IC_TX_ABRT_SOURCE, expect for bit 9
|
|
384
|
-
return value;
|
|
385
|
-
}
|
|
386
|
-
case IC_COMP_PARAM_1:
|
|
387
|
-
// From the datasheet:
|
|
388
|
-
// Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only
|
|
389
|
-
// register that contains encoded information about the component's parameter settings.
|
|
390
|
-
return 0;
|
|
391
|
-
case IC_COMP_VERSION:
|
|
392
|
-
return 0x3230312a;
|
|
393
|
-
case IC_COMP_TYPE:
|
|
394
|
-
return 0x44570140;
|
|
395
|
-
}
|
|
396
|
-
return super.readUint32(offset);
|
|
397
|
-
}
|
|
398
|
-
writeUint32(offset, value) {
|
|
399
|
-
switch (offset) {
|
|
400
|
-
case IC_CON:
|
|
401
|
-
if (((value >> SPEED_SHIFT) & SPEED_MASK) === I2CSpeed.Invalid) {
|
|
402
|
-
value = (value & ~(SPEED_MASK << SPEED_SHIFT)) | (I2CSpeed.HighSpeedMode << SPEED_SHIFT);
|
|
403
|
-
}
|
|
404
|
-
this.control = value;
|
|
405
|
-
return;
|
|
406
|
-
case IC_TAR:
|
|
407
|
-
this.targetAddress = value & 0x3ff;
|
|
408
|
-
return;
|
|
409
|
-
case IC_SAR:
|
|
410
|
-
this.slaveAddress = value & 0x3ff;
|
|
411
|
-
return;
|
|
412
|
-
case IC_DATA_CMD:
|
|
413
|
-
if (this.txFIFO.full) {
|
|
414
|
-
this.setInterrupts(R_TX_OVER);
|
|
415
|
-
}
|
|
416
|
-
else {
|
|
417
|
-
this.txFIFO.push(value);
|
|
418
|
-
this.clearInterrupts(R_TX_EMPTY);
|
|
419
|
-
this.nextCommand();
|
|
420
|
-
}
|
|
421
|
-
return;
|
|
422
|
-
case IC_RX_TL:
|
|
423
|
-
this.rxThreshold = value & 0xff;
|
|
424
|
-
if (this.rxThreshold > this.rxFIFO.size) {
|
|
425
|
-
this.rxThreshold = this.rxFIFO.size;
|
|
426
|
-
}
|
|
427
|
-
return;
|
|
428
|
-
case IC_TX_TL:
|
|
429
|
-
this.txThreshold = value & 0xff;
|
|
430
|
-
if (this.txThreshold > this.txFIFO.size) {
|
|
431
|
-
this.txThreshold = this.txFIFO.size;
|
|
432
|
-
}
|
|
433
|
-
return;
|
|
434
|
-
case IC_ENABLE:
|
|
435
|
-
// ABORT bit can only be set by software, not cleared.
|
|
436
|
-
value |= this.enable & ABORT;
|
|
437
|
-
if (value & ABORT) {
|
|
438
|
-
if (this.state === I2CState.Idle) {
|
|
439
|
-
value &= ~ABORT;
|
|
440
|
-
}
|
|
441
|
-
else {
|
|
442
|
-
this.abort(ABRT_USER_ABRT);
|
|
443
|
-
this.stop = true;
|
|
444
|
-
}
|
|
445
|
-
}
|
|
446
|
-
if (!(value & ENABLE)) {
|
|
447
|
-
this.txFIFO.reset();
|
|
448
|
-
this.rxFIFO.reset();
|
|
449
|
-
}
|
|
450
|
-
this.enable = value;
|
|
451
|
-
this.nextCommand(); // TX_CMD_BLOCK may have changed
|
|
452
|
-
return;
|
|
453
|
-
default:
|
|
454
|
-
super.writeUint32(offset, value);
|
|
455
|
-
}
|
|
456
|
-
}
|
|
457
|
-
}
|
|
458
|
-
exports.RPI2C = RPI2C;
|
|
1
|
+
"use strict";
|
|
2
|
+
Object.defineProperty(exports, "__esModule", { value: true });
|
|
3
|
+
exports.RPI2C = exports.I2CSpeed = exports.I2CMode = void 0;
|
|
4
|
+
const fifo_js_1 = require("../utils/fifo.js");
|
|
5
|
+
const peripheral_js_1 = require("./peripheral.js");
|
|
6
|
+
const IC_CON = 0x00; // I2C Control Register
|
|
7
|
+
const IC_TAR = 0x04; // I2C Target Address Register
|
|
8
|
+
const IC_SAR = 0x08; // I2C Slave Address Register
|
|
9
|
+
const IC_DATA_CMD = 0x10; // I2C Rx/Tx Data Buffer and Command Register
|
|
10
|
+
const IC_SS_SCL_HCNT = 0x14; // Standard Speed I2C Clock SCL High Count Register
|
|
11
|
+
const IC_SS_SCL_LCNT = 0x18; // Standard Speed I2C Clock SCL Low Count Register
|
|
12
|
+
const IC_FS_SCL_HCNT = 0x1c; // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
|
|
13
|
+
const IC_FS_SCL_LCNT = 0x20; // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
|
|
14
|
+
const IC_INTR_STAT = 0x2c; // I2C Interrupt Status Register
|
|
15
|
+
const IC_INTR_MASK = 0x30; // I2C Interrupt Mask Register
|
|
16
|
+
const IC_RAW_INTR_STAT = 0x34; // I2C Raw Interrupt Status Register
|
|
17
|
+
const IC_RX_TL = 0x38; // I2C Receive FIFO Threshold Register
|
|
18
|
+
const IC_TX_TL = 0x3c; // I2C Transmit FIFO Threshold Register
|
|
19
|
+
const IC_CLR_INTR = 0x40; // Clear Combined and Individual Interrupt Register
|
|
20
|
+
const IC_CLR_RX_UNDER = 0x44; // Clear RX_UNDER Interrupt Register
|
|
21
|
+
const IC_CLR_RX_OVER = 0x48; // Clear RX_OVER Interrupt Register
|
|
22
|
+
const IC_CLR_TX_OVER = 0x4c; // Clear TX_OVER Interrupt Register
|
|
23
|
+
const IC_CLR_RD_REQ = 0x50; // Clear RD_REQ Interrupt Register
|
|
24
|
+
const IC_CLR_TX_ABRT = 0x54; // Clear TX_ABRT Interrupt Register
|
|
25
|
+
const IC_CLR_RX_DONE = 0x58; // Clear RX_DONE Interrupt Register
|
|
26
|
+
const IC_CLR_ACTIVITY = 0x5c; // Clear ACTIVITY Interrupt Register
|
|
27
|
+
const IC_CLR_STOP_DET = 0x60; // Clear STOP_DET Interrupt Register
|
|
28
|
+
const IC_CLR_START_DET = 0x64; // Clear START_DET Interrupt Register
|
|
29
|
+
const IC_CLR_GEN_CALL = 0x68; // Clear GEN_CALL Interrupt Register
|
|
30
|
+
const IC_ENABLE = 0x6c; // I2C ENABLE Register
|
|
31
|
+
const IC_STATUS = 0x70; // I2C STATUS Register
|
|
32
|
+
const IC_TXFLR = 0x74; // I2C Transmit FIFO Level Register
|
|
33
|
+
const IC_RXFLR = 0x78; // I2C Receive FIFO Level Register
|
|
34
|
+
const IC_SDA_HOLD = 0x7c; // I2C SDA Hold Time Length Register
|
|
35
|
+
const IC_TX_ABRT_SOURCE = 0x80; // I2C Transmit Abort Source Register
|
|
36
|
+
const IC_SLV_DATA_NACK_ONLY = 0x84; // Generate Slave Data NACK Register
|
|
37
|
+
const IC_DMA_CR = 0x88; // DMA Control Register
|
|
38
|
+
const IC_DMA_TDLR = 0x8c; // DMA Transmit Data Level Register
|
|
39
|
+
const IC_DMA_RDLR = 0x90; // DMA Transmit Data Level Register
|
|
40
|
+
const IC_SDA_SETUP = 0x94; // I2C SDA Setup Register
|
|
41
|
+
const IC_ACK_GENERAL_CALL = 0x98; // I2C ACK General Call Register
|
|
42
|
+
const IC_ENABLE_STATUS = 0x9c; // I2C Enable Status Register
|
|
43
|
+
const IC_FS_SPKLEN = 0xa0; // I2C SS, FS or FM+ spike suppression limit
|
|
44
|
+
const IC_CLR_RESTART_DET = 0xa8; // Clear RESTART_DET Interrupt Register
|
|
45
|
+
const IC_COMP_PARAM_1 = 0xf4; // Component Parameter Register 1
|
|
46
|
+
const IC_COMP_VERSION = 0xf8; // I2C Component Version Register
|
|
47
|
+
const IC_COMP_TYPE = 0xfc; // I2C Component Type Register
|
|
48
|
+
// IC_CON bits:
|
|
49
|
+
const STOP_DET_IF_MASTER_ACTIVE = 1 << 10;
|
|
50
|
+
const RX_FIFO_FULL_HLD_CTRL = 1 << 9;
|
|
51
|
+
const TX_EMPTY_CTRL = 1 << 8;
|
|
52
|
+
const STOP_DET_IFADDRESSED = 1 << 7;
|
|
53
|
+
const IC_SLAVE_DISABLE = 1 << 6;
|
|
54
|
+
const IC_RESTART_EN = 1 << 5;
|
|
55
|
+
const IC_10BITADDR_MASTER = 1 << 4;
|
|
56
|
+
const IC_10BITADDR_SLAVE = 1 << 3;
|
|
57
|
+
const SPEED_SHIFT = 1;
|
|
58
|
+
const SPEED_MASK = 0x3;
|
|
59
|
+
const MASTER_MODE = 1 << 0;
|
|
60
|
+
// IC_TAR bits:
|
|
61
|
+
const SPECIAL = 1 << 11;
|
|
62
|
+
const GC_OR_START = 1 << 10;
|
|
63
|
+
// IC_STATUS bits:
|
|
64
|
+
const SLV_ACTIVITY = 1 << 6;
|
|
65
|
+
const MST_ACTIVITY = 1 << 5;
|
|
66
|
+
const RFF = 1 << 4;
|
|
67
|
+
const RFNE = 1 << 3;
|
|
68
|
+
const TFE = 1 << 2;
|
|
69
|
+
const TFNF = 1 << 1;
|
|
70
|
+
const ACTIVITY = 1 << 0;
|
|
71
|
+
// IC_ENABLE bits:
|
|
72
|
+
const TX_CMD_BLOCK = 1 << 2;
|
|
73
|
+
const ABORT = 1 << 1;
|
|
74
|
+
const ENABLE = 1 << 0;
|
|
75
|
+
// IC_TX_ABRT_SOURCE bits:
|
|
76
|
+
const TX_FLUSH_CNT_MASK = 0x1ff;
|
|
77
|
+
const TX_FLUSH_CNT_SHIFT = 23;
|
|
78
|
+
const ABRT_USER_ABRT = 1 << 16;
|
|
79
|
+
const ABRT_SLVRD_INT = 1 << 15;
|
|
80
|
+
const ABRT_SLV_ARBLOST = 1 << 14;
|
|
81
|
+
const ABRT_SLVFLUSH_TXFIFO = 1 << 13;
|
|
82
|
+
const ARB_LOST = 1 << 12;
|
|
83
|
+
const ABRT_MASTER_DIS = 1 << 11;
|
|
84
|
+
const ABRT_10B_RD_NORSTRT = 1 << 10;
|
|
85
|
+
const ABRT_SBYTE_NORSTRT = 1 << 9;
|
|
86
|
+
const ABRT_HS_NORSTRT = 1 << 8;
|
|
87
|
+
const ABRT_SBYTE_ACKDET = 1 << 7;
|
|
88
|
+
const ABRT_HS_ACKDET = 1 << 6;
|
|
89
|
+
const ABRT_GCALL_READ = 1 << 5;
|
|
90
|
+
const ABRT_GCALL_NOACK = 1 << 4;
|
|
91
|
+
const ABRT_TXDATA_NOACK = 1 << 3;
|
|
92
|
+
const ABRT_10ADDR2_NOACK = 1 << 2;
|
|
93
|
+
const ABRT_10ADDR1_NOACK = 1 << 1;
|
|
94
|
+
const ABRT_7B_ADDR_NOACK = 1 << 0;
|
|
95
|
+
/* Connection parameters */
|
|
96
|
+
var I2CMode;
|
|
97
|
+
(function (I2CMode) {
|
|
98
|
+
I2CMode[I2CMode["Write"] = 0] = "Write";
|
|
99
|
+
I2CMode[I2CMode["Read"] = 1] = "Read";
|
|
100
|
+
})(I2CMode || (exports.I2CMode = I2CMode = {}));
|
|
101
|
+
var I2CSpeed;
|
|
102
|
+
(function (I2CSpeed) {
|
|
103
|
+
I2CSpeed[I2CSpeed["Invalid"] = 0] = "Invalid";
|
|
104
|
+
/* standard mode (100 kbit/s) */
|
|
105
|
+
I2CSpeed[I2CSpeed["Standard"] = 1] = "Standard";
|
|
106
|
+
/* fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) */
|
|
107
|
+
I2CSpeed[I2CSpeed["FastMode"] = 2] = "FastMode";
|
|
108
|
+
/* high speed mode (3.4 Mbit/s) */
|
|
109
|
+
I2CSpeed[I2CSpeed["HighSpeedMode"] = 3] = "HighSpeedMode";
|
|
110
|
+
})(I2CSpeed || (exports.I2CSpeed = I2CSpeed = {}));
|
|
111
|
+
var I2CState;
|
|
112
|
+
(function (I2CState) {
|
|
113
|
+
I2CState[I2CState["Idle"] = 0] = "Idle";
|
|
114
|
+
I2CState[I2CState["Start"] = 1] = "Start";
|
|
115
|
+
I2CState[I2CState["Connect"] = 2] = "Connect";
|
|
116
|
+
I2CState[I2CState["Connected"] = 3] = "Connected";
|
|
117
|
+
I2CState[I2CState["Stop"] = 4] = "Stop";
|
|
118
|
+
})(I2CState || (I2CState = {}));
|
|
119
|
+
// Interrupts
|
|
120
|
+
const R_RESTART_DET = 1 << 12; // Slave mode only
|
|
121
|
+
const R_GEN_CALL = 1 << 11;
|
|
122
|
+
const R_START_DET = 1 << 10;
|
|
123
|
+
const R_STOP_DET = 1 << 9;
|
|
124
|
+
const R_ACTIVITY = 1 << 8;
|
|
125
|
+
const R_RX_DONE = 1 << 7;
|
|
126
|
+
const R_TX_ABRT = 1 << 6;
|
|
127
|
+
const R_RD_REQ = 1 << 5;
|
|
128
|
+
const R_TX_EMPTY = 1 << 4;
|
|
129
|
+
const R_TX_OVER = 1 << 3;
|
|
130
|
+
const R_RX_FULL = 1 << 2;
|
|
131
|
+
const R_RX_OVER = 1 << 1;
|
|
132
|
+
const R_RX_UNDER = 1 << 0;
|
|
133
|
+
// FIFO entry bits
|
|
134
|
+
const FIRST_DATA_BYTE = 1 << 10;
|
|
135
|
+
const RESTART = 1 << 10;
|
|
136
|
+
const STOP = 1 << 9;
|
|
137
|
+
const CMD = 1 << 8; // 0 for write, 1 for read
|
|
138
|
+
class RPI2C extends peripheral_js_1.BasePeripheral {
|
|
139
|
+
get intStatus() {
|
|
140
|
+
return this.intRaw & this.intEnable;
|
|
141
|
+
}
|
|
142
|
+
get speed() {
|
|
143
|
+
return ((this.control >> SPEED_SHIFT) & SPEED_MASK);
|
|
144
|
+
}
|
|
145
|
+
get masterBits() {
|
|
146
|
+
return this.control & IC_10BITADDR_MASTER ? 10 : 7;
|
|
147
|
+
}
|
|
148
|
+
constructor(rp2040, name, irq) {
|
|
149
|
+
super(rp2040, name);
|
|
150
|
+
this.irq = irq;
|
|
151
|
+
this.state = I2CState.Idle;
|
|
152
|
+
this.busy = false;
|
|
153
|
+
this.stop = false;
|
|
154
|
+
this.pendingRestart = false;
|
|
155
|
+
this.firstByte = false;
|
|
156
|
+
this.rxFIFO = new fifo_js_1.FIFO(16);
|
|
157
|
+
this.txFIFO = new fifo_js_1.FIFO(16);
|
|
158
|
+
// user provided callbacks
|
|
159
|
+
this.onStart = () => this.completeStart();
|
|
160
|
+
this.onConnect = () => this.completeConnect(false);
|
|
161
|
+
this.onWriteByte = () => this.completeWrite(false);
|
|
162
|
+
this.onReadByte = () => this.completeRead(0xff);
|
|
163
|
+
this.onStop = () => this.completeStop();
|
|
164
|
+
this.enable = 0;
|
|
165
|
+
this.rxThreshold = 0;
|
|
166
|
+
this.txThreshold = 0;
|
|
167
|
+
this.control = IC_SLAVE_DISABLE | IC_RESTART_EN | (I2CSpeed.FastMode << SPEED_SHIFT) | MASTER_MODE;
|
|
168
|
+
this.targetAddress = 0x55;
|
|
169
|
+
this.slaveAddress = 0x55;
|
|
170
|
+
this.abortSource = 0;
|
|
171
|
+
this.intRaw = 0;
|
|
172
|
+
this.intEnable = 0;
|
|
173
|
+
}
|
|
174
|
+
checkInterrupts() {
|
|
175
|
+
this.rp2040.setInterrupt(this.irq, !!this.intStatus);
|
|
176
|
+
}
|
|
177
|
+
clearInterrupts(mask) {
|
|
178
|
+
if (this.intRaw & mask) {
|
|
179
|
+
this.intRaw &= ~mask;
|
|
180
|
+
this.checkInterrupts();
|
|
181
|
+
return 1;
|
|
182
|
+
}
|
|
183
|
+
else {
|
|
184
|
+
return 0;
|
|
185
|
+
}
|
|
186
|
+
}
|
|
187
|
+
setInterrupts(mask) {
|
|
188
|
+
if (!(this.intRaw & mask)) {
|
|
189
|
+
this.intRaw |= mask;
|
|
190
|
+
this.checkInterrupts();
|
|
191
|
+
}
|
|
192
|
+
}
|
|
193
|
+
abort(reason) {
|
|
194
|
+
this.abortSource &= ~TX_FLUSH_CNT_MASK;
|
|
195
|
+
this.abortSource |= reason | (this.txFIFO.itemCount << TX_FLUSH_CNT_SHIFT);
|
|
196
|
+
this.txFIFO.reset();
|
|
197
|
+
this.setInterrupts(R_TX_ABRT);
|
|
198
|
+
}
|
|
199
|
+
nextCommand() {
|
|
200
|
+
const enabled = this.enable & ENABLE;
|
|
201
|
+
const blocked = this.enable & TX_CMD_BLOCK;
|
|
202
|
+
if (this.txFIFO.empty || this.busy || blocked || !enabled) {
|
|
203
|
+
return;
|
|
204
|
+
}
|
|
205
|
+
this.busy = true;
|
|
206
|
+
const restart = !!(this.txFIFO.peek() & RESTART) && !this.pendingRestart && !this.stop;
|
|
207
|
+
if (this.state === I2CState.Idle || restart) {
|
|
208
|
+
this.pendingRestart = restart;
|
|
209
|
+
this.stop = false;
|
|
210
|
+
this.state = I2CState.Start;
|
|
211
|
+
this.onStart(restart);
|
|
212
|
+
return;
|
|
213
|
+
}
|
|
214
|
+
this.pendingRestart = false;
|
|
215
|
+
const cmd = this.txFIFO.pull();
|
|
216
|
+
const readMode = !!(cmd & CMD);
|
|
217
|
+
this.stop = !!(cmd & STOP);
|
|
218
|
+
if (readMode) {
|
|
219
|
+
this.onReadByte(!this.stop);
|
|
220
|
+
}
|
|
221
|
+
else {
|
|
222
|
+
this.onWriteByte(cmd & 0xff);
|
|
223
|
+
}
|
|
224
|
+
if (this.txFIFO.itemCount <= this.txThreshold) {
|
|
225
|
+
this.setInterrupts(R_TX_EMPTY);
|
|
226
|
+
}
|
|
227
|
+
}
|
|
228
|
+
pushRX(value) {
|
|
229
|
+
if (this.rxFIFO.full) {
|
|
230
|
+
this.setInterrupts(R_RX_OVER);
|
|
231
|
+
return;
|
|
232
|
+
}
|
|
233
|
+
this.rxFIFO.push(value);
|
|
234
|
+
if (this.rxFIFO.itemCount > this.rxThreshold) {
|
|
235
|
+
this.setInterrupts(R_RX_FULL);
|
|
236
|
+
}
|
|
237
|
+
}
|
|
238
|
+
completeStart() {
|
|
239
|
+
if (this.txFIFO.empty || this.state !== I2CState.Start || this.stop) {
|
|
240
|
+
this.onStop();
|
|
241
|
+
return;
|
|
242
|
+
}
|
|
243
|
+
const mode = this.txFIFO.peek() & CMD ? I2CMode.Read : I2CMode.Write;
|
|
244
|
+
this.state = I2CState.Connect;
|
|
245
|
+
this.setInterrupts(R_START_DET);
|
|
246
|
+
const addressMask = this.masterBits === 10 ? 0x3ff : 0xff;
|
|
247
|
+
this.onConnect(this.targetAddress & addressMask, mode);
|
|
248
|
+
}
|
|
249
|
+
completeConnect(ack, nackByte = 0) {
|
|
250
|
+
if (!ack || this.stop) {
|
|
251
|
+
if (!ack) {
|
|
252
|
+
if (!this.targetAddress) {
|
|
253
|
+
this.abort(ABRT_GCALL_NOACK);
|
|
254
|
+
}
|
|
255
|
+
else if (this.control & IC_10BITADDR_MASTER) {
|
|
256
|
+
this.abort(nackByte === 0 ? ABRT_10ADDR1_NOACK : ABRT_10ADDR2_NOACK);
|
|
257
|
+
}
|
|
258
|
+
else {
|
|
259
|
+
this.abort(ABRT_7B_ADDR_NOACK);
|
|
260
|
+
}
|
|
261
|
+
}
|
|
262
|
+
this.state = I2CState.Stop;
|
|
263
|
+
this.onStop();
|
|
264
|
+
return;
|
|
265
|
+
}
|
|
266
|
+
this.state = I2CState.Connected;
|
|
267
|
+
this.busy = false;
|
|
268
|
+
this.firstByte = true;
|
|
269
|
+
this.nextCommand();
|
|
270
|
+
}
|
|
271
|
+
completeWrite(ack) {
|
|
272
|
+
if (!ack || this.stop) {
|
|
273
|
+
if (!ack) {
|
|
274
|
+
this.abort(ABRT_TXDATA_NOACK);
|
|
275
|
+
}
|
|
276
|
+
this.state = I2CState.Stop;
|
|
277
|
+
this.onStop();
|
|
278
|
+
return;
|
|
279
|
+
}
|
|
280
|
+
this.busy = false;
|
|
281
|
+
this.nextCommand();
|
|
282
|
+
}
|
|
283
|
+
completeRead(value) {
|
|
284
|
+
this.pushRX(value | (this.firstByte ? FIRST_DATA_BYTE : 0));
|
|
285
|
+
if (this.stop) {
|
|
286
|
+
this.state = I2CState.Stop;
|
|
287
|
+
this.onStop();
|
|
288
|
+
return;
|
|
289
|
+
}
|
|
290
|
+
this.firstByte = false;
|
|
291
|
+
this.busy = false;
|
|
292
|
+
this.nextCommand();
|
|
293
|
+
}
|
|
294
|
+
completeStop() {
|
|
295
|
+
this.state = I2CState.Idle;
|
|
296
|
+
this.setInterrupts(R_STOP_DET);
|
|
297
|
+
this.busy = false;
|
|
298
|
+
this.pendingRestart = false;
|
|
299
|
+
if (this.enable & ABORT) {
|
|
300
|
+
this.enable &= ~ABORT;
|
|
301
|
+
}
|
|
302
|
+
else {
|
|
303
|
+
this.nextCommand();
|
|
304
|
+
}
|
|
305
|
+
}
|
|
306
|
+
arbitrationLost() {
|
|
307
|
+
this.state = I2CState.Idle;
|
|
308
|
+
this.busy = false;
|
|
309
|
+
this.abort(ARB_LOST);
|
|
310
|
+
}
|
|
311
|
+
readUint32(offset) {
|
|
312
|
+
switch (offset) {
|
|
313
|
+
case IC_CON:
|
|
314
|
+
return this.control;
|
|
315
|
+
case IC_TAR:
|
|
316
|
+
return this.targetAddress;
|
|
317
|
+
case IC_SAR:
|
|
318
|
+
return this.slaveAddress;
|
|
319
|
+
case IC_DATA_CMD:
|
|
320
|
+
if (this.rxFIFO.empty) {
|
|
321
|
+
this.setInterrupts(R_RX_UNDER);
|
|
322
|
+
return 0;
|
|
323
|
+
}
|
|
324
|
+
this.clearInterrupts(R_RX_FULL);
|
|
325
|
+
return this.rxFIFO.pull();
|
|
326
|
+
case IC_INTR_STAT:
|
|
327
|
+
return this.intStatus;
|
|
328
|
+
case IC_INTR_MASK:
|
|
329
|
+
return this.intEnable;
|
|
330
|
+
case IC_RAW_INTR_STAT:
|
|
331
|
+
return this.intRaw;
|
|
332
|
+
case IC_RX_TL:
|
|
333
|
+
return this.rxThreshold;
|
|
334
|
+
case IC_TX_TL:
|
|
335
|
+
return this.txThreshold;
|
|
336
|
+
case IC_CLR_INTR:
|
|
337
|
+
this.abortSource &= ABRT_SBYTE_NORSTRT; // Clear IC_TX_ABRT_SOURCE, expect for bit 9
|
|
338
|
+
return this.clearInterrupts(R_RX_UNDER |
|
|
339
|
+
R_RX_OVER |
|
|
340
|
+
R_TX_OVER |
|
|
341
|
+
R_RD_REQ |
|
|
342
|
+
R_TX_ABRT |
|
|
343
|
+
R_RX_DONE |
|
|
344
|
+
R_ACTIVITY |
|
|
345
|
+
R_STOP_DET |
|
|
346
|
+
R_START_DET |
|
|
347
|
+
R_GEN_CALL);
|
|
348
|
+
case IC_CLR_RX_UNDER:
|
|
349
|
+
return this.clearInterrupts(R_RX_UNDER);
|
|
350
|
+
case IC_CLR_RX_OVER:
|
|
351
|
+
return this.clearInterrupts(R_RX_OVER);
|
|
352
|
+
case IC_CLR_TX_OVER:
|
|
353
|
+
return this.clearInterrupts(R_TX_OVER);
|
|
354
|
+
case IC_CLR_RD_REQ:
|
|
355
|
+
return this.clearInterrupts(R_RD_REQ);
|
|
356
|
+
case IC_CLR_TX_ABRT:
|
|
357
|
+
this.abortSource &= ABRT_SBYTE_NORSTRT; // Clear IC_TX_ABRT_SOURCE, expect for bit 9
|
|
358
|
+
return this.clearInterrupts(R_TX_ABRT);
|
|
359
|
+
case IC_CLR_RX_DONE:
|
|
360
|
+
return this.clearInterrupts(R_RX_DONE);
|
|
361
|
+
case IC_CLR_ACTIVITY:
|
|
362
|
+
return this.clearInterrupts(R_ACTIVITY);
|
|
363
|
+
case IC_CLR_STOP_DET:
|
|
364
|
+
return this.clearInterrupts(R_STOP_DET);
|
|
365
|
+
case IC_CLR_START_DET:
|
|
366
|
+
return this.clearInterrupts(R_START_DET);
|
|
367
|
+
case IC_CLR_GEN_CALL:
|
|
368
|
+
return this.clearInterrupts(R_GEN_CALL);
|
|
369
|
+
case IC_ENABLE:
|
|
370
|
+
return this.enable;
|
|
371
|
+
case IC_STATUS:
|
|
372
|
+
return ((this.state !== I2CState.Idle ? MST_ACTIVITY | ACTIVITY : 0) |
|
|
373
|
+
(this.rxFIFO.full ? RFF : 0) |
|
|
374
|
+
(!this.rxFIFO.empty ? RFNE : 0) |
|
|
375
|
+
(this.txFIFO.empty ? TFE : 0) |
|
|
376
|
+
(!this.txFIFO.full ? TFNF : 0));
|
|
377
|
+
case IC_TXFLR:
|
|
378
|
+
return this.txFIFO.itemCount;
|
|
379
|
+
case IC_RXFLR:
|
|
380
|
+
return this.rxFIFO.itemCount;
|
|
381
|
+
case IC_TX_ABRT_SOURCE: {
|
|
382
|
+
const value = this.abortSource;
|
|
383
|
+
this.abortSource &= ABRT_SBYTE_NORSTRT; // Clear IC_TX_ABRT_SOURCE, expect for bit 9
|
|
384
|
+
return value;
|
|
385
|
+
}
|
|
386
|
+
case IC_COMP_PARAM_1:
|
|
387
|
+
// From the datasheet:
|
|
388
|
+
// Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only
|
|
389
|
+
// register that contains encoded information about the component's parameter settings.
|
|
390
|
+
return 0;
|
|
391
|
+
case IC_COMP_VERSION:
|
|
392
|
+
return 0x3230312a;
|
|
393
|
+
case IC_COMP_TYPE:
|
|
394
|
+
return 0x44570140;
|
|
395
|
+
}
|
|
396
|
+
return super.readUint32(offset);
|
|
397
|
+
}
|
|
398
|
+
writeUint32(offset, value) {
|
|
399
|
+
switch (offset) {
|
|
400
|
+
case IC_CON:
|
|
401
|
+
if (((value >> SPEED_SHIFT) & SPEED_MASK) === I2CSpeed.Invalid) {
|
|
402
|
+
value = (value & ~(SPEED_MASK << SPEED_SHIFT)) | (I2CSpeed.HighSpeedMode << SPEED_SHIFT);
|
|
403
|
+
}
|
|
404
|
+
this.control = value;
|
|
405
|
+
return;
|
|
406
|
+
case IC_TAR:
|
|
407
|
+
this.targetAddress = value & 0x3ff;
|
|
408
|
+
return;
|
|
409
|
+
case IC_SAR:
|
|
410
|
+
this.slaveAddress = value & 0x3ff;
|
|
411
|
+
return;
|
|
412
|
+
case IC_DATA_CMD:
|
|
413
|
+
if (this.txFIFO.full) {
|
|
414
|
+
this.setInterrupts(R_TX_OVER);
|
|
415
|
+
}
|
|
416
|
+
else {
|
|
417
|
+
this.txFIFO.push(value);
|
|
418
|
+
this.clearInterrupts(R_TX_EMPTY);
|
|
419
|
+
this.nextCommand();
|
|
420
|
+
}
|
|
421
|
+
return;
|
|
422
|
+
case IC_RX_TL:
|
|
423
|
+
this.rxThreshold = value & 0xff;
|
|
424
|
+
if (this.rxThreshold > this.rxFIFO.size) {
|
|
425
|
+
this.rxThreshold = this.rxFIFO.size;
|
|
426
|
+
}
|
|
427
|
+
return;
|
|
428
|
+
case IC_TX_TL:
|
|
429
|
+
this.txThreshold = value & 0xff;
|
|
430
|
+
if (this.txThreshold > this.txFIFO.size) {
|
|
431
|
+
this.txThreshold = this.txFIFO.size;
|
|
432
|
+
}
|
|
433
|
+
return;
|
|
434
|
+
case IC_ENABLE:
|
|
435
|
+
// ABORT bit can only be set by software, not cleared.
|
|
436
|
+
value |= this.enable & ABORT;
|
|
437
|
+
if (value & ABORT) {
|
|
438
|
+
if (this.state === I2CState.Idle) {
|
|
439
|
+
value &= ~ABORT;
|
|
440
|
+
}
|
|
441
|
+
else {
|
|
442
|
+
this.abort(ABRT_USER_ABRT);
|
|
443
|
+
this.stop = true;
|
|
444
|
+
}
|
|
445
|
+
}
|
|
446
|
+
if (!(value & ENABLE)) {
|
|
447
|
+
this.txFIFO.reset();
|
|
448
|
+
this.rxFIFO.reset();
|
|
449
|
+
}
|
|
450
|
+
this.enable = value;
|
|
451
|
+
this.nextCommand(); // TX_CMD_BLOCK may have changed
|
|
452
|
+
return;
|
|
453
|
+
default:
|
|
454
|
+
super.writeUint32(offset, value);
|
|
455
|
+
}
|
|
456
|
+
}
|
|
457
|
+
}
|
|
458
|
+
exports.RPI2C = RPI2C;
|