rp2040js 0.17.17 → 0.18.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/cjs/clock/clock.d.ts +11 -11
- package/dist/cjs/clock/clock.js +2 -2
- package/dist/cjs/clock/mock-clock.d.ts +17 -17
- package/dist/cjs/clock/mock-clock.js +52 -52
- package/dist/cjs/clock/realtime-clock.d.ts +23 -23
- package/dist/cjs/clock/realtime-clock.js +73 -73
- package/dist/cjs/cortex-m0-core.d.ts +87 -87
- package/dist/cjs/cortex-m0-core.js +1251 -1251
- package/dist/cjs/gdb/gdb-connection.d.ts +11 -11
- package/dist/cjs/gdb/gdb-connection.js +57 -57
- package/dist/cjs/gdb/gdb-server.d.ts +23 -23
- package/dist/cjs/gdb/gdb-server.js +232 -232
- package/dist/cjs/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/cjs/gdb/gdb-tcp-server.js +34 -34
- package/dist/cjs/gdb/gdb-utils.d.ts +9 -9
- package/dist/cjs/gdb/gdb-utils.js +48 -48
- package/dist/cjs/gpio-pin.d.ts +56 -56
- package/dist/cjs/gpio-pin.js +216 -216
- package/dist/cjs/index.d.ts +11 -11
- package/dist/cjs/index.js +36 -36
- package/dist/cjs/interpolator.d.ts +36 -36
- package/dist/cjs/interpolator.js +150 -150
- package/dist/cjs/irq.d.ts +29 -29
- package/dist/cjs/irq.js +33 -33
- package/dist/cjs/peripherals/adc.d.ts +52 -52
- package/dist/cjs/peripherals/adc.js +261 -261
- package/dist/cjs/peripherals/busctrl.d.ts +10 -10
- package/dist/cjs/peripherals/busctrl.js +84 -84
- package/dist/cjs/peripherals/clocks.d.ts +9 -9
- package/dist/cjs/peripherals/clocks.js +42 -42
- package/dist/cjs/peripherals/dma.d.ts +109 -109
- package/dist/cjs/peripherals/dma.js +520 -520
- package/dist/cjs/peripherals/i2c.d.ts +54 -54
- package/dist/cjs/peripherals/i2c.js +458 -458
- package/dist/cjs/peripherals/io.d.ts +11 -11
- package/dist/cjs/peripherals/io.js +100 -100
- package/dist/cjs/peripherals/pads.d.ts +13 -13
- package/dist/cjs/peripherals/pads.js +58 -58
- package/dist/cjs/peripherals/peripheral.d.ts +22 -22
- package/dist/cjs/peripherals/peripheral.js +61 -61
- package/dist/cjs/peripherals/pio.d.ts +120 -120
- package/dist/cjs/peripherals/pio.js +1086 -1086
- package/dist/cjs/peripherals/ppb.d.ts +25 -25
- package/dist/cjs/peripherals/ppb.js +229 -229
- package/dist/cjs/peripherals/pwm.d.ts +65 -65
- package/dist/cjs/peripherals/pwm.js +372 -372
- package/dist/cjs/peripherals/reset.d.ts +8 -8
- package/dist/cjs/peripherals/reset.js +40 -40
- package/dist/cjs/peripherals/rtc.d.ts +10 -10
- package/dist/cjs/peripherals/rtc.js +74 -74
- package/dist/cjs/peripherals/spi.d.ts +38 -38
- package/dist/cjs/peripherals/spi.js +240 -240
- package/dist/cjs/peripherals/ssi.d.ts +6 -6
- package/dist/cjs/peripherals/ssi.js +43 -43
- package/dist/cjs/peripherals/syscfg.d.ts +5 -5
- package/dist/cjs/peripherals/syscfg.js +26 -26
- package/dist/cjs/peripherals/sysinfo.d.ts +4 -4
- package/dist/cjs/peripherals/sysinfo.js +22 -22
- package/dist/cjs/peripherals/tbman.d.ts +4 -4
- package/dist/cjs/peripherals/tbman.js +17 -17
- package/dist/cjs/peripherals/timer.d.ts +18 -18
- package/dist/cjs/peripherals/timer.js +156 -156
- package/dist/cjs/peripherals/uart.d.ts +31 -31
- package/dist/cjs/peripherals/uart.js +132 -132
- package/dist/cjs/peripherals/usb.d.ts +29 -29
- package/dist/cjs/peripherals/usb.js +309 -309
- package/dist/cjs/rp2040.d.ts +71 -71
- package/dist/cjs/rp2040.js +361 -361
- package/dist/cjs/sio.d.ts +21 -21
- package/dist/cjs/sio.js +425 -425
- package/dist/cjs/usb/cdc.d.ts +20 -20
- package/dist/cjs/usb/cdc.js +126 -126
- package/dist/cjs/usb/interfaces.d.ts +47 -47
- package/dist/cjs/usb/interfaces.js +46 -46
- package/dist/cjs/usb/setup.d.ts +5 -5
- package/dist/cjs/usb/setup.js +53 -53
- package/dist/cjs/utils/assembler.d.ts +79 -79
- package/dist/cjs/utils/assembler.js +328 -328
- package/dist/cjs/utils/bit.d.ts +3 -3
- package/dist/cjs/utils/bit.js +15 -15
- package/dist/cjs/utils/fifo.d.ts +15 -15
- package/dist/cjs/utils/fifo.js +56 -56
- package/dist/cjs/utils/logging.d.ts +23 -23
- package/dist/cjs/utils/logging.js +48 -48
- package/dist/cjs/utils/pio-assembler.d.ts +45 -45
- package/dist/cjs/utils/pio-assembler.js +87 -87
- package/dist/cjs/utils/time.d.ts +2 -2
- package/dist/cjs/utils/time.js +32 -32
- package/dist/cjs/utils/timer32.d.ts +57 -57
- package/dist/cjs/utils/timer32.js +208 -208
- package/dist/esm/clock/clock.d.ts +11 -11
- package/dist/esm/clock/clock.js +1 -1
- package/dist/esm/clock/mock-clock.d.ts +17 -17
- package/dist/esm/clock/mock-clock.js +47 -47
- package/dist/esm/clock/realtime-clock.d.ts +23 -23
- package/dist/esm/clock/realtime-clock.js +68 -68
- package/dist/esm/cortex-m0-core.d.ts +87 -87
- package/dist/esm/cortex-m0-core.js +1247 -1247
- package/dist/esm/gdb/gdb-connection.d.ts +11 -11
- package/dist/esm/gdb/gdb-connection.js +53 -53
- package/dist/esm/gdb/gdb-server.d.ts +23 -23
- package/dist/esm/gdb/gdb-server.js +228 -228
- package/dist/esm/gdb/gdb-tcp-server.d.ts +10 -10
- package/dist/esm/gdb/gdb-tcp-server.js +30 -30
- package/dist/esm/gdb/gdb-utils.d.ts +9 -9
- package/dist/esm/gdb/gdb-utils.js +36 -36
- package/dist/esm/gpio-pin.d.ts +56 -56
- package/dist/esm/gpio-pin.js +212 -212
- package/dist/esm/index.d.ts +11 -11
- package/dist/esm/index.js +11 -11
- package/dist/esm/interpolator.d.ts +36 -36
- package/dist/esm/interpolator.js +145 -145
- package/dist/esm/irq.d.ts +29 -29
- package/dist/esm/irq.js +30 -30
- package/dist/esm/peripherals/adc.d.ts +52 -52
- package/dist/esm/peripherals/adc.js +257 -257
- package/dist/esm/peripherals/busctrl.d.ts +10 -10
- package/dist/esm/peripherals/busctrl.js +80 -80
- package/dist/esm/peripherals/clocks.d.ts +9 -9
- package/dist/esm/peripherals/clocks.js +38 -38
- package/dist/esm/peripherals/dma.d.ts +109 -109
- package/dist/esm/peripherals/dma.js +515 -515
- package/dist/esm/peripherals/i2c.d.ts +54 -54
- package/dist/esm/peripherals/i2c.js +454 -454
- package/dist/esm/peripherals/io.d.ts +11 -11
- package/dist/esm/peripherals/io.js +96 -96
- package/dist/esm/peripherals/pads.d.ts +13 -13
- package/dist/esm/peripherals/pads.js +54 -54
- package/dist/esm/peripherals/peripheral.d.ts +22 -22
- package/dist/esm/peripherals/peripheral.js +55 -55
- package/dist/esm/peripherals/pio.d.ts +120 -120
- package/dist/esm/peripherals/pio.js +1081 -1081
- package/dist/esm/peripherals/ppb.d.ts +25 -25
- package/dist/esm/peripherals/ppb.js +225 -225
- package/dist/esm/peripherals/pwm.d.ts +65 -65
- package/dist/esm/peripherals/pwm.js +368 -368
- package/dist/esm/peripherals/reset.d.ts +8 -8
- package/dist/esm/peripherals/reset.js +36 -36
- package/dist/esm/peripherals/rtc.d.ts +10 -10
- package/dist/esm/peripherals/rtc.js +70 -70
- package/dist/esm/peripherals/spi.d.ts +38 -38
- package/dist/esm/peripherals/spi.js +236 -236
- package/dist/esm/peripherals/ssi.d.ts +6 -6
- package/dist/esm/peripherals/ssi.js +39 -39
- package/dist/esm/peripherals/syscfg.d.ts +5 -5
- package/dist/esm/peripherals/syscfg.js +22 -22
- package/dist/esm/peripherals/sysinfo.d.ts +4 -4
- package/dist/esm/peripherals/sysinfo.js +18 -18
- package/dist/esm/peripherals/tbman.d.ts +4 -4
- package/dist/esm/peripherals/tbman.js +13 -13
- package/dist/esm/peripherals/timer.d.ts +18 -18
- package/dist/esm/peripherals/timer.js +152 -152
- package/dist/esm/peripherals/uart.d.ts +31 -31
- package/dist/esm/peripherals/uart.js +128 -128
- package/dist/esm/peripherals/usb.d.ts +29 -29
- package/dist/esm/peripherals/usb.js +305 -305
- package/dist/esm/rp2040.d.ts +71 -71
- package/dist/esm/rp2040.js +357 -357
- package/dist/esm/sio.d.ts +21 -21
- package/dist/esm/sio.js +421 -421
- package/dist/esm/usb/cdc.d.ts +20 -20
- package/dist/esm/usb/cdc.js +121 -121
- package/dist/esm/usb/interfaces.d.ts +47 -47
- package/dist/esm/usb/interfaces.js +43 -43
- package/dist/esm/usb/setup.d.ts +5 -5
- package/dist/esm/usb/setup.js +46 -46
- package/dist/esm/utils/assembler.d.ts +79 -79
- package/dist/esm/utils/assembler.js +245 -245
- package/dist/esm/utils/bit.d.ts +3 -3
- package/dist/esm/utils/bit.js +9 -9
- package/dist/esm/utils/fifo.d.ts +15 -15
- package/dist/esm/utils/fifo.js +52 -52
- package/dist/esm/utils/logging.d.ts +23 -23
- package/dist/esm/utils/logging.js +44 -44
- package/dist/esm/utils/pio-assembler.d.ts +45 -45
- package/dist/esm/utils/pio-assembler.js +75 -75
- package/dist/esm/utils/time.d.ts +2 -2
- package/dist/esm/utils/time.js +27 -27
- package/dist/esm/utils/timer32.d.ts +57 -57
- package/dist/esm/utils/timer32.js +203 -203
- package/package.json +38 -27
- package/dist/esm/package.json +0 -1
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import { RP2040 } from '../rp2040';
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import { Timer32, Timer32PeriodicAlarm } from '../utils/timer32';
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import { BasePeripheral, Peripheral } from './peripheral';
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export declare const CPUID = 3328;
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export declare const ICSR = 3332;
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export declare const VTOR = 3336;
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export declare const SHPR2 = 3356;
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export declare const SHPR3 = 3360;
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/** PPB stands for Private Periphral Bus.
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* These are peripherals that are part of the ARM Cortex Core, and there's one copy for each processor core.
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*
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* Included peripheral: NVIC, SysTick timer
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*/
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export declare class RPPPB extends BasePeripheral implements Peripheral {
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systickCountFlag: boolean;
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systickClkSource: boolean;
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systickIntEnable: boolean;
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systickReload: number;
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readonly systickTimer: Timer32;
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readonly systickAlarm: Timer32PeriodicAlarm;
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constructor(rp2040: RP2040, name: string);
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reset(): void;
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readUint32(offset: number): number;
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writeUint32(offset: number, value: number): void;
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}
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import { RP2040 } from '../rp2040.js';
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import { Timer32, Timer32PeriodicAlarm } from '../utils/timer32.js';
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import { BasePeripheral, Peripheral } from './peripheral.js';
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export declare const CPUID = 3328;
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export declare const ICSR = 3332;
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export declare const VTOR = 3336;
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export declare const SHPR2 = 3356;
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export declare const SHPR3 = 3360;
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/** PPB stands for Private Periphral Bus.
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* These are peripherals that are part of the ARM Cortex Core, and there's one copy for each processor core.
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*
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* Included peripheral: NVIC, SysTick timer
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*/
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export declare class RPPPB extends BasePeripheral implements Peripheral {
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systickCountFlag: boolean;
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systickClkSource: boolean;
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systickIntEnable: boolean;
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systickReload: number;
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readonly systickTimer: Timer32;
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readonly systickAlarm: Timer32PeriodicAlarm;
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constructor(rp2040: RP2040, name: string);
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reset(): void;
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readUint32(offset: number): number;
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writeUint32(offset: number, value: number): void;
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}
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"use strict";
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Object.defineProperty(exports, "__esModule", { value: true });
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exports.RPPPB = exports.SHPR3 = exports.SHPR2 = exports.VTOR = exports.ICSR = exports.CPUID = void 0;
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const
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const
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const
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exports.CPUID = 0xd00;
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exports.ICSR = 0xd04;
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exports.VTOR = 0xd08;
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exports.SHPR2 = 0xd1c;
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exports.SHPR3 = 0xd20;
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const SYST_CSR = 0x010; // SysTick Control and Status Register
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const SYST_RVR = 0x014; // SysTick Reload Value Register
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const SYST_CVR = 0x018; // SysTick Current Value Register
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const SYST_CALIB = 0x01c; // SysTick Calibration Value Register
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const NVIC_ISER = 0x100; // Interrupt Set-Enable Register
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const NVIC_ICER = 0x180; // Interrupt Clear-Enable Register
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const NVIC_ISPR = 0x200; // Interrupt Set-Pending Register
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const NVIC_ICPR = 0x280; // Interrupt Clear-Pending Register
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// Interrupt priority registers:
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const NVIC_IPR0 = 0x400;
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const NVIC_IPR1 = 0x404;
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const NVIC_IPR2 = 0x408;
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const NVIC_IPR3 = 0x40c;
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const NVIC_IPR4 = 0x410;
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const NVIC_IPR5 = 0x414;
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const NVIC_IPR6 = 0x418;
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const NVIC_IPR7 = 0x41c;
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/** ICSR Bits */
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const NMIPENDSET = 1 << 31;
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const PENDSVSET = 1 << 28;
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const PENDSVCLR = 1 << 27;
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const PENDSTSET = 1 << 26;
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const PENDSTCLR = 1 << 25;
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const ISRPREEMPT = 1 << 23;
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const ISRPENDING = 1 << 22;
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const VECTPENDING_MASK = 0x1ff;
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const VECTPENDING_SHIFT = 12;
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const VECTACTIVE_MASK = 0x1ff;
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const VECTACTIVE_SHIFT = 0;
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/** PPB stands for Private Periphral Bus.
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* These are peripherals that are part of the ARM Cortex Core, and there's one copy for each processor core.
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*
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* Included peripheral: NVIC, SysTick timer
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*/
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class RPPPB extends
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constructor(rp2040, name) {
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super(rp2040, name);
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// Systick
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this.systickCountFlag = false;
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this.systickClkSource = false;
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this.systickIntEnable = false;
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this.systickReload = 0;
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this.systickTimer = new
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this.systickAlarm = new
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this.systickCountFlag = true;
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if (this.systickIntEnable) {
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this.rp2040.core.pendingSystick = true;
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this.rp2040.core.interruptsUpdated = true;
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}
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this.systickTimer.set(this.systickReload);
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});
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this.systickTimer.top = 0xffffff;
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this.systickTimer.mode =
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this.systickAlarm.target = 0;
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this.systickAlarm.enable = true;
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this.reset();
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}
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reset() {
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this.writeUint32(SYST_CSR, 0);
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this.writeUint32(SYST_RVR, 0xffffff);
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this.systickTimer.set(0xffffff);
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}
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readUint32(offset) {
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const { rp2040 } = this;
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const { core } = rp2040;
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switch (offset) {
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case exports.CPUID:
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return 0x410cc601; /* Verified against actual hardware */
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case exports.ICSR: {
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const pendingInterrupts = core.pendingInterrupts || core.pendingPendSV || core.pendingSystick || core.pendingSVCall;
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const vectPending = core.vectPending;
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return ((core.pendingNMI ? NMIPENDSET : 0) |
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(core.pendingPendSV ? PENDSVSET : 0) |
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(core.pendingSystick ? PENDSTSET : 0) |
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(pendingInterrupts ? ISRPENDING : 0) |
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(vectPending << VECTPENDING_SHIFT) |
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((core.IPSR & VECTACTIVE_MASK) << VECTACTIVE_SHIFT));
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}
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case exports.VTOR:
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return core.VTOR;
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/* NVIC */
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case NVIC_ISPR:
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return core.pendingInterrupts >>> 0;
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case NVIC_ICPR:
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return core.pendingInterrupts >>> 0;
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case NVIC_ISER:
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return core.enabledInterrupts >>> 0;
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99
|
-
case NVIC_ICER:
|
|
100
|
-
return core.enabledInterrupts >>> 0;
|
|
101
|
-
case NVIC_IPR0:
|
|
102
|
-
case NVIC_IPR1:
|
|
103
|
-
case NVIC_IPR2:
|
|
104
|
-
case NVIC_IPR3:
|
|
105
|
-
case NVIC_IPR4:
|
|
106
|
-
case NVIC_IPR5:
|
|
107
|
-
case NVIC_IPR6:
|
|
108
|
-
case NVIC_IPR7: {
|
|
109
|
-
const regIndex = (offset - NVIC_IPR0) >> 2;
|
|
110
|
-
let result = 0;
|
|
111
|
-
for (let byteIndex = 0; byteIndex < 4; byteIndex++) {
|
|
112
|
-
const interruptNumber = regIndex * 4 + byteIndex;
|
|
113
|
-
for (let priority = 0; priority < core.interruptPriorities.length; priority++) {
|
|
114
|
-
if (core.interruptPriorities[priority] & (1 << interruptNumber)) {
|
|
115
|
-
result |= priority << (8 * byteIndex + 6);
|
|
116
|
-
}
|
|
117
|
-
}
|
|
118
|
-
}
|
|
119
|
-
return result;
|
|
120
|
-
}
|
|
121
|
-
case exports.SHPR2:
|
|
122
|
-
return core.SHPR2;
|
|
123
|
-
case exports.SHPR3:
|
|
124
|
-
return core.SHPR3;
|
|
125
|
-
/* SysTick */
|
|
126
|
-
case SYST_CSR: {
|
|
127
|
-
const countFlagValue = this.systickCountFlag ? 1 << 16 : 0;
|
|
128
|
-
const clkSourceValue = this.systickClkSource ? 1 << 2 : 0;
|
|
129
|
-
const tickIntValue = this.systickIntEnable ? 1 << 1 : 0;
|
|
130
|
-
const enableFlagValue = this.systickTimer.enable ? 1 << 0 : 0;
|
|
131
|
-
this.systickCountFlag = false;
|
|
132
|
-
return countFlagValue | clkSourceValue | tickIntValue | enableFlagValue;
|
|
133
|
-
}
|
|
134
|
-
case SYST_CVR:
|
|
135
|
-
return this.systickTimer.counter;
|
|
136
|
-
case SYST_RVR:
|
|
137
|
-
return this.systickReload;
|
|
138
|
-
case SYST_CALIB:
|
|
139
|
-
return 0x0000270f;
|
|
140
|
-
}
|
|
141
|
-
return super.readUint32(offset);
|
|
142
|
-
}
|
|
143
|
-
writeUint32(offset, value) {
|
|
144
|
-
const { rp2040 } = this;
|
|
145
|
-
const { core } = rp2040;
|
|
146
|
-
const hardwareInterruptMask = (1 <<
|
|
147
|
-
switch (offset) {
|
|
148
|
-
case exports.ICSR:
|
|
149
|
-
if (value & NMIPENDSET) {
|
|
150
|
-
core.pendingNMI = true;
|
|
151
|
-
core.interruptsUpdated = true;
|
|
152
|
-
}
|
|
153
|
-
if (value & PENDSVSET) {
|
|
154
|
-
core.pendingPendSV = true;
|
|
155
|
-
core.interruptsUpdated = true;
|
|
156
|
-
}
|
|
157
|
-
if (value & PENDSVCLR) {
|
|
158
|
-
core.pendingPendSV = false;
|
|
159
|
-
}
|
|
160
|
-
if (value & PENDSTSET) {
|
|
161
|
-
core.pendingSystick = true;
|
|
162
|
-
core.interruptsUpdated = true;
|
|
163
|
-
}
|
|
164
|
-
if (value & PENDSTCLR) {
|
|
165
|
-
core.pendingSystick = false;
|
|
166
|
-
}
|
|
167
|
-
return;
|
|
168
|
-
case exports.VTOR:
|
|
169
|
-
core.VTOR = value;
|
|
170
|
-
return;
|
|
171
|
-
/* NVIC */
|
|
172
|
-
case NVIC_ISPR:
|
|
173
|
-
core.pendingInterrupts |= value;
|
|
174
|
-
core.interruptsUpdated = true;
|
|
175
|
-
return;
|
|
176
|
-
case NVIC_ICPR:
|
|
177
|
-
core.pendingInterrupts &= ~value | hardwareInterruptMask;
|
|
178
|
-
return;
|
|
179
|
-
case NVIC_ISER:
|
|
180
|
-
core.enabledInterrupts |= value;
|
|
181
|
-
core.interruptsUpdated = true;
|
|
182
|
-
return;
|
|
183
|
-
case NVIC_ICER:
|
|
184
|
-
core.enabledInterrupts &= ~value;
|
|
185
|
-
return;
|
|
186
|
-
case NVIC_IPR0:
|
|
187
|
-
case NVIC_IPR1:
|
|
188
|
-
case NVIC_IPR2:
|
|
189
|
-
case NVIC_IPR3:
|
|
190
|
-
case NVIC_IPR4:
|
|
191
|
-
case NVIC_IPR5:
|
|
192
|
-
case NVIC_IPR6:
|
|
193
|
-
case NVIC_IPR7: {
|
|
194
|
-
const regIndex = (offset - NVIC_IPR0) >> 2;
|
|
195
|
-
for (let byteIndex = 0; byteIndex < 4; byteIndex++) {
|
|
196
|
-
const interruptNumber = regIndex * 4 + byteIndex;
|
|
197
|
-
const newPriority = (value >> (8 * byteIndex + 6)) & 0x3;
|
|
198
|
-
for (let priority = 0; priority < core.interruptPriorities.length; priority++) {
|
|
199
|
-
core.interruptPriorities[priority] &= ~(1 << interruptNumber);
|
|
200
|
-
}
|
|
201
|
-
core.interruptPriorities[newPriority] |= 1 << interruptNumber;
|
|
202
|
-
}
|
|
203
|
-
core.interruptsUpdated = true;
|
|
204
|
-
return;
|
|
205
|
-
}
|
|
206
|
-
case exports.SHPR2:
|
|
207
|
-
core.SHPR2 = value;
|
|
208
|
-
return;
|
|
209
|
-
case exports.SHPR3:
|
|
210
|
-
core.SHPR3 = value;
|
|
211
|
-
return;
|
|
212
|
-
// SysTick
|
|
213
|
-
case SYST_CSR:
|
|
214
|
-
this.systickClkSource = value & (1 << 2) ? true : false;
|
|
215
|
-
this.systickIntEnable = value & (1 << 1) ? true : false;
|
|
216
|
-
this.systickTimer.enable = value & (1 << 0) ? true : false;
|
|
217
|
-
return;
|
|
218
|
-
case SYST_CVR:
|
|
219
|
-
this.systickTimer.set(0);
|
|
220
|
-
return;
|
|
221
|
-
case SYST_RVR:
|
|
222
|
-
this.systickReload = value;
|
|
223
|
-
return;
|
|
224
|
-
default:
|
|
225
|
-
super.writeUint32(offset, value);
|
|
226
|
-
}
|
|
227
|
-
}
|
|
228
|
-
}
|
|
229
|
-
exports.RPPPB = RPPPB;
|
|
1
|
+
"use strict";
|
|
2
|
+
Object.defineProperty(exports, "__esModule", { value: true });
|
|
3
|
+
exports.RPPPB = exports.SHPR3 = exports.SHPR2 = exports.VTOR = exports.ICSR = exports.CPUID = void 0;
|
|
4
|
+
const irq_js_1 = require("../irq.js");
|
|
5
|
+
const timer32_js_1 = require("../utils/timer32.js");
|
|
6
|
+
const peripheral_js_1 = require("./peripheral.js");
|
|
7
|
+
exports.CPUID = 0xd00;
|
|
8
|
+
exports.ICSR = 0xd04;
|
|
9
|
+
exports.VTOR = 0xd08;
|
|
10
|
+
exports.SHPR2 = 0xd1c;
|
|
11
|
+
exports.SHPR3 = 0xd20;
|
|
12
|
+
const SYST_CSR = 0x010; // SysTick Control and Status Register
|
|
13
|
+
const SYST_RVR = 0x014; // SysTick Reload Value Register
|
|
14
|
+
const SYST_CVR = 0x018; // SysTick Current Value Register
|
|
15
|
+
const SYST_CALIB = 0x01c; // SysTick Calibration Value Register
|
|
16
|
+
const NVIC_ISER = 0x100; // Interrupt Set-Enable Register
|
|
17
|
+
const NVIC_ICER = 0x180; // Interrupt Clear-Enable Register
|
|
18
|
+
const NVIC_ISPR = 0x200; // Interrupt Set-Pending Register
|
|
19
|
+
const NVIC_ICPR = 0x280; // Interrupt Clear-Pending Register
|
|
20
|
+
// Interrupt priority registers:
|
|
21
|
+
const NVIC_IPR0 = 0x400;
|
|
22
|
+
const NVIC_IPR1 = 0x404;
|
|
23
|
+
const NVIC_IPR2 = 0x408;
|
|
24
|
+
const NVIC_IPR3 = 0x40c;
|
|
25
|
+
const NVIC_IPR4 = 0x410;
|
|
26
|
+
const NVIC_IPR5 = 0x414;
|
|
27
|
+
const NVIC_IPR6 = 0x418;
|
|
28
|
+
const NVIC_IPR7 = 0x41c;
|
|
29
|
+
/** ICSR Bits */
|
|
30
|
+
const NMIPENDSET = 1 << 31;
|
|
31
|
+
const PENDSVSET = 1 << 28;
|
|
32
|
+
const PENDSVCLR = 1 << 27;
|
|
33
|
+
const PENDSTSET = 1 << 26;
|
|
34
|
+
const PENDSTCLR = 1 << 25;
|
|
35
|
+
const ISRPREEMPT = 1 << 23;
|
|
36
|
+
const ISRPENDING = 1 << 22;
|
|
37
|
+
const VECTPENDING_MASK = 0x1ff;
|
|
38
|
+
const VECTPENDING_SHIFT = 12;
|
|
39
|
+
const VECTACTIVE_MASK = 0x1ff;
|
|
40
|
+
const VECTACTIVE_SHIFT = 0;
|
|
41
|
+
/** PPB stands for Private Periphral Bus.
|
|
42
|
+
* These are peripherals that are part of the ARM Cortex Core, and there's one copy for each processor core.
|
|
43
|
+
*
|
|
44
|
+
* Included peripheral: NVIC, SysTick timer
|
|
45
|
+
*/
|
|
46
|
+
class RPPPB extends peripheral_js_1.BasePeripheral {
|
|
47
|
+
constructor(rp2040, name) {
|
|
48
|
+
super(rp2040, name);
|
|
49
|
+
// Systick
|
|
50
|
+
this.systickCountFlag = false;
|
|
51
|
+
this.systickClkSource = false;
|
|
52
|
+
this.systickIntEnable = false;
|
|
53
|
+
this.systickReload = 0;
|
|
54
|
+
this.systickTimer = new timer32_js_1.Timer32(this.rp2040.clock, this.rp2040.clkSys);
|
|
55
|
+
this.systickAlarm = new timer32_js_1.Timer32PeriodicAlarm(this.systickTimer, () => {
|
|
56
|
+
this.systickCountFlag = true;
|
|
57
|
+
if (this.systickIntEnable) {
|
|
58
|
+
this.rp2040.core.pendingSystick = true;
|
|
59
|
+
this.rp2040.core.interruptsUpdated = true;
|
|
60
|
+
}
|
|
61
|
+
this.systickTimer.set(this.systickReload);
|
|
62
|
+
});
|
|
63
|
+
this.systickTimer.top = 0xffffff;
|
|
64
|
+
this.systickTimer.mode = timer32_js_1.TimerMode.Decrement;
|
|
65
|
+
this.systickAlarm.target = 0;
|
|
66
|
+
this.systickAlarm.enable = true;
|
|
67
|
+
this.reset();
|
|
68
|
+
}
|
|
69
|
+
reset() {
|
|
70
|
+
this.writeUint32(SYST_CSR, 0);
|
|
71
|
+
this.writeUint32(SYST_RVR, 0xffffff);
|
|
72
|
+
this.systickTimer.set(0xffffff);
|
|
73
|
+
}
|
|
74
|
+
readUint32(offset) {
|
|
75
|
+
const { rp2040 } = this;
|
|
76
|
+
const { core } = rp2040;
|
|
77
|
+
switch (offset) {
|
|
78
|
+
case exports.CPUID:
|
|
79
|
+
return 0x410cc601; /* Verified against actual hardware */
|
|
80
|
+
case exports.ICSR: {
|
|
81
|
+
const pendingInterrupts = core.pendingInterrupts || core.pendingPendSV || core.pendingSystick || core.pendingSVCall;
|
|
82
|
+
const vectPending = core.vectPending;
|
|
83
|
+
return ((core.pendingNMI ? NMIPENDSET : 0) |
|
|
84
|
+
(core.pendingPendSV ? PENDSVSET : 0) |
|
|
85
|
+
(core.pendingSystick ? PENDSTSET : 0) |
|
|
86
|
+
(pendingInterrupts ? ISRPENDING : 0) |
|
|
87
|
+
(vectPending << VECTPENDING_SHIFT) |
|
|
88
|
+
((core.IPSR & VECTACTIVE_MASK) << VECTACTIVE_SHIFT));
|
|
89
|
+
}
|
|
90
|
+
case exports.VTOR:
|
|
91
|
+
return core.VTOR;
|
|
92
|
+
/* NVIC */
|
|
93
|
+
case NVIC_ISPR:
|
|
94
|
+
return core.pendingInterrupts >>> 0;
|
|
95
|
+
case NVIC_ICPR:
|
|
96
|
+
return core.pendingInterrupts >>> 0;
|
|
97
|
+
case NVIC_ISER:
|
|
98
|
+
return core.enabledInterrupts >>> 0;
|
|
99
|
+
case NVIC_ICER:
|
|
100
|
+
return core.enabledInterrupts >>> 0;
|
|
101
|
+
case NVIC_IPR0:
|
|
102
|
+
case NVIC_IPR1:
|
|
103
|
+
case NVIC_IPR2:
|
|
104
|
+
case NVIC_IPR3:
|
|
105
|
+
case NVIC_IPR4:
|
|
106
|
+
case NVIC_IPR5:
|
|
107
|
+
case NVIC_IPR6:
|
|
108
|
+
case NVIC_IPR7: {
|
|
109
|
+
const regIndex = (offset - NVIC_IPR0) >> 2;
|
|
110
|
+
let result = 0;
|
|
111
|
+
for (let byteIndex = 0; byteIndex < 4; byteIndex++) {
|
|
112
|
+
const interruptNumber = regIndex * 4 + byteIndex;
|
|
113
|
+
for (let priority = 0; priority < core.interruptPriorities.length; priority++) {
|
|
114
|
+
if (core.interruptPriorities[priority] & (1 << interruptNumber)) {
|
|
115
|
+
result |= priority << (8 * byteIndex + 6);
|
|
116
|
+
}
|
|
117
|
+
}
|
|
118
|
+
}
|
|
119
|
+
return result;
|
|
120
|
+
}
|
|
121
|
+
case exports.SHPR2:
|
|
122
|
+
return core.SHPR2;
|
|
123
|
+
case exports.SHPR3:
|
|
124
|
+
return core.SHPR3;
|
|
125
|
+
/* SysTick */
|
|
126
|
+
case SYST_CSR: {
|
|
127
|
+
const countFlagValue = this.systickCountFlag ? 1 << 16 : 0;
|
|
128
|
+
const clkSourceValue = this.systickClkSource ? 1 << 2 : 0;
|
|
129
|
+
const tickIntValue = this.systickIntEnable ? 1 << 1 : 0;
|
|
130
|
+
const enableFlagValue = this.systickTimer.enable ? 1 << 0 : 0;
|
|
131
|
+
this.systickCountFlag = false;
|
|
132
|
+
return countFlagValue | clkSourceValue | tickIntValue | enableFlagValue;
|
|
133
|
+
}
|
|
134
|
+
case SYST_CVR:
|
|
135
|
+
return this.systickTimer.counter;
|
|
136
|
+
case SYST_RVR:
|
|
137
|
+
return this.systickReload;
|
|
138
|
+
case SYST_CALIB:
|
|
139
|
+
return 0x0000270f;
|
|
140
|
+
}
|
|
141
|
+
return super.readUint32(offset);
|
|
142
|
+
}
|
|
143
|
+
writeUint32(offset, value) {
|
|
144
|
+
const { rp2040 } = this;
|
|
145
|
+
const { core } = rp2040;
|
|
146
|
+
const hardwareInterruptMask = (1 << irq_js_1.MAX_HARDWARE_IRQ) - 1;
|
|
147
|
+
switch (offset) {
|
|
148
|
+
case exports.ICSR:
|
|
149
|
+
if (value & NMIPENDSET) {
|
|
150
|
+
core.pendingNMI = true;
|
|
151
|
+
core.interruptsUpdated = true;
|
|
152
|
+
}
|
|
153
|
+
if (value & PENDSVSET) {
|
|
154
|
+
core.pendingPendSV = true;
|
|
155
|
+
core.interruptsUpdated = true;
|
|
156
|
+
}
|
|
157
|
+
if (value & PENDSVCLR) {
|
|
158
|
+
core.pendingPendSV = false;
|
|
159
|
+
}
|
|
160
|
+
if (value & PENDSTSET) {
|
|
161
|
+
core.pendingSystick = true;
|
|
162
|
+
core.interruptsUpdated = true;
|
|
163
|
+
}
|
|
164
|
+
if (value & PENDSTCLR) {
|
|
165
|
+
core.pendingSystick = false;
|
|
166
|
+
}
|
|
167
|
+
return;
|
|
168
|
+
case exports.VTOR:
|
|
169
|
+
core.VTOR = value;
|
|
170
|
+
return;
|
|
171
|
+
/* NVIC */
|
|
172
|
+
case NVIC_ISPR:
|
|
173
|
+
core.pendingInterrupts |= value;
|
|
174
|
+
core.interruptsUpdated = true;
|
|
175
|
+
return;
|
|
176
|
+
case NVIC_ICPR:
|
|
177
|
+
core.pendingInterrupts &= ~value | hardwareInterruptMask;
|
|
178
|
+
return;
|
|
179
|
+
case NVIC_ISER:
|
|
180
|
+
core.enabledInterrupts |= value;
|
|
181
|
+
core.interruptsUpdated = true;
|
|
182
|
+
return;
|
|
183
|
+
case NVIC_ICER:
|
|
184
|
+
core.enabledInterrupts &= ~value;
|
|
185
|
+
return;
|
|
186
|
+
case NVIC_IPR0:
|
|
187
|
+
case NVIC_IPR1:
|
|
188
|
+
case NVIC_IPR2:
|
|
189
|
+
case NVIC_IPR3:
|
|
190
|
+
case NVIC_IPR4:
|
|
191
|
+
case NVIC_IPR5:
|
|
192
|
+
case NVIC_IPR6:
|
|
193
|
+
case NVIC_IPR7: {
|
|
194
|
+
const regIndex = (offset - NVIC_IPR0) >> 2;
|
|
195
|
+
for (let byteIndex = 0; byteIndex < 4; byteIndex++) {
|
|
196
|
+
const interruptNumber = regIndex * 4 + byteIndex;
|
|
197
|
+
const newPriority = (value >> (8 * byteIndex + 6)) & 0x3;
|
|
198
|
+
for (let priority = 0; priority < core.interruptPriorities.length; priority++) {
|
|
199
|
+
core.interruptPriorities[priority] &= ~(1 << interruptNumber);
|
|
200
|
+
}
|
|
201
|
+
core.interruptPriorities[newPriority] |= 1 << interruptNumber;
|
|
202
|
+
}
|
|
203
|
+
core.interruptsUpdated = true;
|
|
204
|
+
return;
|
|
205
|
+
}
|
|
206
|
+
case exports.SHPR2:
|
|
207
|
+
core.SHPR2 = value;
|
|
208
|
+
return;
|
|
209
|
+
case exports.SHPR3:
|
|
210
|
+
core.SHPR3 = value;
|
|
211
|
+
return;
|
|
212
|
+
// SysTick
|
|
213
|
+
case SYST_CSR:
|
|
214
|
+
this.systickClkSource = value & (1 << 2) ? true : false;
|
|
215
|
+
this.systickIntEnable = value & (1 << 1) ? true : false;
|
|
216
|
+
this.systickTimer.enable = value & (1 << 0) ? true : false;
|
|
217
|
+
return;
|
|
218
|
+
case SYST_CVR:
|
|
219
|
+
this.systickTimer.set(0);
|
|
220
|
+
return;
|
|
221
|
+
case SYST_RVR:
|
|
222
|
+
this.systickReload = value;
|
|
223
|
+
return;
|
|
224
|
+
default:
|
|
225
|
+
super.writeUint32(offset, value);
|
|
226
|
+
}
|
|
227
|
+
}
|
|
228
|
+
}
|
|
229
|
+
exports.RPPPB = RPPPB;
|
|
@@ -1,65 +1,65 @@
|
|
|
1
|
-
import { IClock } from '../clock/clock';
|
|
2
|
-
import { Timer32, Timer32PeriodicAlarm } from '../utils/timer32';
|
|
3
|
-
import { BasePeripheral, Peripheral } from './peripheral';
|
|
4
|
-
declare enum PWMDivMode {
|
|
5
|
-
FreeRunning = 0,
|
|
6
|
-
BGated = 1,
|
|
7
|
-
BRisingEdge = 2,
|
|
8
|
-
BFallingEdge = 3
|
|
9
|
-
}
|
|
10
|
-
declare class PWMChannel {
|
|
11
|
-
private pwm;
|
|
12
|
-
readonly clock: IClock;
|
|
13
|
-
readonly index: number;
|
|
14
|
-
readonly timer: Timer32;
|
|
15
|
-
readonly alarmA: Timer32PeriodicAlarm;
|
|
16
|
-
readonly alarmB: Timer32PeriodicAlarm;
|
|
17
|
-
readonly alarmBottom: Timer32PeriodicAlarm;
|
|
18
|
-
csr: number;
|
|
19
|
-
div: number;
|
|
20
|
-
cc: number;
|
|
21
|
-
top: number;
|
|
22
|
-
lastBValue: boolean;
|
|
23
|
-
countingUp: boolean;
|
|
24
|
-
ccUpdated: boolean;
|
|
25
|
-
topUpdated: boolean;
|
|
26
|
-
tickCounter: number;
|
|
27
|
-
divMode: PWMDivMode;
|
|
28
|
-
readonly pinA1: number;
|
|
29
|
-
readonly pinB1: number;
|
|
30
|
-
readonly pinA2: number;
|
|
31
|
-
readonly pinB2: number;
|
|
32
|
-
constructor(pwm: RPPWM, clock: IClock, index: number);
|
|
33
|
-
readRegister(offset: number): number;
|
|
34
|
-
writeRegister(offset: number, value: number): void;
|
|
35
|
-
reset(): void;
|
|
36
|
-
private updateDoubleBuffered;
|
|
37
|
-
private wrap;
|
|
38
|
-
setA(value: boolean): void;
|
|
39
|
-
setB(value: boolean): void;
|
|
40
|
-
get gpioBValue(): boolean;
|
|
41
|
-
setBDirection(value: boolean): void;
|
|
42
|
-
gpioBChanged(): void;
|
|
43
|
-
updateEnable(): void;
|
|
44
|
-
set en(value: number);
|
|
45
|
-
}
|
|
46
|
-
export declare class RPPWM extends BasePeripheral implements Peripheral {
|
|
47
|
-
readonly channels: PWMChannel[];
|
|
48
|
-
private intRaw;
|
|
49
|
-
private intEnable;
|
|
50
|
-
private intForce;
|
|
51
|
-
gpioValue: number;
|
|
52
|
-
gpioDirection: number;
|
|
53
|
-
get intStatus(): number;
|
|
54
|
-
readUint32(offset: number): number;
|
|
55
|
-
writeUint32(offset: number, value: number): void;
|
|
56
|
-
get clockFreq(): number;
|
|
57
|
-
channelInterrupt(index: number): void;
|
|
58
|
-
checkInterrupts(): void;
|
|
59
|
-
gpioSet(index: number, value: boolean): void;
|
|
60
|
-
gpioSetDir(index: number, output: boolean): void;
|
|
61
|
-
gpioRead(index: number): boolean;
|
|
62
|
-
gpioOnInput(index: number): void;
|
|
63
|
-
reset(): void;
|
|
64
|
-
}
|
|
65
|
-
export {};
|
|
1
|
+
import { IClock } from '../clock/clock.js';
|
|
2
|
+
import { Timer32, Timer32PeriodicAlarm } from '../utils/timer32.js';
|
|
3
|
+
import { BasePeripheral, Peripheral } from './peripheral.js';
|
|
4
|
+
declare enum PWMDivMode {
|
|
5
|
+
FreeRunning = 0,
|
|
6
|
+
BGated = 1,
|
|
7
|
+
BRisingEdge = 2,
|
|
8
|
+
BFallingEdge = 3
|
|
9
|
+
}
|
|
10
|
+
declare class PWMChannel {
|
|
11
|
+
private pwm;
|
|
12
|
+
readonly clock: IClock;
|
|
13
|
+
readonly index: number;
|
|
14
|
+
readonly timer: Timer32;
|
|
15
|
+
readonly alarmA: Timer32PeriodicAlarm;
|
|
16
|
+
readonly alarmB: Timer32PeriodicAlarm;
|
|
17
|
+
readonly alarmBottom: Timer32PeriodicAlarm;
|
|
18
|
+
csr: number;
|
|
19
|
+
div: number;
|
|
20
|
+
cc: number;
|
|
21
|
+
top: number;
|
|
22
|
+
lastBValue: boolean;
|
|
23
|
+
countingUp: boolean;
|
|
24
|
+
ccUpdated: boolean;
|
|
25
|
+
topUpdated: boolean;
|
|
26
|
+
tickCounter: number;
|
|
27
|
+
divMode: PWMDivMode;
|
|
28
|
+
readonly pinA1: number;
|
|
29
|
+
readonly pinB1: number;
|
|
30
|
+
readonly pinA2: number;
|
|
31
|
+
readonly pinB2: number;
|
|
32
|
+
constructor(pwm: RPPWM, clock: IClock, index: number);
|
|
33
|
+
readRegister(offset: number): number;
|
|
34
|
+
writeRegister(offset: number, value: number): void;
|
|
35
|
+
reset(): void;
|
|
36
|
+
private updateDoubleBuffered;
|
|
37
|
+
private wrap;
|
|
38
|
+
setA(value: boolean): void;
|
|
39
|
+
setB(value: boolean): void;
|
|
40
|
+
get gpioBValue(): boolean;
|
|
41
|
+
setBDirection(value: boolean): void;
|
|
42
|
+
gpioBChanged(): void;
|
|
43
|
+
updateEnable(): void;
|
|
44
|
+
set en(value: number);
|
|
45
|
+
}
|
|
46
|
+
export declare class RPPWM extends BasePeripheral implements Peripheral {
|
|
47
|
+
readonly channels: PWMChannel[];
|
|
48
|
+
private intRaw;
|
|
49
|
+
private intEnable;
|
|
50
|
+
private intForce;
|
|
51
|
+
gpioValue: number;
|
|
52
|
+
gpioDirection: number;
|
|
53
|
+
get intStatus(): number;
|
|
54
|
+
readUint32(offset: number): number;
|
|
55
|
+
writeUint32(offset: number, value: number): void;
|
|
56
|
+
get clockFreq(): number;
|
|
57
|
+
channelInterrupt(index: number): void;
|
|
58
|
+
checkInterrupts(): void;
|
|
59
|
+
gpioSet(index: number, value: boolean): void;
|
|
60
|
+
gpioSetDir(index: number, output: boolean): void;
|
|
61
|
+
gpioRead(index: number): boolean;
|
|
62
|
+
gpioOnInput(index: number): void;
|
|
63
|
+
reset(): void;
|
|
64
|
+
}
|
|
65
|
+
export {};
|