udb 0.1.9 → 0.1.13

data/.data/spec/std/isa/inst/V/vmv.x.s.yaml

@@ -34,6 +34,6 @@ operation(): |
   VectorState state = vector_state();
 
   # vmv.x.s copies element 0 of vs2 to xd, sign-extending to XLEN
-  X[xd] = $signed(v[vs2][state.sew-1:0]);
+  X[xd] = $signed(V[vs2][state.sew-1:0]);
 
   CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vmxnor.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: (vs2 == vs1) && (vd == vs2)
+    to: vmset.m vd
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmxor.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: (vs2 == vs1) && (vd == vs2)
+    to: vmclr.m vd
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vncvt.x.x.w vd, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vrsub.vx.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vneg.v vd, vs2, vm
 data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/V/vse8.v.yaml

@@ -31,9 +31,8 @@ data_independent_timing: false
 operation(): |
   XReg virtual_address = X[xs1];
   # "A simple in-order implementation can ignore the settings and simply execute all vector instructions using the undisturbed policy"
-  for (U32 i = 0; i < CSR[vl].VALUE; i++) {
-    U32 start_bit_pos = (CSR[vstart].VALUE + i) * 8;
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * 8;
     U32 end_bit_pos = start_bit_pos + 7;
-    write_memory(8, virtual_address, v[vs3][end_bit_pos:start_bit_pos], $encoding);
-    virtual_address = virtual_address + 1;
+    write_memory(8, virtual_address + i, V[vs3][end_bit_pos:start_bit_pos], $encoding);
   }

data/.data/spec/std/isa/inst/V/vwadd.vx.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vwcvt.x.x.v vd, vs2, vm
 data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/V/vwaddu.vx.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: vwcvtu.x.x.v vd, vs2, vm
 data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/V/vxor.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:
@@ -29,5 +30,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm == -1
+    to: vnot.v vd, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/Zalasr/lSIZE.AQRL.layout

@@ -7,10 +7,10 @@
   raise "'rl' must be defined as true or false" unless [true, false].include?(rl)
 
   size_info = {
-    "b" => { funct3: "000", long_name_suffix: "Byte" },
-    "h" => { funct3: "001", long_name_suffix: "Halfword" },
-    "w" => { funct3: "010", long_name_suffix: "Word" },
-    "d" => { funct3: "011", long_name_suffix: "Doubleword" }
+    "b" => { funct3: "000", long_name_suffix: "Byte", bits: 8 },
+    "h" => { funct3: "001", long_name_suffix: "Halfword", bits: 16 },
+    "w" => { funct3: "010", long_name_suffix: "Word", bits: 32 },
+    "d" => { funct3: "011", long_name_suffix: "Doubleword", bits: 64 }
   }
 
   current_size = size_info[size]
@@ -19,6 +19,11 @@
   rl_bit = rl ? "1" : "0"
   acquire_suffix = " Acquire"
   release_suffix = rl ? " Release" : ""
+
+  aq_bit_val = "1'b1"
+  rl_bit_val = rl ? "1'b1" : "1'b0"
+
+  alignment_bytes = current_size[:bits] / 8
 -%>
 
 $schema: "inst_schema.json#"
@@ -26,7 +31,30 @@ kind: instruction
 name: l<%= size %><%= aq_rl_suffix %>
 long_name: Load <%= current_size[:long_name_suffix] %><%= acquire_suffix %><%= release_suffix %>
 description: |
-  No description available.
+  Load <%= current_size[:bits] %> bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+<% if rl -%>
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes, and no previous memory operations can be observed to occur
+  after this load completes.
+<% else -%>
+
+  This instruction has acquire semantics, which means that no subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes. Acquire semantics provide ordering guarantees useful for
+  synchronization, such as reading a lock variable.
+<% end -%>
+<% if current_size[:bits] == 8 -%>
+
+  The address must be naturally aligned; if not, an address-misaligned or
+  access-fault exception will be raised.
+<% else -%>
+
+  The address must be naturally aligned (<%= alignment_bytes %>-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
+<% end -%>
 definedBy:
   extension:
     name: Zalasr
@@ -45,3 +73,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(<%= current_size[:bits] %>, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(<%= current_size[:bits] %>, virtual_address, $encoding, <%= aq_bit_val %>, <%= rl_bit_val %>), <%= current_size[:bits] %>);

data/.data/spec/std/isa/inst/Zalasr/lb.aq.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: lb.aq
 long_name: Load Byte Acquire
 description: |
-  No description available.
+  Load 8 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has acquire semantics, which means that no subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes. Acquire semantics provide ordering guarantees useful for
+  synchronization, such as reading a lock variable.
+
+  The address must be naturally aligned; if not, an address-misaligned or
+  access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(8, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(8, virtual_address, $encoding, 1'b1, 1'b0), 8);

data/.data/spec/std/isa/inst/Zalasr/lb.aqrl.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: lb.aqrl
 long_name: Load Byte Acquire Release
 description: |
-  No description available.
+  Load 8 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes, and no previous memory operations can be observed to occur
+  after this load completes.
+
+  The address must be naturally aligned; if not, an address-misaligned or
+  access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(8, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(8, virtual_address, $encoding, 1'b1, 1'b1), 8);

data/.data/spec/std/isa/inst/Zalasr/ld.aq.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: ld.aq
 long_name: Load Doubleword Acquire
 description: |
-  No description available.
+  Load 64 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has acquire semantics, which means that no subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes. Acquire semantics provide ordering guarantees useful for
+  synchronization, such as reading a lock variable.
+
+  The address must be naturally aligned (8-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(64, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(64, virtual_address, $encoding, 1'b1, 1'b0), 64);

data/.data/spec/std/isa/inst/Zalasr/ld.aqrl.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: ld.aqrl
 long_name: Load Doubleword Acquire Release
 description: |
-  No description available.
+  Load 64 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes, and no previous memory operations can be observed to occur
+  after this load completes.
+
+  The address must be naturally aligned (8-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(64, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(64, virtual_address, $encoding, 1'b1, 1'b1), 64);

data/.data/spec/std/isa/inst/Zalasr/lh.aq.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: lh.aq
 long_name: Load Halfword Acquire
 description: |
-  No description available.
+  Load 16 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has acquire semantics, which means that no subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes. Acquire semantics provide ordering guarantees useful for
+  synchronization, such as reading a lock variable.
+
+  The address must be naturally aligned (2-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(16, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(16, virtual_address, $encoding, 1'b1, 1'b0), 16);

data/.data/spec/std/isa/inst/Zalasr/lh.aqrl.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: lh.aqrl
 long_name: Load Halfword Acquire Release
 description: |
-  No description available.
+  Load 16 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes, and no previous memory operations can be observed to occur
+  after this load completes.
+
+  The address must be naturally aligned (2-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(16, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(16, virtual_address, $encoding, 1'b1, 1'b1), 16);

data/.data/spec/std/isa/inst/Zalasr/lw.aq.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: lw.aq
 long_name: Load Word Acquire
 description: |
-  No description available.
+  Load 32 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has acquire semantics, which means that no subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes. Acquire semantics provide ordering guarantees useful for
+  synchronization, such as reading a lock variable.
+
+  The address must be naturally aligned (4-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(32, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(32, virtual_address, $encoding, 1'b1, 1'b0), 32);

data/.data/spec/std/isa/inst/Zalasr/lw.aqrl.yaml

@@ -11,7 +11,16 @@ kind: instruction
 name: lw.aqrl
 long_name: Load Word Acquire Release
 description: |
-  No description available.
+  Load 32 bits of data from the address in `xs1` into register `xd`, sign-extending
+  the result to XLEN bits.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this load completes, and no previous memory operations can be observed to occur
+  after this load completes.
+
+  The address must be naturally aligned (4-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +39,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(32, virtual_address)) {
+    raise(ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+  }
+
+  X[xd] = sext(read_memory_aligned(32, virtual_address, $encoding, 1'b1, 1'b1), 32);

data/.data/spec/std/isa/inst/Zalasr/sSIZE.AQRL.layout

@@ -7,10 +7,10 @@
   raise "'aq' must be defined as true or false" unless [true, false].include?(aq)
 
   size_info = {
-    "b" => { funct3: "000", long_name_suffix: "Byte" },
-    "h" => { funct3: "001", long_name_suffix: "Halfword" },
-    "w" => { funct3: "010", long_name_suffix: "Word" },
-    "d" => { funct3: "011", long_name_suffix: "Doubleword" }
+    "b" => { funct3: "000", long_name_suffix: "Byte", bits: 8 },
+    "h" => { funct3: "001", long_name_suffix: "Halfword", bits: 16 },
+    "w" => { funct3: "010", long_name_suffix: "Word", bits: 32 },
+    "d" => { funct3: "011", long_name_suffix: "Doubleword", bits: 64 }
   }
 
   current_size = size_info[size]
@@ -19,6 +19,18 @@
   aq_bit = aq ? "1" : "0"
   acquire_suffix = aq ? " Acquire" : ""
   release_suffix = " Release"
+
+  aq_bit_val = aq ? "1'b1" : "1'b0"
+  rl_bit_val = "1'b1"
+
+  alignment_bytes = current_size[:bits] / 8
+
+  store_slice = case size
+                when "b" then "[7:0]"
+                when "h" then "[15:0]"
+                when "w" then "[31:0]"
+                when "d" then ""
+                end
 -%>
 
 $schema: "inst_schema.json#"
@@ -26,7 +38,29 @@ kind: instruction
 name: s<%= size %><%= aq_rl_suffix %>
 long_name: Store <%= current_size[:long_name_suffix] %><%= acquire_suffix %><%= release_suffix %>
 description: |
-  No description available.
+  Store the lowest <%= current_size[:bits] %> bits of register `xs2` to the address in `xs1`.
+<% if aq -%>
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this store completes, and no previous memory operations can be observed to occur
+  after this store completes.
+<% else -%>
+
+  This instruction has release semantics, which means that no previous memory
+  operations (in program order) from this hart can be observed to occur after
+  this store completes. Release semantics provide ordering guarantees useful for
+  synchronization, such as writing a lock variable to release it.
+<% end -%>
+<% if current_size[:bits] == 8 -%>
+
+  The address must be naturally aligned; if not, an address-misaligned or
+  access-fault exception will be raised.
+<% else -%>
+
+  The address must be naturally aligned (<%= alignment_bytes %>-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
+<% end -%>
 definedBy:
   extension:
     name: Zalasr
@@ -45,3 +79,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(<%= current_size[:bits] %>, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(<%= current_size[:bits] %>, virtual_address, X[xs2]<%= store_slice %>, $encoding, <%= aq_bit_val %>, <%= rl_bit_val %>);

data/.data/spec/std/isa/inst/Zalasr/sb.aqrl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sb.aqrl
 long_name: Store Byte Acquire Release
 description: |
-  No description available.
+  Store the lowest 8 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this store completes, and no previous memory operations can be observed to occur
+  after this store completes.
+
+  The address must be naturally aligned; if not, an address-misaligned or
+  access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(8, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(8, virtual_address, X[xs2][7:0], $encoding, 1'b1, 1'b1);

data/.data/spec/std/isa/inst/Zalasr/sb.rl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sb.rl
 long_name: Store Byte Release
 description: |
-  No description available.
+  Store the lowest 8 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has release semantics, which means that no previous memory
+  operations (in program order) from this hart can be observed to occur after
+  this store completes. Release semantics provide ordering guarantees useful for
+  synchronization, such as writing a lock variable to release it.
+
+  The address must be naturally aligned; if not, an address-misaligned or
+  access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(8, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(8, virtual_address, X[xs2][7:0], $encoding, 1'b0, 1'b1);

data/.data/spec/std/isa/inst/Zalasr/sd.aqrl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sd.aqrl
 long_name: Store Doubleword Acquire Release
 description: |
-  No description available.
+  Store the lowest 64 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this store completes, and no previous memory operations can be observed to occur
+  after this store completes.
+
+  The address must be naturally aligned (8-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(64, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(64, virtual_address, X[xs2], $encoding, 1'b1, 1'b1);

data/.data/spec/std/isa/inst/Zalasr/sd.rl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sd.rl
 long_name: Store Doubleword Release
 description: |
-  No description available.
+  Store the lowest 64 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has release semantics, which means that no previous memory
+  operations (in program order) from this hart can be observed to occur after
+  this store completes. Release semantics provide ordering guarantees useful for
+  synchronization, such as writing a lock variable to release it.
+
+  The address must be naturally aligned (8-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(64, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(64, virtual_address, X[xs2], $encoding, 1'b0, 1'b1);

data/.data/spec/std/isa/inst/Zalasr/sh.aqrl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sh.aqrl
 long_name: Store Halfword Acquire Release
 description: |
-  No description available.
+  Store the lowest 16 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this store completes, and no previous memory operations can be observed to occur
+  after this store completes.
+
+  The address must be naturally aligned (2-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(16, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(16, virtual_address, X[xs2][15:0], $encoding, 1'b1, 1'b1);

data/.data/spec/std/isa/inst/Zalasr/sh.rl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sh.rl
 long_name: Store Halfword Release
 description: |
-  No description available.
+  Store the lowest 16 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has release semantics, which means that no previous memory
+  operations (in program order) from this hart can be observed to occur after
+  this store completes. Release semantics provide ordering guarantees useful for
+  synchronization, such as writing a lock variable to release it.
+
+  The address must be naturally aligned (2-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(16, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(16, virtual_address, X[xs2][15:0], $encoding, 1'b0, 1'b1);