udb 0.1.9 → 0.1.13

data/.data/spec/std/isa/ext/A.yaml

@@ -19,13 +19,11 @@ versions:
       - name: Unknown
         email: unknown@void.segfault
         company: Unknown
-    requirements:
-      extension:
-        allOf:
-          - name: Zaamo
-            version: "= 1.0.0"
-          - name: Zalrsc
-            version: "= 1.0.0"
+requirements:
+  extension:
+    allOf:
+      - name: Zaamo
+      - name: Zalrsc
 description: |
 
   The atomic-instruction extension, named `A`, contains

data/.data/spec/std/isa/ext/S.yaml

@@ -12,12 +12,24 @@ versions:
 - version: "1.11.0"
   state: ratified
   ratification_date: 2019-06
+  requirements:
+    extension:
+      name: Sm
+      version: "= 1.11"
 - version: "1.12.0"
   state: ratified
   ratification_date: 2021-12
+  requirements:
+    extension:
+      name: Sm
+      version: "= 1.12"
 - version: "1.13.0"
   state: ratified
   ratification_date: 2024-10
+  requirements:
+    extension:
+      name: Sm
+      version: "= 1.13"
 requirements:
   extension:
     name: U

data/.data/spec/std/isa/ext/Smpmpmt.yaml

@@ -0,0 +1,52 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: CC-BY-4.0
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Smpmpmt
+long_name: PMP-based Memory Types Extension
+description: |
+  The Smpmpmt extension provides a mechanism analogous to Svpbmt but associated
+  with the PMP registers rather than page-table entries.
+  A new WARL field, MT (Memory Type), is added in the unallocated bits 6--5 in
+  each PMP configuration register.
+  The MT field of the lowest-numbered PMP register that an access matches,
+  following the existing PMP address-matching rules, overrides the PMAs for
+  that access.
+  If an access matches no PMP registers, or if the MT field of the matching PMP
+  register contains the value PMA, then the access proceeds as though the
+  Smpmpmt extension were not implemented.
+
+  NOTE: The permissions checks associated with a PMP register are unrelated to
+  whether an access is considered to match a PMP register.
+  For example, even though a PMP register with its L bit clear does not enforce
+  its permissions checks on M-mode accesses, M-mode accesses within the
+  address range of that PMP register are still considered to match.
+  Hence, that PMP register's MT field takes effect for matching M-mode accesses.
+
+  The MT field is encoded as shown below.
+  The encoding is identical to that of the PBMT field, and the meaning of each
+  type is as specified by the Svpbmt extension.
+  Refer to that specification for the semantics of each type.
+
+  The MT field encoding is identical to Svpbmt's PBMT field:
+
+  * 0 (PMA): No override; use platform PMAs.
+  * 1 (NC): Non-cacheable, idempotent, weakly-ordered (RVWMO) main memory.
+  * 2 (IO): Non-cacheable, non-idempotent, strongly-ordered (I/O ordering) I/O.
+  * 3: Reserved for future standard use.
+
+  The PMP-based memory types compose with the page-based memory types as follows.
+  First, the PMP-based memory types override the PMAs, producing an intermediate
+  set of attributes.
+  Then, supervisor-level memory attributes (e.g. the page-based attributes
+  described in the Svpbmt specification) override the intermediate attributes to
+  produce a final set of attributes.
+  As with Svpbmt, it is implementation-defined whether PMP-based memory types
+  override additional PMAs not explicitly listed in the table above.
+type: privileged
+versions:
+  - version: "0.6"
+    state: frozen

data/.data/spec/std/isa/ext/Sv32.yaml

@@ -10,25 +10,13 @@ long_name: 32-bit virtual address translation (3 level)
 description: 32-bit virtual address translation (3 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: 2019-05
-    requirements:
-      extension:
+requirements:
+  allOf:
+    - extension:
         name: S
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.13"
+    - param:
+        name: SXLEN
+        includes: 32

data/.data/spec/std/isa/ext/Sv39.yaml

@@ -10,25 +10,13 @@ long_name: 39-bit virtual address translation (3 level)
 description: 39-bit virtual address translation (3 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: 2019-05
-    requirements:
-      extension:
+requirements:
+  allOf:
+    - extension:
         name: S
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: S
-        version: ">= 1.13"
+    - param:
+        name: SXLEN
+        includes: 64

data/.data/spec/std/isa/ext/Sv48.yaml

@@ -10,25 +10,9 @@ long_name: 48-bit virtual address translation (4 level)
 description: 48-bit virtual address translation (4 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: 2019-05
-    requirements:
-      extension:
-        name: Sv39
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: Sv39
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: Sv39
-        version: ">= 1.13"
+requirements:
+  extension:
+    name: Sv39

data/.data/spec/std/isa/ext/Sv57.yaml

@@ -10,25 +10,9 @@ long_name: 57-bit virtual address translation (5 level)
 description: 57-bit virtual address translation (5 level)
 type: privileged
 versions:
-  - version: "1.11.0"
+  - version: "1.0"
     state: ratified
     ratification_date: unknown
-    requirements:
-      extension:
-        name: Sv48
-        version: ">= 1.11"
-  - version: "1.12.0"
-    state: ratified
-    ratification_date: 2021-12
-    url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
-    requirements:
-      extension:
-        name: Sv48
-        version: ">= 1.12"
-  - version: "1.13.0"
-    state: ratified
-    ratification_date: 2024-10
-    requirements:
-      extension:
-        name: Sv48
-        version: ">= 1.13"
+requirements:
+  extension:
+    name: Sv48

data/.data/spec/std/isa/ext/Svukte.yaml

@@ -0,0 +1,71 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: CC-BY-4.0
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Svukte
+long_name: Address-Independent Latency of User-Mode Faults to Supervisor Addresses
+type: privileged
+description: |
+  == "Svukte" Extension for Address-Independent Latency of User-Mode Faults to Supervisor Addresses, Version 0.4
+
+  The Svukte extension provides a means to make user-mode accesses to supervisor
+  memory raise page faults with timing that is independent of the address-translation
+  configuration and page-table contents, thereby mitigating attacks that attempt
+  to discover the supervisor software's address-space layout.
+
+  If the Svukte extension is implemented, the `senvcfg`.UKTE field is writable.
+  If the hypervisor extension is additionally implemented, the `hstatus`.HUKTE
+  field is also writable.
+  See <<sec:senvcfg>> and <<sec:hstatus>> for the definitions of those fields.
+
+  The Svukte extension depends on the Sv39 extension.
+
+  [NOTE]
+  ====
+  Svukte is not defined for Sv32 because the small address space limits the
+  available entropy, reducing the effectiveness of address-space layout
+  randomization.
+  If an Sv32 variant were to be defined, it would need to account for the fact
+  that it is more common to reserve only the upper 1 GiB of the virtual-address
+  space for the operating system, leaving the lower 3 GiB for user
+  processes.
+  ====
+
+  When `senvcfg`.UKTE=1 and the active `satp` register's MODE field is not Bare,
+  an instruction fetch or explicit memory access whose
+  effective privilege mode is U or VU is considered to be _Svukte-qualified_.
+  For any Svukte-qualified memory access, virtual addresses >= 2^SXLEN-1^ are
+  considered to be invalid; hence, an Svukte-qualified access to such an address
+  raises a page-fault exception corresponding to the original access type.
+  The timing of an instruction that raises an exception for this reason must be
+  independent of the faulting virtual address.
+
+  [NOTE]
+  ====
+  An Svukte-qualified access to such an address raises an exception even
+  if the underlying PTE would have otherwise allowed the access.
+  Practical implementations of Svukte will raise these exceptions based upon the
+  effective address, without accessing the page tables or address-translation
+  caches.
+  ====
+
+  [NOTE]
+  ====
+  Since whether an instruction is Svukte-qualified depends on the _effective_
+  privilege mode of the access, even some instructions executed in HS-mode or M-mode
+  (e.g. HLV with `hstatus`.SPVP=0, or LW with `mstatus`.MPRV=1 and
+  `mstatus`.MPP=U) are Svukte-qualified.
+  ====
+
+  As described in <<sec:hstatus>>, the `hstatus`.HUKTE field, rather than the
+  `senvcfg`.UKTE field, determines whether HLV, HLVX, and HSV instructions
+  executed within U-mode are Svukte-qualified.
+versions:
+  - version: "0.4.0"
+    state: development
+requirements:
+  extension:
+    name: Sv39

data/.data/spec/std/isa/ext/Zawrs.yaml

@@ -20,6 +20,6 @@ description: |
     accelerator device indicating completion of a job previously submitted to the device.
 type: unprivileged
 versions:
-  - version: "1.0.1"
+  - version: "1.0.0"
     state: ratified
     ratification_date: 2022-11

data/.data/spec/std/isa/ext/Zihpm.yaml

@@ -13,15 +13,3 @@ versions:
   - version: "2.0.0"
     state: ratified
     ratification_date: 2023-03
-requirements:
-  idl(): |
-    -> (HPM_COUNTER_EN[3] || HPM_COUNTER_EN[4] || HPM_COUNTER_EN[5] ||
-        HPM_COUNTER_EN[6] || HPM_COUNTER_EN[7] || HPM_COUNTER_EN[8] ||
-        HPM_COUNTER_EN[9] || HPM_COUNTER_EN[10] || HPM_COUNTER_EN[11] ||
-        HPM_COUNTER_EN[12] || HPM_COUNTER_EN[13] || HPM_COUNTER_EN[14] ||
-        HPM_COUNTER_EN[15] || HPM_COUNTER_EN[16] || HPM_COUNTER_EN[17] ||
-        HPM_COUNTER_EN[18] || HPM_COUNTER_EN[19] || HPM_COUNTER_EN[20] ||
-        HPM_COUNTER_EN[21] || HPM_COUNTER_EN[22] || HPM_COUNTER_EN[23] ||
-        HPM_COUNTER_EN[24] || HPM_COUNTER_EN[25] || HPM_COUNTER_EN[26] ||
-        HPM_COUNTER_EN[27] || HPM_COUNTER_EN[28] || HPM_COUNTER_EN[29] ||
-        HPM_COUNTER_EN[30] || HPM_COUNTER_EN[31]);

data/.data/spec/std/isa/inst/C/c.addi.yaml

@@ -22,6 +22,7 @@ encoding:
     - name: imm
       location: 12|6-2
       not: 0
+      sign_extend: true
     - name: xd
       location: 11-7
       not: 0

data/.data/spec/std/isa/inst/C/c.addi16sp.yaml

@@ -23,6 +23,7 @@ encoding:
       location: 12|4-3|5|2|6
       left_shift: 4
       not: 0
+      sign_extend: true
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/C/c.addiw.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 12|6-2
+      sign_extend: true
     - name: xd
       location: 11-7
       not: 0

data/.data/spec/std/isa/inst/C/c.andi.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 12|6-2
+      sign_extend: true
     - name: xd
       location: 9-7
 access:

data/.data/spec/std/isa/inst/C/c.ldsp.yaml

@@ -34,7 +34,7 @@ encoding:
         left_shift: 3
       - name: xd
         location: 11-7
-        not: [0, 1, 3, 5, 7]
+        not: [0, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
   RV64:
     match: 011-----------10
     variables:

data/.data/spec/std/isa/inst/C/c.li.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 12|6-2
+      sign_extend: true
     - name: xd
       location: 11-7
       not: 0

data/.data/spec/std/isa/inst/C/c.lui.yaml

@@ -22,6 +22,7 @@ encoding:
     - name: imm
       location: 12|6-2
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
       not: [0, 2]

data/.data/spec/std/isa/inst/C/c.mv.yaml

@@ -9,7 +9,7 @@ name: c.mv
 long_name: Move Register
 description: |
   C.MV (move register) performs copy of the data in register xs2 to register xd
-  C.MV expands to addi xd, x0, xs2.
+  C.MV expands to add xd, x0, xs2.
 definedBy:
   extension:
     name: Zca

data/.data/spec/std/isa/inst/C/c.sdsp.yaml

@@ -27,7 +27,7 @@ encoding:
     variables:
       - name: xs2
         location: 6-2
-        not: [1, 3, 5, 7]
+        not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
       - name: imm
         location: 9-7|12-10
         left_shift: 3

data/.data/spec/std/isa/inst/D/fsgnj.d.yaml

@@ -27,6 +27,9 @@ encoding:
       location: 19-15
     - name: fd
       location: 11-7
+pseudoinstructions:
+  - when: fs1 == fs2
+    to: fmv.d fd, fs1
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/D/fsgnjn.d.yaml

@@ -32,5 +32,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: fs1 == fs2
+    to: fneg.d fd, fs1
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/D/fsgnjx.d.yaml

@@ -32,5 +32,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: fs1 == fs2
+    to: fabs.d fd, fs1
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/F/fadd.s.yaml

@@ -34,19 +34,19 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  Bits<32> a = f[fs1];
-  Bits<32> b = f[fs2];
+  Bits<32> a = F[fs1];
+  Bits<32> b = F[fs2];
 
   if (implemented?(ExtensionName::D)) {
     # check for incorrectly NaN-boxed inputs
-    if (f[fs1][63:32] != 32'hffffffff) {
+    if (F[fs1][63:32] != 32'hffffffff) {
       a = SP_CANONICAL_NAN;
     }
-    if (f[fs2][63:32] != 32'hffffffff) {
+    if (F[fs2][63:32] != 32'hffffffff) {
       b = SP_CANONICAL_NAN;
     }
   }
 
-  f[fd] = f32_add(a, b, mode);
+  F[fd] = f32_add(a, b, mode);
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fclass.s.yaml

@@ -51,11 +51,11 @@ data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = f[fs1][31:0];
+  Bits<32> sp_value = F[fs1][31:0];
 
   if (implemented?(ExtensionName::D)) {
     # check for an incorrectly NaN-boxed value
-    if (f[fs1][63:32] != 32'hffffffff) {
+    if (F[fs1][63:32] != 32'hffffffff) {
       sp_value = SP_CANONICAL_NAN;
     }
   }

data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml

@@ -34,4 +34,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_i64(f[fs1], rounding_mode);
+  X[xd] = f32_to_i64(F[fs1], rounding_mode);

data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml

@@ -34,4 +34,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_ui64(f[fs1], rounding_mode);
+  X[xd] = f32_to_ui64(F[fs1], rounding_mode);

data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml

@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = i64_to_f32(X[xs1], rounding_mode);
+  F[fd] = i64_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml

@@ -33,5 +33,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = ui64_to_f32(X[xs1], rounding_mode);
+  F[fd] = ui64_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.s.w.yaml

@@ -41,5 +41,5 @@ data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = i32_to_f32(X[xs1], rounding_mode);
+  F[fd] = i32_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml

@@ -41,5 +41,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = ui32_to_f32(X[xs1], rounding_mode);
+  F[fd] = ui32_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml

@@ -60,4 +60,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = $signed(f32_to_i32(f[fs1], rounding_mode));
+  X[xd] = $signed(f32_to_i32(F[fs1], rounding_mode));

data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml

@@ -59,4 +59,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = $signed(f32_to_ui32(f[fs1], rounding_mode));
+  X[xd] = $signed(f32_to_ui32(F[fs1], rounding_mode));

data/.data/spec/std/isa/inst/F/fdiv.s.yaml

@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_div(f[fs1], f[fs2], mode);
+  F[fd] = f32_div(F[fs1], F[fs2], mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/feq.s.yaml

@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {

data/.data/spec/std/isa/inst/F/fle.s.yaml

@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
   Bits<1> sign_a = sp_value_a[31];
   Bits<1> sign_b = sp_value_b[31];
 

data/.data/spec/std/isa/inst/F/fleq.s.yaml

@@ -32,8 +32,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     # Quiet comparison: only set NV for signaling NaN

data/.data/spec/std/isa/inst/F/flt.s.yaml

@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
   Bits<1> sign_a = sp_value_a[31];
   Bits<1> sign_b = sp_value_b[31];
 

data/.data/spec/std/isa/inst/F/fltq.s.yaml

@@ -32,8 +32,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     # Quiet comparison: only set NV for signaling NaN

data/.data/spec/std/isa/inst/F/flw.yaml

@@ -38,9 +38,9 @@ operation(): |
   Bits<32> sp_value = read_memory(32, virtual_address, $encoding);
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmadd.s.yaml

@@ -35,5 +35,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_addC, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_addC, mode);
   mark_f_state_dirty();