udb 0.1.9 → 0.1.13
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +5 -2
- data/.data/cfgs/mc100-32-full-example.yaml +1 -0
- data/.data/cfgs/profile/README.adoc +10 -0
- data/.data/cfgs/profile/RVA20S64.yaml +26 -6
- data/.data/cfgs/profile/RVA20U64.yaml +18 -4
- data/.data/cfgs/profile/RVA22S64.yaml +27 -7
- data/.data/cfgs/profile/RVA22U64.yaml +18 -4
- data/.data/cfgs/profile/RVA23S64.yaml +61 -7
- data/.data/cfgs/profile/RVA23U64.yaml +36 -4
- data/.data/cfgs/profile/RVB23S64.yaml +27 -7
- data/.data/cfgs/profile/RVB23U64.yaml +18 -4
- data/.data/cfgs/profile/RVI20U32.yaml +10 -4
- data/.data/cfgs/profile/RVI20U64.yaml +10 -4
- data/.data/cfgs/qc_iu.yaml +4 -1
- data/.data/cfgs/rv32-riscv-tests.yaml +2 -1
- data/.data/cfgs/rv32-vector.yaml +2 -1
- data/.data/cfgs/rv64-riscv-tests.yaml +2 -1
- data/.data/cfgs/rv64-vector.yaml +2 -1
- data/.data/spec/custom/isa/qc_iu/csr/Smrnmi/mnepc.yaml +17 -0
- data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml +45 -0
- data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml +39 -0
- data/.data/spec/custom/isa/qc_iu/csr/jvt.yaml +11 -0
- data/.data/spec/custom/isa/qc_iu/csr/mepc.yaml +16 -0
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +219 -0
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmt.yaml +127 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +153 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jalt.yaml +84 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jt.yaml +60 -0
- data/.data/spec/custom/isa/qc_iu/isa/globals.isa +112 -0
- data/.data/spec/schemas/config_schema.json +219 -26
- data/.data/spec/schemas/csr_schema.json +0 -6
- data/.data/spec/schemas/ext_schema.json +80 -24
- data/.data/spec/schemas/inst_schema.json +0 -3
- data/.data/spec/schemas/profile_release_schema.json +1 -1
- data/.data/spec/schemas/profile_schema.json +0 -3
- data/.data/spec/schemas/register_file_schema.json +8 -3
- data/.data/spec/schemas/schema_defs.json +8 -27
- data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfgN.layout +1 -1
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +6 -2
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +6 -2
- data/.data/spec/std/isa/csr/hstatus.yaml +16 -0
- data/.data/spec/std/isa/csr/mcycleh.yaml +1 -1
- data/.data/spec/std/isa/csr/misa.yaml +0 -12
- data/.data/spec/std/isa/csr/mstatus.yaml +38 -0
- data/.data/spec/std/isa/csr/mstatush.yaml +17 -15
- data/.data/spec/std/isa/csr/senvcfg.yaml +16 -0
- data/.data/spec/std/isa/csr/sstatus.yaml +12 -0
- data/.data/spec/std/isa/csr/vsstatus.yaml +24 -0
- data/.data/spec/std/isa/ext/A.yaml +5 -7
- data/.data/spec/std/isa/ext/S.yaml +12 -0
- data/.data/spec/std/isa/ext/Smpmpmt.yaml +52 -0
- data/.data/spec/std/isa/ext/Sv32.yaml +7 -19
- data/.data/spec/std/isa/ext/Sv39.yaml +7 -19
- data/.data/spec/std/isa/ext/Sv48.yaml +4 -20
- data/.data/spec/std/isa/ext/Sv57.yaml +4 -20
- data/.data/spec/std/isa/ext/Svukte.yaml +71 -0
- data/.data/spec/std/isa/ext/Zawrs.yaml +1 -1
- data/.data/spec/std/isa/ext/Zihpm.yaml +0 -12
- data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addi16sp.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.ldsp.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.li.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.sdsp.yaml +1 -1
- data/.data/spec/std/isa/inst/D/fsgnj.d.yaml +3 -0
- data/.data/spec/std/isa/inst/D/fsgnjn.d.yaml +3 -0
- data/.data/spec/std/isa/inst/D/fsgnjx.d.yaml +3 -0
- data/.data/spec/std/isa/inst/F/fadd.s.yaml +5 -5
- data/.data/spec/std/isa/inst/F/fclass.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/feq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fle.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fleq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/flt.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fltq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/flw.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmax.s.yaml +6 -6
- data/.data/spec/std/isa/inst/F/fmin.s.yaml +6 -6
- data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +4 -4
- data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +3 -3
- data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +4 -4
- data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/addi.yaml +1 -1
- data/.data/spec/std/isa/inst/I/addiw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/andi.yaml +1 -1
- data/.data/spec/std/isa/inst/I/beq.yaml +1 -1
- data/.data/spec/std/isa/inst/I/bge.yaml +4 -2
- data/.data/spec/std/isa/inst/I/bgeu.yaml +3 -0
- data/.data/spec/std/isa/inst/I/blt.yaml +4 -2
- data/.data/spec/std/isa/inst/I/bltu.yaml +3 -0
- data/.data/spec/std/isa/inst/I/bne.yaml +1 -1
- data/.data/spec/std/isa/inst/I/slt.yaml +2 -2
- data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sltu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sub.yaml +1 -1
- data/.data/spec/std/isa/inst/I/subw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/xori.yaml +1 -1
- data/.data/spec/std/isa/inst/M/mul.yaml +0 -19
- data/.data/spec/std/isa/inst/Q/fsgnj.q.yaml +1 -1
- data/.data/spec/std/isa/inst/S/sret.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vadd.vv.yaml +1 -5
- data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl1re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl2re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl4re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl8re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vle8.v.yaml +3 -8
- data/.data/spec/std/isa/inst/V/vmand.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmfle.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmflt.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmnand.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsle.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmslt.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsltu.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +2 -13
- data/.data/spec/std/isa/inst/V/vmv.x.s.yaml +1 -1
- data/.data/spec/std/isa/inst/V/vmxnor.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmxor.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vrsub.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vse8.v.yaml +3 -4
- data/.data/spec/std/isa/inst/V/vwadd.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vwaddu.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vxor.vi.yaml +4 -0
- data/.data/spec/std/isa/inst/Zalasr/lSIZE.AQRL.layout +40 -5
- data/.data/spec/std/isa/inst/Zalasr/lb.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lb.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/ld.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/ld.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lh.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lh.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lw.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lw.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/sSIZE.AQRL.layout +46 -5
- data/.data/spec/std/isa/inst/Zalasr/sb.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sb.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sd.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sd.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sh.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sh.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sw.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sw.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zbkb/packw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml +2 -3
- data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +6 -6
- data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +5 -5
- data/.data/spec/std/isa/inst/Zfh/flh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fsh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrc.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrci.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrs.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicsr/csrrsi.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrwi.yaml +1 -1
- data/.data/spec/std/isa/isa/builtin_functions.idl +17 -0
- data/.data/spec/std/isa/isa/fp.idl +1 -5
- data/.data/spec/std/isa/isa/globals.isa +45 -14
- data/.data/spec/std/isa/isa/vec.idl +1 -2
- data/.data/spec/std/isa/manual_version/isa/20240411/isa_20240411.yaml +5 -5
- data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +8 -2
- data/.data/spec/std/isa/param/JVT_BASE_MASK.yaml +1 -1
- data/.data/spec/std/isa/param/MCOUNTINHIBIT_IMPLEMENTED.yaml +25 -0
- data/.data/spec/std/isa/param/MTVEC_MODES.yaml +10 -3
- data/.data/spec/std/isa/param/VLEN.yaml +2 -0
- data/.data/spec/std/isa/profile/RVA20S64.yaml +11 -4
- data/.data/spec/std/isa/profile/RVA20U64.yaml +14 -5
- data/.data/spec/std/isa/profile/RVA22S64.yaml +14 -3
- data/.data/spec/std/isa/profile/RVA22U64.yaml +8 -1
- data/.data/spec/std/isa/profile/RVA23S64.yaml +13 -0
- data/.data/spec/std/isa/profile/RVA23U64.yaml +15 -1
- data/.data/spec/std/isa/profile/RVB23S64.yaml +15 -3
- data/.data/spec/std/isa/profile/RVB23U64.yaml +8 -1
- data/.data/spec/std/isa/profile/RVI20U32.yaml +8 -1
- data/.data/spec/std/isa/profile/RVI20U64.yaml +7 -0
- data/.data/spec/std/isa/register_file/F.yaml +3 -2
- data/.data/spec/std/isa/register_file/V.yaml +2 -2
- data/.data/spec/std/isa/register_file/X.yaml +2 -1
- data/lib/udb/architecture.rb +4 -25
- data/lib/udb/cfg_arch.rb +171 -59
- data/lib/udb/cli.rb +10 -1
- data/lib/udb/condition.rb +38 -37
- data/lib/udb/config.rb +72 -6
- data/lib/udb/logic.rb +29 -56
- data/lib/udb/obj/csr.rb +23 -5
- data/lib/udb/obj/csr_field.rb +36 -21
- data/lib/udb/obj/database_obj.rb +2 -5
- data/lib/udb/obj/extension.rb +0 -3
- data/lib/udb/obj/instruction.rb +1 -4
- data/lib/udb/obj/portfolio.rb +75 -20
- data/lib/udb/obj/profile.rb +0 -4
- data/lib/udb/obj/register_file.rb +63 -2
- data/lib/udb/portfolio_design.rb +3 -6
- data/lib/udb/resolver.rb +84 -23
- data/lib/udb/version.rb +1 -1
- data/lib/udb/version_spec.rb +8 -0
- data/lib/udb/z3.rb +23 -0
- data/lib/udb.rb +0 -3
- metadata +25 -37
- data/.data/cfgs/profile/RVA23M64.yaml +0 -159
- data/.data/cfgs/profile/RVB23M64.yaml +0 -149
- data/.data/spec/schemas/proc_cert_class_schema.json +0 -35
- data/.data/spec/schemas/proc_cert_model_schema.json +0 -336
- data/.data/spec/std/isa/proc_cert_class/AC.yaml +0 -13
- data/.data/spec/std/isa/proc_cert_class/MC.yaml +0 -13
- data/.data/spec/std/isa/proc_cert_class/RVI.yaml +0 -16
- data/.data/spec/std/isa/proc_cert_model/AC100.yaml +0 -72
- data/.data/spec/std/isa/proc_cert_model/AC200.yaml +0 -58
- data/.data/spec/std/isa/proc_cert_model/MC100-32.yaml +0 -155
- data/.data/spec/std/isa/proc_cert_model/MC100-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/MC200-32.yaml +0 -60
- data/.data/spec/std/isa/proc_cert_model/MC200-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/MC300-32.yaml +0 -40
- data/.data/spec/std/isa/proc_cert_model/MC300-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/RVI20-32.yaml +0 -39
- data/.data/spec/std/isa/proc_cert_model/RVI20-64.yaml +0 -19
- data/.data/spec/std/isa/profile/RVA23M64.yaml +0 -24
- data/.data/spec/std/isa/profile/RVB23M64.yaml +0 -86
- data/lib/udb/cert_normative_rule.rb +0 -41
- data/lib/udb/obj/certifiable_obj.rb +0 -21
- data/lib/udb/obj/certificate.rb +0 -230
- data/lib/udb/proc_cert_design.rb +0 -77
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requirements:
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param:
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allOf:
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- name: U_MODE_ENDIANNESS
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equal: little
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- name: S_MODE_ENDIANNESS
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equal: little
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- name: SXLEN
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includes: 64
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- name: UXLEN
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includes: 64
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name: RVA20U64
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long_name: U-mode extensions for version 20 of the 64-bit Apps Processor profile
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marketing_name: RVA20U64
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mode:
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mode: U
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base: 64
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introduction: |
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@@ -21,21 +21,26 @@ extensions:
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$remove: Zifencei # Not allowed as an option for Unpriv ISA (only available in Priv ISA).
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A:
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presence: mandatory
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version: ~> 2.1
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C:
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presence: mandatory
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version: ~> 2.0
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D:
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version: ~> 2.0
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U:
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-
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version: "~> 2.0"
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-
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Zicsr:
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presence: mandatory
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version: "~> 2.0"
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Ziccif:
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- text: |
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Implementations are strongly recommended to raise illegal-instruction
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exceptions on attempts to execute unimplemented opcodes.
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requirements:
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equal: little
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includes: 64
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version: "~> 1.0"
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Sv39:
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presence: mandatory
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version: "~> 1.
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version: "~> 1.0"
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presence: optional
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version: "~> 1.
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version: "~> 1.0"
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presence: optional
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version: "~> 1.
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version: "~> 1.0"
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presence: optional
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version: "~> 1.0"
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@@ -78,3 +78,14 @@ extensions:
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The Sha extension name was introduced in RVA23/RVB23 and wasn't
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in the ratified RVA22 profile but has since been added retroactively
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as a documentation-only change (doesn't affect requirements or functionality).
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requirements:
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param:
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allOf:
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- name: U_MODE_ENDIANNESS
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equal: little
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- name: S_MODE_ENDIANNESS
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equal: little
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- name: SXLEN
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includes: 64
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- name: UXLEN
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includes: 64
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@@ -8,7 +8,7 @@ kind: profile
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name: RVA22U64
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long_name: U-mode extensions for version 22 of the 64-bit Apps Processor profile
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marketing_name: RVA22U64
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-
mode:
|
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+
mode: U
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base: 64
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|
release: { $ref: profile_release/RVA22.yaml# }
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introduction: |
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|
@@ -138,3 +138,10 @@ extra_notes:
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text: |
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The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible
|
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with the profile mandates to support the F and D extensions.
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+
requirements:
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|
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param:
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|
+
allOf:
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- name: U_MODE_ENDIANNESS
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|
+
equal: little
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+
- name: UXLEN
|
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+
includes: 64
|
|
@@ -48,8 +48,21 @@ extensions:
|
|
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48
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|
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|
Ssnpm:
|
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|
presence: mandatory
|
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|
+
version: ~> 1.0
|
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|
# Pointer masking, with *senvcfg*.PME supporting, at minimum
|
|
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53
|
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Sha:
|
|
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|
presence: mandatory
|
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+
version: ~> 1.0
|
|
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|
# collection of Hypervisor extensions
|
|
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|
+
requirements:
|
|
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|
+
param:
|
|
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|
+
allOf:
|
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|
+
- name: U_MODE_ENDIANNESS
|
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|
+
equal: little
|
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- name: S_MODE_ENDIANNESS
|
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|
+
equal: little
|
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65
|
+
- name: SXLEN
|
|
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|
+
includes: 64
|
|
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|
+
- name: UXLEN
|
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|
+
includes: 64
|
|
@@ -8,7 +8,7 @@ kind: profile
|
|
|
8
8
|
name: RVA23U64
|
|
9
9
|
long_name: U-mode extensions for version 23 of the 64-bit Apps Processor profile
|
|
10
10
|
marketing_name: RVA23U64
|
|
11
|
-
mode:
|
|
11
|
+
mode: U
|
|
12
12
|
base: 64
|
|
13
13
|
release: { $ref: profile_release/RVA23.yaml# }
|
|
14
14
|
introduction: |
|
|
@@ -34,21 +34,27 @@ extensions:
|
|
|
34
34
|
|
|
35
35
|
Zfhmin:
|
|
36
36
|
presence: mandatory
|
|
37
|
+
version: ~> 1.0
|
|
37
38
|
|
|
38
39
|
V:
|
|
39
40
|
presence: mandatory
|
|
41
|
+
version: ~> 1.0
|
|
40
42
|
|
|
41
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|
Zvfhmin:
|
|
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44
|
presence: mandatory
|
|
45
|
+
version: ~> 1.0
|
|
43
46
|
|
|
44
47
|
Zvbb:
|
|
45
48
|
presence: mandatory
|
|
49
|
+
version: ~> 1.0
|
|
46
50
|
|
|
47
51
|
Zvkt:
|
|
48
52
|
presence: mandatory
|
|
53
|
+
version: ~> 1.0
|
|
49
54
|
|
|
50
55
|
Supm:
|
|
51
56
|
presence: mandatory
|
|
57
|
+
version: ~> 1.0
|
|
52
58
|
|
|
53
59
|
#--------------------------------------------
|
|
54
60
|
# Zvbc is an expansion option in RVB23U64
|
|
@@ -60,6 +66,7 @@ extensions:
|
|
|
60
66
|
Zvbc:
|
|
61
67
|
presence:
|
|
62
68
|
optional: development
|
|
69
|
+
version: ~> 1.0
|
|
63
70
|
|
|
64
71
|
#########################################################################
|
|
65
72
|
# TRANSITORY EXPANSION extensions in RVA23U64
|
|
@@ -68,3 +75,10 @@ extensions:
|
|
|
68
75
|
#--------------------------------------------
|
|
69
76
|
# (there are no Transitory expansion options in RVA23U64)
|
|
70
77
|
#--------------------------------------------
|
|
78
|
+
requirements:
|
|
79
|
+
param:
|
|
80
|
+
allOf:
|
|
81
|
+
- name: U_MODE_ENDIANNESS
|
|
82
|
+
equal: little
|
|
83
|
+
- name: UXLEN
|
|
84
|
+
includes: 64
|
|
@@ -52,7 +52,7 @@ extensions:
|
|
|
52
52
|
#########################################################################
|
|
53
53
|
Zifencei:
|
|
54
54
|
presence: mandatory
|
|
55
|
-
version: "~>
|
|
55
|
+
version: "~>2.0"
|
|
56
56
|
note: |
|
|
57
57
|
Instruction-Fetch fence instruction.
|
|
58
58
|
|
|
@@ -190,6 +190,7 @@ extensions:
|
|
|
190
190
|
Sha:
|
|
191
191
|
presence:
|
|
192
192
|
optional: expansion
|
|
193
|
+
version: ~> 1.0
|
|
193
194
|
note: |
|
|
194
195
|
The set of augmented hypervisor extensions: H, Ssstateen,
|
|
195
196
|
Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa
|
|
@@ -215,14 +216,14 @@ extensions:
|
|
|
215
216
|
Sv48:
|
|
216
217
|
presence:
|
|
217
218
|
optional: expansion
|
|
218
|
-
version: "~>1.
|
|
219
|
+
version: "~>1.0"
|
|
219
220
|
note: |
|
|
220
221
|
Page-based 48-bit virtual-memory system
|
|
221
222
|
|
|
222
223
|
Sv57:
|
|
223
224
|
presence:
|
|
224
225
|
optional: expansion
|
|
225
|
-
version: "~>1.
|
|
226
|
+
version: "~>1.0"
|
|
226
227
|
note: |
|
|
227
228
|
Page-based 57-bit virtual-memory system
|
|
228
229
|
|
|
@@ -297,3 +298,14 @@ recommendations:
|
|
|
297
298
|
- text: |
|
|
298
299
|
Implementations are strongly recommended to raise illegal-instruction
|
|
299
300
|
exceptions on attempts to execute unimplemented opcodes.
|
|
301
|
+
requirements:
|
|
302
|
+
param:
|
|
303
|
+
allOf:
|
|
304
|
+
- name: U_MODE_ENDIANNESS
|
|
305
|
+
equal: little
|
|
306
|
+
- name: S_MODE_ENDIANNESS
|
|
307
|
+
equal: little
|
|
308
|
+
- name: SXLEN
|
|
309
|
+
includes: 64
|
|
310
|
+
- name: UXLEN
|
|
311
|
+
includes: 64
|
|
@@ -8,7 +8,7 @@ kind: profile
|
|
|
8
8
|
name: RVB23U64
|
|
9
9
|
long_name: U-mode extensions for version 23 of the 64-bit Bespoke Apps Processor profile
|
|
10
10
|
marketing_name: RVB23U64
|
|
11
|
-
mode:
|
|
11
|
+
mode: U
|
|
12
12
|
base: 64
|
|
13
13
|
release: { $ref: profile_release/RVB23.yaml# }
|
|
14
14
|
introduction: |
|
|
@@ -271,3 +271,10 @@ extensions:
|
|
|
271
271
|
#--------------------------------------------
|
|
272
272
|
# (there are no Transitory expansion options in RVB23)
|
|
273
273
|
#--------------------------------------------
|
|
274
|
+
requirements:
|
|
275
|
+
param:
|
|
276
|
+
allOf:
|
|
277
|
+
- name: U_MODE_ENDIANNESS
|
|
278
|
+
equal: little
|
|
279
|
+
- name: UXLEN
|
|
280
|
+
includes: 64
|
|
@@ -8,7 +8,7 @@ kind: profile
|
|
|
8
8
|
name: RVI20U32
|
|
9
9
|
long_name: U-mode extensions for version 20 of a 32-bit processor
|
|
10
10
|
marketing_name: RVI20U32
|
|
11
|
-
mode:
|
|
11
|
+
mode: U
|
|
12
12
|
base: 32
|
|
13
13
|
release: { $ref: profile_release/RVI20.yaml# }
|
|
14
14
|
introduction: |
|
|
@@ -81,3 +81,10 @@ recommendations:
|
|
|
81
81
|
- text: |
|
|
82
82
|
Implementations are strongly recommended to raise illegal-instruction
|
|
83
83
|
exceptions on attempts to execute unimplemented opcodes.
|
|
84
|
+
requirements:
|
|
85
|
+
param:
|
|
86
|
+
allOf:
|
|
87
|
+
- name: U_MODE_ENDIANNESS
|
|
88
|
+
equal: little
|
|
89
|
+
- name: UXLEN
|
|
90
|
+
includes: 32
|
|
@@ -10,3 +10,10 @@ long_name: U-mode extensions for version 20 of a 64-bit processor
|
|
|
10
10
|
$inherits: "profile/RVI20U32.yaml#"
|
|
11
11
|
base: 64
|
|
12
12
|
marketing_name: RVI20U64
|
|
13
|
+
requirements:
|
|
14
|
+
param:
|
|
15
|
+
allOf:
|
|
16
|
+
- name: U_MODE_ENDIANNESS
|
|
17
|
+
equal: little
|
|
18
|
+
- name: UXLEN
|
|
19
|
+
includes: 64
|
|
@@ -1,7 +1,7 @@
|
|
|
1
1
|
# Copyright (c) Animesh Agarwal
|
|
2
2
|
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
3
|
|
|
4
|
-
# yaml-language-server: $schema
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/register_file_schema.json
|
|
5
5
|
|
|
6
6
|
$schema: register_file_schema.json#
|
|
7
7
|
kind: register_file
|
|
@@ -13,7 +13,8 @@ description: |
|
|
|
13
13
|
participates in the standard calling convention defined by the RISC-V ABI spec.
|
|
14
14
|
definedBy: F
|
|
15
15
|
register_class: floating_point
|
|
16
|
-
register_length:
|
|
16
|
+
register_length(): |
|
|
17
|
+
return implemented?(ExtensionName::Q) ? 128 : (implemented?(ExtensionName::D) ? 64 : 32);
|
|
17
18
|
registers:
|
|
18
19
|
- name: f0
|
|
19
20
|
abi_mnemonics: [ft0]
|
|
@@ -1,7 +1,7 @@
|
|
|
1
1
|
# Copyright (c) Animesh Agarwal
|
|
2
2
|
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
3
|
|
|
4
|
-
# yaml-language-server: $schema
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/register_file_schema.json
|
|
5
5
|
|
|
6
6
|
$schema: register_file_schema.json#
|
|
7
7
|
kind: register_file
|
|
@@ -14,7 +14,7 @@ description: |
|
|
|
14
14
|
participate in argument passing or return values.
|
|
15
15
|
definedBy: V
|
|
16
16
|
register_class: vector
|
|
17
|
-
register_length: VLEN
|
|
17
|
+
register_length(): return VLEN;
|
|
18
18
|
registers:
|
|
19
19
|
- name: v0
|
|
20
20
|
caller_saved: true
|
|
@@ -14,11 +14,12 @@ description: |
|
|
|
14
14
|
visible integer state used by the calling convention and execution environment.
|
|
15
15
|
definedBy: I
|
|
16
16
|
register_class: general_purpose
|
|
17
|
-
register_length: MXLEN
|
|
17
|
+
register_length(): return MXLEN;
|
|
18
18
|
registers:
|
|
19
19
|
- name: x0
|
|
20
20
|
abi_mnemonics: [zero]
|
|
21
21
|
roles: [zero]
|
|
22
|
+
reset_value: "0"
|
|
22
23
|
description: |
|
|
23
24
|
Register x0 is hardwired with all bits equal to 0.
|
|
24
25
|
arch_read(): |
|
data/lib/udb/architecture.rb
CHANGED
|
@@ -6,7 +6,7 @@
|
|
|
6
6
|
|
|
7
7
|
# The Architecture class is the API to the architecture database.
|
|
8
8
|
# The "database" contains RISC-V standards including extensions, instructions,
|
|
9
|
-
# CSRs,
|
|
9
|
+
# CSRs, and Profiles.
|
|
10
10
|
# The Architecture class is used by backends to export the information in the
|
|
11
11
|
# architecture database to create various outputs.
|
|
12
12
|
#
|
|
@@ -21,8 +21,6 @@
|
|
|
21
21
|
# Instruction instructions() instruction_hash() instruction(name)
|
|
22
22
|
# Csr csrs() csr_hash() csr(name)
|
|
23
23
|
# Mmr mmrs() mmr_hash() mmr(name)
|
|
24
|
-
# ProcCertClass proc_cert_classes() proc_cert_class_hash() proc_cert_class(name)
|
|
25
|
-
# ProcCertModel proc_cert_models() proc_cert_model_hash() proc_cert_model(name)
|
|
26
24
|
# ProfileFamily profile_families() profile_family_hash() profile_family(name)
|
|
27
25
|
# ProfileRelease profile_releases() profile_release_hash() profile_release(name)
|
|
28
26
|
# Profile profiles() profile_hash() profile(name)
|
|
@@ -48,7 +46,6 @@ require "pathname"
|
|
|
48
46
|
require "sorbet-runtime"
|
|
49
47
|
require "yaml"
|
|
50
48
|
|
|
51
|
-
require_relative "obj/certificate"
|
|
52
49
|
require_relative "obj/csr"
|
|
53
50
|
require_relative "obj/csr_field"
|
|
54
51
|
require_relative "obj/register_file"
|
|
@@ -128,7 +125,7 @@ module Udb
|
|
|
128
125
|
},
|
|
129
126
|
{
|
|
130
127
|
fn_name: "register_file",
|
|
131
|
-
arch_dir: "
|
|
128
|
+
arch_dir: "register_file",
|
|
132
129
|
klass: RegisterFile,
|
|
133
130
|
kind: DatabaseObject::Kind::RegisterFile
|
|
134
131
|
},
|
|
@@ -156,18 +153,6 @@ module Udb
|
|
|
156
153
|
klass: InterruptCode,
|
|
157
154
|
kind: DatabaseObject::Kind::InterruptCode
|
|
158
155
|
},
|
|
159
|
-
{
|
|
160
|
-
fn_name: "proc_cert_class",
|
|
161
|
-
arch_dir: "proc_cert_class",
|
|
162
|
-
klass: ProcCertClass,
|
|
163
|
-
kind: DatabaseObject::Kind::ProcessorCertificateClass
|
|
164
|
-
},
|
|
165
|
-
{
|
|
166
|
-
fn_name: "proc_cert_model",
|
|
167
|
-
arch_dir: "proc_cert_model",
|
|
168
|
-
klass: ProcCertModel,
|
|
169
|
-
kind: DatabaseObject::Kind::ProcessorCertificateModel
|
|
170
|
-
},
|
|
171
156
|
{
|
|
172
157
|
fn_name: "manual",
|
|
173
158
|
arch_dir: "manual",
|
|
@@ -229,7 +214,7 @@ module Udb
|
|
|
229
214
|
def portfolio_classes
|
|
230
215
|
return @portfolio_classes unless @portfolio_classes.nil?
|
|
231
216
|
|
|
232
|
-
@portfolio_classes = profile_families.
|
|
217
|
+
@portfolio_classes = profile_families.sort_by!(&:name).freeze
|
|
233
218
|
end
|
|
234
219
|
|
|
235
220
|
# @return Hash of all portfolio classes defined in the architecture
|
|
@@ -252,7 +237,7 @@ module Udb
|
|
|
252
237
|
def portfolios
|
|
253
238
|
return @portfolios unless @portfolios.nil?
|
|
254
239
|
|
|
255
|
-
@portfolios =
|
|
240
|
+
@portfolios = profiles.sort_by!(&:name)
|
|
256
241
|
end
|
|
257
242
|
|
|
258
243
|
# @return [Hash<String, Portfolio>] Hash of all portfolios defined in the architecture
|
|
@@ -285,12 +270,6 @@ module Udb
|
|
|
285
270
|
obj = T.let(nil, T.untyped)
|
|
286
271
|
obj =
|
|
287
272
|
case file_path
|
|
288
|
-
when /^proc_cert_class.*/
|
|
289
|
-
proc_cert_class_name = File.basename(file_path, ".yaml")
|
|
290
|
-
proc_cert_class(proc_cert_class_name)
|
|
291
|
-
when /^proc_cert_model.*/
|
|
292
|
-
proc_cert_model_name = File.basename(file_path, ".yaml")
|
|
293
|
-
proc_cert_model(proc_cert_model_name)
|
|
294
273
|
when /^csr.*/
|
|
295
274
|
csr_name = File.basename(file_path, ".yaml")
|
|
296
275
|
csr(csr_name)
|