udb 0.1.9 → 0.1.13

data/.data/spec/std/isa/inst/Zalasr/sw.aqrl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sw.aqrl
 long_name: Store Word Acquire Release
 description: |
-  No description available.
+  Store the lowest 32 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has both acquire and release semantics. No subsequent memory
+  operations (in program order) from this hart can be observed to occur before
+  this store completes, and no previous memory operations can be observed to occur
+  after this store completes.
+
+  The address must be naturally aligned (4-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(32, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(32, virtual_address, X[xs2][31:0], $encoding, 1'b1, 1'b1);

data/.data/spec/std/isa/inst/Zalasr/sw.rl.yaml

@@ -11,7 +11,15 @@ kind: instruction
 name: sw.rl
 long_name: Store Word Release
 description: |
-  No description available.
+  Store the lowest 32 bits of register `xs2` to the address in `xs1`.
+
+  This instruction has release semantics, which means that no previous memory
+  operations (in program order) from this hart can be observed to occur after
+  this store completes. Release semantics provide ordering guarantees useful for
+  synchronization, such as writing a lock variable to release it.
+
+  The address must be naturally aligned (4-byte aligned); if not, an
+  address-misaligned or access-fault exception will be raised.
 definedBy:
   extension:
     name: Zalasr
@@ -30,3 +38,10 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  XReg virtual_address = X[xs1];
+
+  if (!is_naturally_aligned(32, virtual_address)) {
+    raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+  }
+
+  write_memory_aligned(32, virtual_address, X[xs2][31:0], $encoding, 1'b0, 1'b1);

data/.data/spec/std/isa/inst/Zbkb/packw.yaml

@@ -32,5 +32,5 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: (xs2 == 0x0)
-    to: zext.h xd,xs1
+    to: zext.h xd, xs1
 operation(): |

data/.data/spec/std/isa/inst/Zcd/c.fld.yaml

@@ -38,4 +38,4 @@ operation(): |
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  f[fd] = sext(read_memory(64, virtual_address, $encoding), 64);
+  F[fd] = sext(read_memory(64, virtual_address, $encoding), 64);

data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  f[fd] = read_memory(64, virtual_address, $encoding);
+  F[fd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  write_memory(64, virtual_address, f[fs2][63:0], $encoding);
+  write_memory(64, virtual_address, F[fs2][63:0], $encoding);

data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  f[fd] = read_memory(32, virtual_address, $encoding);
+  F[fd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml

@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, F[fs2][31:0], $encoding);

data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml

@@ -20,7 +20,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, stack_adj
+assembly: "{reg_list}, stack_adj"
 encoding:
   match: 10111010------10
   variables:

data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml

@@ -20,7 +20,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, stack_adj
+assembly: "{reg_list}, stack_adj"
 encoding:
   match: 10111110------10
   variables:

data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml

@@ -20,7 +20,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, stack_adj
+assembly: "{reg_list}, stack_adj"
 encoding:
   match: 10111100------10
   variables:

data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml

@@ -21,7 +21,7 @@ description: |
 definedBy:
   extension:
     name: Zcmp
-assembly: reg_list, -stack_adj
+assembly: "{reg_list}, -stack_adj"
 encoding:
   match: 10111000------10
   variables:
@@ -30,7 +30,6 @@ encoding:
       not: [0, 1, 2, 3]
     - name: spimm
       location: 3-2
-      left_shift: 4
 access:
   s: always
   u: always
@@ -45,7 +44,7 @@ operation(): |
   XReg nreg = (rlist == 15) ? 13 : (rlist - 3);
   XReg stack_aligned_adj = (nreg * 4 + 15) & ~0xF;
   XReg virtual_address_sp = X[2];
-  XReg virtual_address_new_sp = virtual_address_sp - stack_aligned_adj - spimm;
+  XReg virtual_address_new_sp = virtual_address_sp - stack_aligned_adj - spimm * 16;
   XReg virtual_address_base = virtual_address_sp - (nreg * size);
 
   write_memory_xlen_aligned(virtual_address_base +  0*size, X[ 1], $encoding);

data/.data/spec/std/isa/inst/Zfa/fround.s.yaml

@@ -37,5 +37,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = round_f32_to_integral(f[fs1], rounding_mode);
+  F[fd] = round_f32_to_integral(F[fs1], rounding_mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml

@@ -39,7 +39,7 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<16> hp_value = f[fs1][15:0];
+  Bits<16> hp_value = F[fs1][15:0];
 
   Bits<1> sign = hp_value[15];
   Bits<5> exp = hp_value[14:10];
@@ -50,22 +50,22 @@ operation(): |
       if ((hp_value & 0x0200) != 0) {
         set_fp_flag(FpFlag::NV);
       }
-      f[fd] = HP_CANONICAL_NAN;
+      F[fd] = HP_CANONICAL_NAN;
     } else {
-      f[fd] = packToF32UI(sign, 0xFF, 0);
+      F[fd] = packToF32UI(sign, 0xFF, 0);
     }
   } else {
     if (exp != 0) {
       if (frac != 0) {
-        f[fd] = packToF32UI(sign, 0, 0);
+        F[fd] = packToF32UI(sign, 0, 0);
       } else {
         Bits<6> norm_exp;
         (norm_exp, frac) = softfloat_normSubnormalF16Sig( frac );
         exp = norm_exp - 1;
-        f[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+        F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
       }
     } else {
-      f[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+      F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
     }
   }
 

data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml

@@ -36,7 +36,7 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = f[fs1][31:0];
+  Bits<32> sp_value = F[fs1][31:0];
 
   Bits<1> sign = sp_value[31];
   Bits<8> exp = sp_value[30:23];
@@ -47,9 +47,9 @@ operation(): |
       if ((sp_value & 0x00400000) != 0) {
         set_fp_flag(FpFlag::NV);
       }
-      f[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
+      F[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
     } else {
-      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
     }
   } else {
 
@@ -58,10 +58,10 @@ operation(): |
     # is OR-red with the sticky
     Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
     if ((exp | frac16) == 0) {
-      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
     } else {
       assert(false, "TODO: implement roundPackToF16");
-      # f[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
+      # F[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
     }
 
   }

data/.data/spec/std/isa/inst/Zfh/flh.yaml

@@ -39,6 +39,6 @@ operation(): |
 
   Bits<16> hp_value = read_memory(16, virtual_address, $encoding);
 
-  f[fd] = nan_box(16, FLEN, hp_value);
+  F[fd] = nan_box(16, FLEN, hp_value);
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml

@@ -33,6 +33,6 @@ operation(): |
 
   Bits<16> hp_value = X[xs1][15:0];
 
-  f[fd] = nan_box(16, FLEN, hp_value);
+  F[fd] = nan_box(16, FLEN, hp_value);
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml

@@ -35,4 +35,4 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  X[xd] = sext(f[fs1][15:0], 16);
+  X[xd] = sext(F[fs1][15:0], 16);

data/.data/spec/std/isa/inst/Zfh/fsh.yaml

@@ -40,6 +40,6 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  Bits<16> hp_value = f[fs2][15:0];
+  Bits<16> hp_value = F[fs2][15:0];
 
   write_memory(16, virtual_address, hp_value, $encoding);

data/.data/spec/std/isa/inst/Zicsr/csrrc.yaml

@@ -41,7 +41,7 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrc csr,xs1
+    to: csrc csr, xs1
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 

data/.data/spec/std/isa/inst/Zicsr/csrrci.yaml

@@ -35,7 +35,7 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrci csr,imm
+    to: csrci csr, imm
 operation(): |
   Boolean will_write = imm != 0;
 

data/.data/spec/std/isa/inst/Zicsr/csrrs.yaml

@@ -54,9 +54,9 @@ pseudoinstructions:
   - when: xs1 == 0 && csr == 0xC82
     to: rdinstreth xd
   - when: xs1 == 0
-    to: csrr xd,csr
+    to: csrr xd, csr
   - when: xd == 0
-    to: csrs csr,xs1
+    to: csrs csr, xs1
 operation(): |
   Boolean will_write = xs1 != 0;
 

data/.data/spec/std/isa/inst/Zicsr/csrrsi.yaml

@@ -35,7 +35,7 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrsi csr,imm
+    to: csrsi csr, imm
 operation(): |
   Boolean will_write = imm != 0;
 

data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml

@@ -35,7 +35,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xd == 0
-    to: csrw csr,xs1
+    to: csrw csr, xs1
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 

data/.data/spec/std/isa/inst/Zicsr/csrrwi.yaml

@@ -35,7 +35,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xd == 0
-    to: csrwi csr,imm
+    to: csrwi csr, imm
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 

data/.data/spec/std/isa/isa/builtin_functions.idl

@@ -280,6 +280,23 @@ builtin function ebreak {
   }
 }
 
+builtin function execute_instruction {
+  arguments
+    Bits<32> encoding
+  description {
+    Fetch and execute the instruction with the given 32-bit encoding in the current hart
+    context. The instruction executes as if it were a normal instruction, with the
+    following differences:
+
+    * The PC is not advanced after execution (the calling instruction is responsible
+      for PC management).
+    * If the instruction raises an exception, the exception propagates normally.
+
+    This builtin is intended for use by instructions that dynamically dispatch
+    sub-instructions fetched from memory (e.g., instruction lookup table instructions).
+  }
+}
+
 builtin function prefetch_instruction {
   arguments
     XReg virtual_address     # virtual cache block address

data/.data/spec/std/isa/isa/fp.idl

@@ -9,11 +9,7 @@
 # Files in berkely-softfloat-3 repository are licensed under BSD-3-clause.
 
 # floating point register file
-U32 FLEN = 64; # implemented?(ExtensionName::D) ? 7'd64 : 7'd32;
-Bits<FLEN> f[32] = [0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0];
+U32 FLEN = implemented?(ExtensionName::Q) ? 8'd128 : (implemented?(ExtensionName::D) ? 7'd64 : 7'd32);
 
 # FP constants
 Bits<32> SP_POS_INF       = 32'b0_11111111_00000000000000000000000;

data/.data/spec/std/isa/isa/globals.isa

@@ -327,8 +327,7 @@ function exception_handling_mode {
       } else {
         return PrivilegeMode::M;
       }
-    } else {
-      assert(implemented?(ExtensionName::H) && ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)), "Unexpected mode");
+    } else if (implemented?(ExtensionName::H) && ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) ) {
       if (($bits(CSR[medeleg]) &  (MXLEN'1 << $bits(exception_code))) != 0) {
         if (($bits(CSR[hedeleg]) & (MXLEN'1 << $bits(exception_code))) != 0) {
           return PrivilegeMode::VS;
@@ -339,6 +338,8 @@ function exception_handling_mode {
         # if an exception is not delegated to HS-mode, it can't be delegated to VS-mode
         return PrivilegeMode::M;
       }
+    } else {
+      unreachable();
     }
   }
 }
@@ -717,7 +718,7 @@ function raise_precise {
       $pc = {CSR[mtvec].BASE, 2'b00};
       CSR[mcause].INT = 1'b0;
       CSR[mcause].CODE = $bits(exception_code);
-      if (CSR[misa].H == 1) {
+      if (implemented?(ExtensionName::H) && CSR[misa].H == 1) {
         # write zero into mtval2 and minst
         # (when these are non-zero values, raise_guest_page_fault should be callecd)
         CSR[mtval2].VALUE = 0;
@@ -1196,13 +1197,13 @@ function effective_ldst_mode {
     if (mode() == PrivilegeMode::M) {
       if (CSR[misa].U == 1 && CSR[mstatus].MPRV == 1) {
         if (CSR[mstatus].MPP == 0b00) {
-          if (CSR[misa].H == 1 && mpv() == 0b1) {
+          if (implemented?(ExtensionName::H) && CSR[misa].H == 1 && mpv() == 0b1) {
             return PrivilegeMode::VU;
           } else {
             return PrivilegeMode::U;
           }
         } else if (CSR[misa].S == 1 && CSR[mstatus].MPP == 0b01) {
-          if (CSR[misa].H == 1 && mpv() == 0b1) {
+          if (implemented?(ExtensionName::H) && CSR[misa].H == 1 && mpv() == 0b1) {
             return PrivilegeMode::VS;
           } else {
             return PrivilegeMode::S;
@@ -1532,7 +1533,7 @@ function translate_gstage {
   body {
     TranslationResult result;
 
-    if (effective_mode == PrivilegeMode::S || effective_mode == PrivilegeMode::U) {
+    if (!implemented?(ExtensionName::H) || effective_mode == PrivilegeMode::S || effective_mode == PrivilegeMode::U) {
       # there is no gstage page walk
       result.paddr = gpaddr;
       return result;
@@ -2562,9 +2563,15 @@ function read_memory_aligned {
   arguments
     U32 LEN,
     XReg virtual_address,
-    Bits<INSTR_ENC_SIZE> encoding   # the encoding of an instruction causing this access
+    Bits<INSTR_ENC_SIZE> encoding,  # the encoding of an instruction causing this access
+    Bits<1> aq,                     # acquire semantics? 0=no, 1=yes
+    Bits<1> rl                      # release semantics? 0=no, 1=yes
   description {
     Read from virtual memory using a known aligned address.
+
+    If +rl+ is 1, then the load also acts as a memory model release (applied after all
+    checks pass but before the physical read).
+    If +aq+ is 1, then the load also acts as a memory model acquire (applied after the read).
   }
   body {
     TranslationResult result;
@@ -2578,7 +2585,17 @@ function read_memory_aligned {
     # may raise an exception
     access_check(result.paddr, LEN, virtual_address, MemoryOperation::Read, ExceptionCode::LoadAccessFault, effective_ldst_mode());
 
-    return read_physical_memory(LEN, result.paddr);
+    if (rl == 1'b1) {
+      memory_model_release();
+    }
+
+    XReg value = read_physical_memory(LEN, result.paddr);
+
+    if (aq == 1'b1) {
+      memory_model_acquire();
+    }
+
+    return value;
   }
 }
 
@@ -2597,7 +2614,7 @@ function read_memory {
     XReg physical_address;
 
     if (aligned) {
-      return read_memory_aligned(LEN, virtual_address, encoding);
+      return read_memory_aligned(LEN, virtual_address, encoding, 1'b0, 1'b0);
     }
 
     # access isn't naturally aligned, but it still might be atomic if this hart supports
@@ -2636,7 +2653,7 @@ function read_memory {
       if (MISALIGNED_SPLIT_STRATEGY == "sequential_bytes") {
         XReg result = 0;
         for (U32 I = 0; I < (LEN/8); I++) {
-          result = result | (read_memory_aligned(8, virtual_address + I, encoding) `<< (8*I));
+          result = result | (read_memory_aligned(8, virtual_address + I, encoding, 1'b0, 1'b0) `<< (8*I));
         }
         return result;
       } else if (MISALIGNED_SPLIT_STRATEGY == "custom") {
@@ -2805,7 +2822,7 @@ function load_reserved {
       reservation_virtual_address = virtual_address;
     }
 
-    return read_memory_aligned(N, physical_address, encoding);
+    return read_memory_aligned(N, physical_address, encoding, 1'b0, 1'b0);
   }
 }
 
@@ -2951,9 +2968,15 @@ function write_memory_aligned {
     U32 LEN,
     XReg virtual_address,
     XReg value,
-    Bits<INSTR_ENC_SIZE> encoding # encoding of the instruction causing this access
+    Bits<INSTR_ENC_SIZE> encoding, # encoding of the instruction causing this access
+    Bits<1> aq,                    # acquire semantics? 0=no, 1=yes
+    Bits<1> rl                     # release semantics? 0=no, 1=yes
   description {
     Write to virtual memory using a known aligned address.
+
+    If +rl+ is 1, then the store also acts as a memory model release (applied after all
+    checks pass but before the physical write).
+    If +aq+ is 1, then the store also acts as a memory model acquire.
   }
   body {
     XReg physical_address;
@@ -2965,7 +2988,15 @@ function write_memory_aligned {
     # may raise an exception
     access_check(physical_address, LEN, virtual_address, MemoryOperation::Write, ExceptionCode::StoreAmoAccessFault, effective_ldst_mode());
 
+    if (rl == 1'b1) {
+      memory_model_release();
+    }
+
     write_physical_memory(LEN, physical_address, value);
+
+    if (aq == 1'b1) {
+      memory_model_acquire();
+    }
   }
 }
 
@@ -2983,7 +3014,7 @@ function write_memory {
     XReg physical_address;
 
     if (aligned) {
-      write_memory_aligned(LEN, virtual_address, value, encoding);
+      write_memory_aligned(LEN, virtual_address, value, encoding, 1'b0, 1'b0);
       return;
     }
 
@@ -3022,7 +3053,7 @@ function write_memory {
       # misaligned, must break into multiple reads
       if (MISALIGNED_SPLIT_STRATEGY == "sequential_bytes") {
         for (U32 I = 0; I < (LEN/8); I++) {
-          write_memory_aligned(8, virtual_address + I, (value >> (8*I))[7:0], encoding);
+          write_memory_aligned(8, virtual_address + I, (value >> (8*I))[7:0], encoding, 1'b0, 1'b0);
         }
       } else if (MISALIGNED_SPLIT_STRATEGY == "custom") {
         unpredictable("An implementation is free to break a misaligned access any way, leading to unpredictable behavior when any part of the misaligned access causes an exception");

data/.data/spec/std/isa/isa/vec.idl

@@ -11,8 +11,7 @@
 #   - integer arith (vadd/vsub/vrsub(.vv,.vx,.vi), compare, min, max)
 #   - integer widening arith ()
 
-# the vector register file
-Bits<128> v[32];
+# the vector register file is populated by the symtab from V.yaml
 
 enum VectorLmulType {
   Divide

data/.data/spec/std/isa/manual_version/isa/20240411/isa_20240411.yaml

@@ -85,7 +85,7 @@ volumes:
       - { name: Zicond, version: "1.0.0" }
       - { name: M, version: "2.0.0" }
       - { name: A, version: "2.1.0" }
-      - { name: Zawrs, version: "1.0.1" }
+      - { name: Zawrs, version: "1.0" }
       - { name: Zacas, version: "1.0.0" }
       - { name: Zabha, version: "1.0.0" }
       # - { name: RVWMO, version: "2.0" }
@@ -207,10 +207,10 @@ volumes:
       - { name: Smcdeleg, version: "1.0.0" }
       - { name: S, version: "1.12.0" }
       - { name: Sm, version: "1.12.0" }
-      - { name: Sv32, version: "1.12.0" }
-      - { name: Sv39, version: "1.12.0" }
-      - { name: Sv48, version: "1.12.0" }
-      - { name: Sv57, version: "1.12.0" }
+      - { name: Sv32, version: "1.0" }
+      - { name: Sv39, version: "1.0" }
+      - { name: Sv48, version: "1.0" }
+      - { name: Sv57, version: "1.0" }
       - { name: Svnapot, version: "1.0.0" }
       - { name: Svpbmt, version: "1.0.0" }
       - { name: Svinval, version: "1.0.0" }

data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml

@@ -26,5 +26,11 @@ schema:
   maxItems: 32
   minItems: 32
 definedBy:
-  extension:
-    name: Sm
+  allOf:
+    - extension:
+        name: Sm
+    - param:
+        name: MCOUNTINHIBIT_IMPLEMENTED
+        equal: true
+        reason: |
+          `COUNTINHIBIT_EN` only has effect when the `mcountinhibit` CSR is implemented.

data/.data/spec/std/isa/param/JVT_BASE_MASK.yaml

@@ -23,6 +23,6 @@ schema:
   maximum: 0x7ffffffffffffff # 58 bits
 requirements:
   idl(): |
-    MXLEN == 32 -> JVT_BASE_MASK < 0xffff_ffc0;
+    MXLEN == 32 -> JVT_BASE_MASK <= 0xffff_ffc0;
   reason: |
     Includes the implicitly-zero bits of jvt.BASE, so JVT_BASE_MASK[5:0] must always be 0.

data/.data/spec/std/isa/param/MCOUNTINHIBIT_IMPLEMENTED.yaml

@@ -0,0 +1,25 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/param_schema.json
+
+$schema: param_schema.json#
+kind: parameter
+name: MCOUNTINHIBIT_IMPLEMENTED
+long_name: |
+  Whether or not the `mcountinhibit` CSR is implemented
+description: |
+  Options:
+
+    true::
+      The `mcountinhibit` CSR is implemented and can be accessed in M-mode.
+
+    false::
+      The `mcountinhibit` CSR is not implemented.
+      Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state,
+      depending on TRAP_ON_UNIMPLEMENTED_CSR.
+schema:
+  type: boolean
+definedBy:
+  extension:
+    name: Sm

data/.data/spec/std/isa/param/MTVEC_MODES.yaml

@@ -30,6 +30,13 @@ schema:
   maxItems: 2
   uniqueItems: true
 requirements:
-  idl(): |
-    (MTVEC_ACCESS == "ro") -> ($array_size(MTVEC_MODES) == 1);
-  reason: If `mtvec` is read-only, the mode cannot be changed.
+  # If `mtvec` is read-only, the mode cannot be changed.
+  if:
+    param:
+      name: MTVEC_ACCESS
+      equal: ro
+  then:
+    param:
+      name: MTVEC_MODES
+      size: true
+      equal: 1

data/.data/spec/std/isa/param/VLEN.yaml

@@ -11,6 +11,8 @@ description: |
 long_name: TODO
 schema:
   type: integer
+  minimum: 32
+  maximum: 65536
 #    requirements:
 #      idl(): |
 #        -> (VLEN >= ELEN) && (VLEN <='h10000) && (popcount(VLEN) == 1);