udb 0.1.9 → 0.1.13
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +5 -2
- data/.data/cfgs/mc100-32-full-example.yaml +1 -0
- data/.data/cfgs/profile/README.adoc +10 -0
- data/.data/cfgs/profile/RVA20S64.yaml +26 -6
- data/.data/cfgs/profile/RVA20U64.yaml +18 -4
- data/.data/cfgs/profile/RVA22S64.yaml +27 -7
- data/.data/cfgs/profile/RVA22U64.yaml +18 -4
- data/.data/cfgs/profile/RVA23S64.yaml +61 -7
- data/.data/cfgs/profile/RVA23U64.yaml +36 -4
- data/.data/cfgs/profile/RVB23S64.yaml +27 -7
- data/.data/cfgs/profile/RVB23U64.yaml +18 -4
- data/.data/cfgs/profile/RVI20U32.yaml +10 -4
- data/.data/cfgs/profile/RVI20U64.yaml +10 -4
- data/.data/cfgs/qc_iu.yaml +4 -1
- data/.data/cfgs/rv32-riscv-tests.yaml +2 -1
- data/.data/cfgs/rv32-vector.yaml +2 -1
- data/.data/cfgs/rv64-riscv-tests.yaml +2 -1
- data/.data/cfgs/rv64-vector.yaml +2 -1
- data/.data/spec/custom/isa/qc_iu/csr/Smrnmi/mnepc.yaml +17 -0
- data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml +45 -0
- data/.data/spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml +39 -0
- data/.data/spec/custom/isa/qc_iu/csr/jvt.yaml +11 -0
- data/.data/spec/custom/isa/qc_iu/csr/mepc.yaml +16 -0
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +219 -0
- data/.data/spec/custom/isa/qc_iu/ext/Xqccmt.yaml +127 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +153 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jalt.yaml +84 -0
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmt/qc.cm.jt.yaml +60 -0
- data/.data/spec/custom/isa/qc_iu/isa/globals.isa +112 -0
- data/.data/spec/schemas/config_schema.json +219 -26
- data/.data/spec/schemas/csr_schema.json +0 -6
- data/.data/spec/schemas/ext_schema.json +80 -24
- data/.data/spec/schemas/inst_schema.json +0 -3
- data/.data/spec/schemas/profile_release_schema.json +1 -1
- data/.data/spec/schemas/profile_schema.json +0 -3
- data/.data/spec/schemas/register_file_schema.json +8 -3
- data/.data/spec/schemas/schema_defs.json +8 -27
- data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +8 -8
- data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +4 -4
- data/.data/spec/std/isa/csr/I/pmpcfgN.layout +1 -1
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +6 -2
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +6 -2
- data/.data/spec/std/isa/csr/hstatus.yaml +16 -0
- data/.data/spec/std/isa/csr/mcycleh.yaml +1 -1
- data/.data/spec/std/isa/csr/misa.yaml +0 -12
- data/.data/spec/std/isa/csr/mstatus.yaml +38 -0
- data/.data/spec/std/isa/csr/mstatush.yaml +17 -15
- data/.data/spec/std/isa/csr/senvcfg.yaml +16 -0
- data/.data/spec/std/isa/csr/sstatus.yaml +12 -0
- data/.data/spec/std/isa/csr/vsstatus.yaml +24 -0
- data/.data/spec/std/isa/ext/A.yaml +5 -7
- data/.data/spec/std/isa/ext/S.yaml +12 -0
- data/.data/spec/std/isa/ext/Smpmpmt.yaml +52 -0
- data/.data/spec/std/isa/ext/Sv32.yaml +7 -19
- data/.data/spec/std/isa/ext/Sv39.yaml +7 -19
- data/.data/spec/std/isa/ext/Sv48.yaml +4 -20
- data/.data/spec/std/isa/ext/Sv57.yaml +4 -20
- data/.data/spec/std/isa/ext/Svukte.yaml +71 -0
- data/.data/spec/std/isa/ext/Zawrs.yaml +1 -1
- data/.data/spec/std/isa/ext/Zihpm.yaml +0 -12
- data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addi16sp.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.ldsp.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.li.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
- data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -1
- data/.data/spec/std/isa/inst/C/c.sdsp.yaml +1 -1
- data/.data/spec/std/isa/inst/D/fsgnj.d.yaml +3 -0
- data/.data/spec/std/isa/inst/D/fsgnjn.d.yaml +3 -0
- data/.data/spec/std/isa/inst/D/fsgnjx.d.yaml +3 -0
- data/.data/spec/std/isa/inst/F/fadd.s.yaml +5 -5
- data/.data/spec/std/isa/inst/F/fclass.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/feq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fle.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fleq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/flt.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fltq.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/flw.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmax.s.yaml +6 -6
- data/.data/spec/std/isa/inst/F/fmin.s.yaml +6 -6
- data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +2 -2
- data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +4 -4
- data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +3 -3
- data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +4 -4
- data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
- data/.data/spec/std/isa/inst/F/fsw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/addi.yaml +1 -1
- data/.data/spec/std/isa/inst/I/addiw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/andi.yaml +1 -1
- data/.data/spec/std/isa/inst/I/beq.yaml +1 -1
- data/.data/spec/std/isa/inst/I/bge.yaml +4 -2
- data/.data/spec/std/isa/inst/I/bgeu.yaml +3 -0
- data/.data/spec/std/isa/inst/I/blt.yaml +4 -2
- data/.data/spec/std/isa/inst/I/bltu.yaml +3 -0
- data/.data/spec/std/isa/inst/I/bne.yaml +1 -1
- data/.data/spec/std/isa/inst/I/slt.yaml +2 -2
- data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sltu.yaml +1 -1
- data/.data/spec/std/isa/inst/I/sub.yaml +1 -1
- data/.data/spec/std/isa/inst/I/subw.yaml +1 -1
- data/.data/spec/std/isa/inst/I/xori.yaml +1 -1
- data/.data/spec/std/isa/inst/M/mul.yaml +0 -19
- data/.data/spec/std/isa/inst/Q/fsgnj.q.yaml +1 -1
- data/.data/spec/std/isa/inst/S/sret.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vadd.vv.yaml +1 -5
- data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl1re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl2re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl4re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vl8re8.v.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vle8.v.yaml +3 -8
- data/.data/spec/std/isa/inst/V/vmand.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmfle.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmflt.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmnand.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsle.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsleu.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmslt.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmsltu.vv.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +2 -13
- data/.data/spec/std/isa/inst/V/vmv.x.s.yaml +1 -1
- data/.data/spec/std/isa/inst/V/vmxnor.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vmxor.mm.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vnsrl.wx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vrsub.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vse8.v.yaml +3 -4
- data/.data/spec/std/isa/inst/V/vwadd.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vwaddu.vx.yaml +3 -0
- data/.data/spec/std/isa/inst/V/vxor.vi.yaml +4 -0
- data/.data/spec/std/isa/inst/Zalasr/lSIZE.AQRL.layout +40 -5
- data/.data/spec/std/isa/inst/Zalasr/lb.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lb.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/ld.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/ld.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lh.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lh.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lw.aq.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/lw.aqrl.yaml +17 -1
- data/.data/spec/std/isa/inst/Zalasr/sSIZE.AQRL.layout +46 -5
- data/.data/spec/std/isa/inst/Zalasr/sb.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sb.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sd.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sd.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sh.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sh.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sw.aqrl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zalasr/sw.rl.yaml +16 -1
- data/.data/spec/std/isa/inst/Zbkb/packw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fld.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fldsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcd/c.fsdsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.flwsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcf/c.fswsp.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.pop.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.popret.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.popretz.yaml +1 -1
- data/.data/spec/std/isa/inst/Zcmp/cm.push.yaml +2 -3
- data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fcvt.h.s.yaml +6 -6
- data/.data/spec/std/isa/inst/Zfh/fcvt.s.h.yaml +5 -5
- data/.data/spec/std/isa/inst/Zfh/flh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +1 -1
- data/.data/spec/std/isa/inst/Zfh/fsh.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrc.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrci.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrs.yaml +2 -2
- data/.data/spec/std/isa/inst/Zicsr/csrrsi.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +1 -1
- data/.data/spec/std/isa/inst/Zicsr/csrrwi.yaml +1 -1
- data/.data/spec/std/isa/isa/builtin_functions.idl +17 -0
- data/.data/spec/std/isa/isa/fp.idl +1 -5
- data/.data/spec/std/isa/isa/globals.isa +45 -14
- data/.data/spec/std/isa/isa/vec.idl +1 -2
- data/.data/spec/std/isa/manual_version/isa/20240411/isa_20240411.yaml +5 -5
- data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml +8 -2
- data/.data/spec/std/isa/param/JVT_BASE_MASK.yaml +1 -1
- data/.data/spec/std/isa/param/MCOUNTINHIBIT_IMPLEMENTED.yaml +25 -0
- data/.data/spec/std/isa/param/MTVEC_MODES.yaml +10 -3
- data/.data/spec/std/isa/param/VLEN.yaml +2 -0
- data/.data/spec/std/isa/profile/RVA20S64.yaml +11 -4
- data/.data/spec/std/isa/profile/RVA20U64.yaml +14 -5
- data/.data/spec/std/isa/profile/RVA22S64.yaml +14 -3
- data/.data/spec/std/isa/profile/RVA22U64.yaml +8 -1
- data/.data/spec/std/isa/profile/RVA23S64.yaml +13 -0
- data/.data/spec/std/isa/profile/RVA23U64.yaml +15 -1
- data/.data/spec/std/isa/profile/RVB23S64.yaml +15 -3
- data/.data/spec/std/isa/profile/RVB23U64.yaml +8 -1
- data/.data/spec/std/isa/profile/RVI20U32.yaml +8 -1
- data/.data/spec/std/isa/profile/RVI20U64.yaml +7 -0
- data/.data/spec/std/isa/register_file/F.yaml +3 -2
- data/.data/spec/std/isa/register_file/V.yaml +2 -2
- data/.data/spec/std/isa/register_file/X.yaml +2 -1
- data/lib/udb/architecture.rb +4 -25
- data/lib/udb/cfg_arch.rb +171 -59
- data/lib/udb/cli.rb +10 -1
- data/lib/udb/condition.rb +38 -37
- data/lib/udb/config.rb +72 -6
- data/lib/udb/logic.rb +29 -56
- data/lib/udb/obj/csr.rb +23 -5
- data/lib/udb/obj/csr_field.rb +36 -21
- data/lib/udb/obj/database_obj.rb +2 -5
- data/lib/udb/obj/extension.rb +0 -3
- data/lib/udb/obj/instruction.rb +1 -4
- data/lib/udb/obj/portfolio.rb +75 -20
- data/lib/udb/obj/profile.rb +0 -4
- data/lib/udb/obj/register_file.rb +63 -2
- data/lib/udb/portfolio_design.rb +3 -6
- data/lib/udb/resolver.rb +84 -23
- data/lib/udb/version.rb +1 -1
- data/lib/udb/version_spec.rb +8 -0
- data/lib/udb/z3.rb +23 -0
- data/lib/udb.rb +0 -3
- metadata +25 -37
- data/.data/cfgs/profile/RVA23M64.yaml +0 -159
- data/.data/cfgs/profile/RVB23M64.yaml +0 -149
- data/.data/spec/schemas/proc_cert_class_schema.json +0 -35
- data/.data/spec/schemas/proc_cert_model_schema.json +0 -336
- data/.data/spec/std/isa/proc_cert_class/AC.yaml +0 -13
- data/.data/spec/std/isa/proc_cert_class/MC.yaml +0 -13
- data/.data/spec/std/isa/proc_cert_class/RVI.yaml +0 -16
- data/.data/spec/std/isa/proc_cert_model/AC100.yaml +0 -72
- data/.data/spec/std/isa/proc_cert_model/AC200.yaml +0 -58
- data/.data/spec/std/isa/proc_cert_model/MC100-32.yaml +0 -155
- data/.data/spec/std/isa/proc_cert_model/MC100-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/MC200-32.yaml +0 -60
- data/.data/spec/std/isa/proc_cert_model/MC200-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/MC300-32.yaml +0 -40
- data/.data/spec/std/isa/proc_cert_model/MC300-64.yaml +0 -21
- data/.data/spec/std/isa/proc_cert_model/RVI20-32.yaml +0 -39
- data/.data/spec/std/isa/proc_cert_model/RVI20-64.yaml +0 -19
- data/.data/spec/std/isa/profile/RVA23M64.yaml +0 -24
- data/.data/spec/std/isa/profile/RVB23M64.yaml +0 -86
- data/lib/udb/cert_normative_rule.rb +0 -41
- data/lib/udb/obj/certifiable_obj.rb +0 -21
- data/lib/udb/obj/certificate.rb +0 -230
- data/lib/udb/proc_cert_design.rb +0 -77
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"name": {
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"pattern": "^[A-Z][a-zA-Z0-9_-]*$",
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"description": "The short name of the model, used as a database key"
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"description": "List of in-scope privilege modes for the certificate"
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"extra_notes": {
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}
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},
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"recommendations": {
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},
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"$source": {
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|
@@ -1,13 +0,0 @@
|
|
|
1
|
-
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
-
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
-
|
|
4
|
-
# yaml-language-server: $schema=../../../schemas/proc_cert_class_schema.json
|
|
5
|
-
|
|
6
|
-
$schema: proc_cert_class_schema.json#
|
|
7
|
-
kind: processor certificate class
|
|
8
|
-
processor_kind: Apps Processor
|
|
9
|
-
name: AC
|
|
10
|
-
long_name: Apps Processor Certificate Class
|
|
11
|
-
|
|
12
|
-
introduction: |
|
|
13
|
-
The AC (Apps processor Class) targets processors that support virtual memory and run rich operating systems such as Linux and Android.
|
|
@@ -1,13 +0,0 @@
|
|
|
1
|
-
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
-
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
-
|
|
4
|
-
# yaml-language-server: $schema=../../../schemas/proc_cert_class_schema.json
|
|
5
|
-
|
|
6
|
-
$schema: proc_cert_class_schema.json#
|
|
7
|
-
kind: processor certificate class
|
|
8
|
-
processor_kind: Microcontroller
|
|
9
|
-
name: MC
|
|
10
|
-
long_name: Microcontroller Processor Certificate Class
|
|
11
|
-
|
|
12
|
-
introduction: |
|
|
13
|
-
The MC (Microcontroller Class) targets processors running low-level software on an RTOS or bare-metal.
|
|
@@ -1,16 +0,0 @@
|
|
|
1
|
-
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
-
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
-
|
|
4
|
-
# yaml-language-server: $schema=../../schemas/proc_cert_class_schema.json
|
|
5
|
-
|
|
6
|
-
$schema: proc_cert_class_schema.json#
|
|
7
|
-
kind: processor certificate class
|
|
8
|
-
processor_kind: Generic Unprivileged
|
|
9
|
-
name: RVI
|
|
10
|
-
long_name: RVI Certificate Class
|
|
11
|
-
|
|
12
|
-
introduction: |
|
|
13
|
-
The RVI certificate class corresponds to the RVI Profile Family.
|
|
14
|
-
This certificate class only includes the RISC-V Unprivileged ISA.
|
|
15
|
-
Certificates for the RVI certificate class are intended for internal
|
|
16
|
-
use by the RVCP (RISC-V Certification Program).
|
|
@@ -1,72 +0,0 @@
|
|
|
1
|
-
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
-
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
-
|
|
4
|
-
# yaml-language-server: $schema=../../../schemas/proc_cert_model_schema.json
|
|
5
|
-
|
|
6
|
-
$schema: proc_cert_model_schema.json#
|
|
7
|
-
kind: processor certificate model
|
|
8
|
-
name: AC100
|
|
9
|
-
long_name: AC100 Apps Processor Certificate based on the RVB23 profile release
|
|
10
|
-
class:
|
|
11
|
-
$ref: proc_cert_class/AC.yaml#
|
|
12
|
-
|
|
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# MXLEN used by rakefile
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-
base: 64
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# Semantic versions within the model
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versions:
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- version: "1.0.0"
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revision_history:
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- revision: "0.1.0"
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date: "2025-02-03"
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changes:
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- Created
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25
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introduction: |
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The AC100 Processor Certificate targets RISC-V Apps Processors running rich operating systems such as
|
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custom Yocto Linux.
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Software source code compatibility is a strong requirement and binary compatibility is a lesser requirement.
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AC100 is based on the following:
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* RVB23 Profile without Hypervisor or Vector support
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* M-mode requirements
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* AIA or PLIC interrupt controller
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* Debug and trace (TBD)
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# Specification versions
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tsc_profile_release:
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$ref: profile_release/RVB23.yaml#
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unpriv_isa_manual_revision: "20240411"
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priv_isa_manual_revision: "20240411"
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debug_manual_revision: "1.0.0"
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# Certificate doesn't include hypervisor
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in_scope_priv_modes:
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- U
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- S
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- M
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-
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extensions:
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$inherits:
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- "profile/RVB23M64.yaml#/extensions"
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requirement_groups:
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55
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m_mode_reqs:
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name: M-mode Requirements
|
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description: |
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58
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Extra requirements for M-mode beyond the minimum M-mode defined by the Sm extension.
|
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These extra requirements come from https://github.com/riscv/riscv-profiles/blob/main/src/old-m-profiles.adoc.
|
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requirements:
|
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61
|
-
- name: REQ-M_Mode-Non_Zero_CSRs
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62
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-
description: The `mvendorid`, `marchid`, and `mimpid` CSRs must be nonzero.
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|
63
|
-
- name: REQ-M_Mode-mstatus_writable_fields
|
|
64
|
-
description: The `mstatus.TVM`, `mstatus.TW`, and `mstatus.TSR` CSR fields must be writable.
|
|
65
|
-
- name: REQ-M_Mode-medeleg_writable_bits
|
|
66
|
-
description: The `medeleg` CSR bits 3, 8, 12, 13, and 15 must be writable.
|
|
67
|
-
- name: REQ-M_Mode-mideleg_writable_bits
|
|
68
|
-
description: The `mideleg` CSR bits 1, 5, and 9 must be writable.
|
|
69
|
-
- name: REQ-M_Mode-mideleg_readonlyzero_bits
|
|
70
|
-
description: The `mideleg` CSR bits 3, 7, and 11 must be read-only zero.
|
|
71
|
-
- name: REQ-M_Mode-mcounteren_writable_bits
|
|
72
|
-
description: For any `mhpmcounter` that is writable, the corresponding bit in `mcounteren` must be writable.
|
|
@@ -1,58 +0,0 @@
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|
|
1
|
-
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
-
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
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3
|
-
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|
4
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-
# yaml-language-server: $schema=../../../schemas/proc_cert_model_schema.json
|
|
5
|
-
|
|
6
|
-
$schema: proc_cert_model_schema.json#
|
|
7
|
-
kind: processor certificate model
|
|
8
|
-
name: AC200
|
|
9
|
-
long_name: AC200 Apps Processor Certificate based on the RVA23 profile release
|
|
10
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-
class:
|
|
11
|
-
$ref: proc_cert_class/AC.yaml#
|
|
12
|
-
|
|
13
|
-
# MXLEN used by rakefile
|
|
14
|
-
base: 64
|
|
15
|
-
|
|
16
|
-
# Semantic versions within the model
|
|
17
|
-
versions:
|
|
18
|
-
- version: "1.0.0"
|
|
19
|
-
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|
20
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revision_history:
|
|
21
|
-
- revision: "0.1.0"
|
|
22
|
-
date: "2025-03-07"
|
|
23
|
-
changes:
|
|
24
|
-
- Created
|
|
25
|
-
|
|
26
|
-
introduction: |
|
|
27
|
-
The AC200 Processor Certificate targets RISC-V Apps Processors running rich operating systems such as
|
|
28
|
-
commercial Linux distributions or Android.
|
|
29
|
-
Software source code compatibility and binary compatibility between implementations are strong requirements.
|
|
30
|
-
|
|
31
|
-
AC200 is based on the following:
|
|
32
|
-
|
|
33
|
-
* RVA23 Profile (includes mandatory Hypervisor and Vector support)
|
|
34
|
-
* M-mode requirements
|
|
35
|
-
* AIA or PLIC interrupt controller
|
|
36
|
-
* Debug and trace (TBD)
|
|
37
|
-
|
|
38
|
-
# Specification versions
|
|
39
|
-
tsc_profile_release:
|
|
40
|
-
$ref: profile_release/RVA23.yaml#
|
|
41
|
-
unpriv_isa_manual_revision: "20240411"
|
|
42
|
-
priv_isa_manual_revision: "20240411"
|
|
43
|
-
debug_manual_revision: "1.0.0"
|
|
44
|
-
|
|
45
|
-
in_scope_priv_modes:
|
|
46
|
-
- U
|
|
47
|
-
- S
|
|
48
|
-
- M
|
|
49
|
-
- HS
|
|
50
|
-
- VS
|
|
51
|
-
- VU
|
|
52
|
-
|
|
53
|
-
extensions:
|
|
54
|
-
$inherits:
|
|
55
|
-
- "profile/RVA23M64.yaml#/extensions"
|
|
56
|
-
requirement_groups:
|
|
57
|
-
$inherits:
|
|
58
|
-
- "proc_cert_model/AC100.yaml#/requirement_groups"
|
|
@@ -1,155 +0,0 @@
|
|
|
1
|
-
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
-
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
-
|
|
4
|
-
# yaml-language-server: $schema=../../../schemas/proc_cert_model_schema.json
|
|
5
|
-
|
|
6
|
-
$schema: proc_cert_model_schema.json#
|
|
7
|
-
kind: processor certificate model
|
|
8
|
-
name: MC100-32
|
|
9
|
-
long_name: Basic 32-bit Microcontroller Certificate
|
|
10
|
-
class:
|
|
11
|
-
$ref: proc_cert_class/MC.yaml#
|
|
12
|
-
|
|
13
|
-
# Semantic versions within the model
|
|
14
|
-
versions:
|
|
15
|
-
- version: "1.0.0"
|
|
16
|
-
|
|
17
|
-
# MXLEN used by rakefile
|
|
18
|
-
base: 32
|
|
19
|
-
|
|
20
|
-
in_scope_priv_modes:
|
|
21
|
-
- M
|
|
22
|
-
|
|
23
|
-
# History of this certificate.
|
|
24
|
-
revision_history:
|
|
25
|
-
- revision: "0.9.0"
|
|
26
|
-
date: "2025-10-29"
|
|
27
|
-
changes:
|
|
28
|
-
- |
|
|
29
|
-
Made Zicntr from mandatory to optional since recent published ISA manuals have it as "recommended"
|
|
30
|
-
- revision: "0.8.0"
|
|
31
|
-
date: "2025-01-19"
|
|
32
|
-
changes:
|
|
33
|
-
- Updated so that content can apply equally to all certificate-related documents
|
|
34
|
-
such as CRDs (Certification Requirement Documents) and CTPs (Certification Test Plans).
|
|
35
|
-
- revision: "0.7.0"
|
|
36
|
-
date: "2024-07-29"
|
|
37
|
-
changes:
|
|
38
|
-
- First version after moving non-microcontroller content in this document to a new document
|
|
39
|
-
called "RISC-V CRDs (Certification Requirement Documents)"
|
|
40
|
-
- Change MC100 Unpriv ISA spec from
|
|
41
|
-
"https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
|
|
42
|
-
2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
|
|
43
|
-
former isn't ratified by the latter is the oldest ratified version.
|
|
44
|
-
- Added requirements for WFI instruction
|
|
45
|
-
- Added requirements related to msip memory-mapped register
|
|
46
|
-
- revision: "0.6.0"
|
|
47
|
-
date: "2024-07-11"
|
|
48
|
-
changes:
|
|
49
|
-
- Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
|
|
50
|
-
- Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
|
|
51
|
-
- Added a table showing the mapping from MC version to ISA manuals.
|
|
52
|
-
- Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller
|
|
53
|
-
was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations.
|
|
54
|
-
- Clarified MANDATORY behaviors for mie and mip CSRs
|
|
55
|
-
- Removed canonical discovery recipe because the OPT-* options directly inform the certification
|
|
56
|
-
tests and certification reference model of the status of the various options. Also, canonical
|
|
57
|
-
discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
|
|
58
|
-
potentially illegal values to CSR fields.
|
|
59
|
-
- Added more options for interrupts
|
|
60
|
-
- Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans"
|
|
61
|
-
- revision: "0.5.0"
|
|
62
|
-
date: "2024-06-03"
|
|
63
|
-
changes:
|
|
64
|
-
- Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation
|
|
65
|
-
- Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
|
|
66
|
-
these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet).
|
|
67
|
-
- Added table showing mapping of MC versions to associated RISC-V specifications
|
|
68
|
-
- revision: "0.4.0"
|
|
69
|
-
date: "2024-06-03"
|
|
70
|
-
changes:
|
|
71
|
-
- Added M-mode instruction requirements
|
|
72
|
-
- Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
|
|
73
|
-
- Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
|
|
74
|
-
- revision: "0.3.0"
|
|
75
|
-
date: "2024-05-25"
|
|
76
|
-
changes:
|
|
77
|
-
- Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
|
|
78
|
-
- revision: "0.2.0"
|
|
79
|
-
date: "2024-05-20"
|
|
80
|
-
changes:
|
|
81
|
-
- Very early draft
|
|
82
|
-
- revision: "0.1.0"
|
|
83
|
-
date: "2024-05-16"
|
|
84
|
-
changes:
|
|
85
|
-
- Initial version
|
|
86
|
-
|
|
87
|
-
introduction: |
|
|
88
|
-
The MC100 Processor Certificate targets basic RISC-V microcontrollers.
|
|
89
|
-
It supports either a 32-bit (MC100-32) or 64-bit (MC100-64) base ISA.
|
|
90
|
-
MC100 is not intended for the smallest possible microcontrollers but rather for applications
|
|
91
|
-
benefiting from a minimal but standardized microcontroller. It consists of:
|
|
92
|
-
|
|
93
|
-
* Unprivileged ISA: RV32I for MC100-32 and RV64I for MC100-64 with a few extensions suitable
|
|
94
|
-
for a basic microcontroller.
|
|
95
|
-
* Privileged ISA: Only the M-mode features listed as mandatory in the RISC-V Privileged ISA manual
|
|
96
|
-
|
|
97
|
-
# Specification versions
|
|
98
|
-
tsc_profile_release: null # None for MC100
|
|
99
|
-
unpriv_isa_manual_revision: "20191213"
|
|
100
|
-
priv_isa_manual_revision: "20190608-Priv-MSU-Ratified"
|
|
101
|
-
debug_manual_revision: "0.13.2"
|
|
102
|
-
|
|
103
|
-
# XXX - Remove version information since specifying priv/unpriv ISA manual should imply this.
|
|
104
|
-
extensions:
|
|
105
|
-
I:
|
|
106
|
-
version: "~> 2.1"
|
|
107
|
-
presence: mandatory
|
|
108
|
-
C:
|
|
109
|
-
version: "~> 2.2"
|
|
110
|
-
presence: mandatory
|
|
111
|
-
M:
|
|
112
|
-
version: "~> 2.0"
|
|
113
|
-
presence: optional
|
|
114
|
-
Zicsr:
|
|
115
|
-
version: "~> 2.0"
|
|
116
|
-
presence: mandatory
|
|
117
|
-
Zicntr:
|
|
118
|
-
version: "~> 2.0"
|
|
119
|
-
presence: optional
|
|
120
|
-
Sm:
|
|
121
|
-
version: "~> 1.11.0"
|
|
122
|
-
presence: mandatory
|
|
123
|
-
param_constraints:
|
|
124
|
-
TIME_CSR_IMPLEMENTED: {} # Unconstrained
|
|
125
|
-
MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
|
|
126
|
-
MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained
|
|
127
|
-
ARCH_ID_VALUE: {} # Unconstrained
|
|
128
|
-
IMP_ID_VALUE: {} # Unconstrained
|
|
129
|
-
VENDOR_ID_BANK: {} # Unconstrained
|
|
130
|
-
VENDOR_ID_OFFSET: {} # Unconstrained
|
|
131
|
-
MISA_CSR_IMPLEMENTED: {} # Unconstrained
|
|
132
|
-
MTVAL_WIDTH: {} # Unconstrained
|
|
133
|
-
MTVEC_MODES: {} # Unconstrained
|
|
134
|
-
PHYS_ADDR_WIDTH: {} # Unconstrained
|
|
135
|
-
MISALIGNED_LDST: {} # Unconstrained
|
|
136
|
-
MISALIGNED_LDST_EXCEPTION_PRIORITY: {} # Unconstrained
|
|
137
|
-
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained
|
|
138
|
-
MISALIGNED_SPLIT_STRATEGY:
|
|
139
|
-
schema:
|
|
140
|
-
const: sequential_bytes
|
|
141
|
-
PRECISE_SYNCHRONOUS_EXCEPTIONS:
|
|
142
|
-
schema:
|
|
143
|
-
const: true
|
|
144
|
-
TRAP_ON_ECALL_FROM_M:
|
|
145
|
-
schema:
|
|
146
|
-
const: true
|
|
147
|
-
TRAP_ON_EBREAK:
|
|
148
|
-
schema:
|
|
149
|
-
const: true
|
|
150
|
-
M_MODE_ENDIANNESS:
|
|
151
|
-
schema:
|
|
152
|
-
const: little
|
|
153
|
-
MXLEN:
|
|
154
|
-
schema:
|
|
155
|
-
const: 32
|
|
@@ -1,21 +0,0 @@
|
|
|
1
|
-
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
-
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
-
|
|
4
|
-
# yaml-language-server: $schema=../../../schemas/proc_cert_model_schema.json
|
|
5
|
-
|
|
6
|
-
$schema: proc_cert_model_schema.json#
|
|
7
|
-
kind: processor certificate model
|
|
8
|
-
name: MC100-64
|
|
9
|
-
long_name: Basic 64-bit Microcontroller Certificate
|
|
10
|
-
class:
|
|
11
|
-
$ref: proc_cert_class/MC.yaml#
|
|
12
|
-
|
|
13
|
-
$inherits: "proc_cert_model/MC100-32.yaml#"
|
|
14
|
-
|
|
15
|
-
# MXLEN used by rakefile
|
|
16
|
-
base: 64
|
|
17
|
-
|
|
18
|
-
param_constraints:
|
|
19
|
-
MXLEN:
|
|
20
|
-
schema:
|
|
21
|
-
const: 64
|