udb 0.1.9 → 0.1.13

data/.data/spec/std/isa/inst/F/fmax.s.yaml

@@ -41,8 +41,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
@@ -50,11 +50,11 @@ operation(): |
     }
     # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
     if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
-      f[fd] = SP_CANONICAL_NAN;
+      F[fd] = SP_CANONICAL_NAN;
     } else if (is_sp_nan?(sp_value_a)) {
-      f[fd] = sp_value_b;
+      F[fd] = sp_value_b;
     } else {
-      f[fd] = sp_value_a;
+      F[fd] = sp_value_a;
     }
   } else {
     Boolean sign_a = sp_value_a[31] == 1;
@@ -66,6 +66,6 @@ operation(): |
     } else {
       a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
     }
-    f[fd] = a_lt_b ? sp_value_b : sp_value_a;
+    F[fd] = a_lt_b ? sp_value_b : sp_value_a;
   }
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmin.s.yaml

@@ -41,8 +41,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
@@ -50,11 +50,11 @@ operation(): |
     }
     # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
     if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
-      f[fd] = SP_CANONICAL_NAN;
+      F[fd] = SP_CANONICAL_NAN;
     } else if (is_sp_nan?(sp_value_a)) {
-      f[fd] = sp_value_b;
+      F[fd] = sp_value_b;
     } else {
-      f[fd] = sp_value_a;
+      F[fd] = sp_value_a;
     }
   } else {
     Boolean sign_a = sp_value_a[31] == 1;
@@ -66,6 +66,6 @@ operation(): |
     } else {
       a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
     }
-    f[fd] = a_lt_b ? sp_value_a : sp_value_b;
+    F[fd] = a_lt_b ? sp_value_a : sp_value_b;
   }
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmsub.s.yaml

@@ -35,5 +35,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subC, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_subC, mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmul.s.yaml

@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_mul(f[fs1], f[fs2], mode);
+  F[fd] = f32_mul(F[fs1], F[fs2], mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmv.w.x.yaml

@@ -34,9 +34,9 @@ operation(): |
   Bits<32> sp_value = X[xs1][31:0];
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmv.x.w.yaml

@@ -32,4 +32,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  X[xd] = sext(f[fs1][31:0], 32);
+  X[xd] = sext(F[fs1][31:0], 32);

data/.data/spec/std/isa/inst/F/fnmadd.s.yaml

@@ -38,6 +38,6 @@ operation(): |
   RoundingMode mode = rm_to_mode(rm, $encoding);
   # fnmadd: -(fs1 * fs2) - fs3 = -(fs1 * fs2) + (-fs3)
   # Negate fs3 by flipping its sign bit, then use subProd op
-  Bits<32> fs3_negated = f[fs3][31:0] ^ 32'h80000000;
-  f[fd] = f32_muladd(f[fs1], f[fs2], fs3_negated, F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  Bits<32> fs3_negated = F[fs3][31:0] ^ 32'h80000000;
+  F[fd] = f32_muladd(F[fs1], F[fs2], fs3_negated, F32MulAddOp::Softfloat_mulAdd_subProd, mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fnmsub.s.yaml

@@ -36,5 +36,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_subProd, mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsgnj.s.yaml

@@ -34,17 +34,17 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: (fs2 == fs1)
-    to: fmv.s fd,fs1
+    to: fmv.s fd, fs1
 
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml

@@ -38,12 +38,12 @@ pseudoinstructions:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {~f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {~F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml

@@ -33,16 +33,16 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: (fs2 == fs1)
-    to: fabs.s fd,fs1
+    to: fabs.s fd, fs1
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {f[fs1][31] ^ f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {F[fs1][31] ^ F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsqrt.s.yaml

@@ -31,5 +31,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_sqrt(f[fs1], mode);
+  F[fd] = f32_sqrt(F[fs1], mode);
   mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsub.s.yaml

@@ -33,4 +33,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_sub(f[fs1], f[fs2], mode);
+  F[fd] = f32_sub(F[fs1], F[fs2], mode);

data/.data/spec/std/isa/inst/F/fsw.yaml

@@ -35,4 +35,4 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, F[fs2][31:0], $encoding);

data/.data/spec/std/isa/inst/I/addi.yaml

@@ -33,5 +33,5 @@ pseudoinstructions:
   - when: (xd == 0 && xs1 == 0 && imm == 0)
     to: nop
   - when: imm == 0
-    to: mv xd,xs1
+    to: mv xd, xs1
 operation(): X[xd] = X[xs1] + $signed(imm);

data/.data/spec/std/isa/inst/I/addiw.yaml

@@ -33,6 +33,6 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: imm == 0
-    to: sext.w xd,xs1
+    to: sext.w xd, xs1
 operation(): |
   X[xd] = $signed((X[xs1] + $signed(imm))[31:0]);

data/.data/spec/std/isa/inst/I/andi.yaml

@@ -29,5 +29,5 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: imm == 255
-    to: zext.b xd,xs1
+    to: zext.b xd, xs1
 operation(): X[xd] = X[xs1] & $signed(imm);

data/.data/spec/std/isa/inst/I/beq.yaml

@@ -34,7 +34,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs2 == 0
-    to: beqz xs1,imm
+    to: beqz xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bge.yaml

@@ -34,9 +34,11 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs1 == 0
-    to: blez xs2,imm
+    to: blez xs2, imm
   - when: xs2 == 0
-    to: bgez xs1,imm
+    to: bgez xs1, imm
+  - when: "true"
+    to: ble xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bgeu.yaml

@@ -32,6 +32,9 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: bleu xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/blt.yaml

@@ -34,9 +34,11 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs2 == 0
-    to: bltz xs1,imm
+    to: bltz xs1, imm
   - when: xs1 == 0
-    to: bgtz xs2,imm
+    to: bgtz xs2, imm
+  - when: "true"
+    to: bgt xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bltu.yaml

@@ -32,6 +32,9 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: bgtu xs2, xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/bne.yaml

@@ -34,7 +34,7 @@ access:
   vu: always
 pseudoinstructions:
   - when: xs2 == 0
-    to: bnez xs1,imm
+    to: bnez xs1, imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];

data/.data/spec/std/isa/inst/I/slt.yaml

@@ -31,9 +31,9 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs2 == 0
-    to: sltz xd,xs1
+    to: sltz xd, xs1
   - when: xs1 == 0
-    to: sgtz xd,xs2
+    to: sgtz xd, xs2
 operation(): |
   XReg src1 = X[xs1];
   XReg src2 = X[xs2];

data/.data/spec/std/isa/inst/I/sltiu.yaml

@@ -35,7 +35,7 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: imm == 1
-    to: seqz xd,xs1
+    to: seqz xd, xs1
 operation(): |
   Bits<MXLEN> sign_extend_imm = $signed(imm);
   X[xd] = (X[xs1] < sign_extend_imm) ? 1 : 0;

data/.data/spec/std/isa/inst/I/sltu.yaml

@@ -31,6 +31,6 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs1 == 0
-    to: snez xd,xs2
+    to: snez xd, xs2
 operation(): |
   X[xd] = (X[xs1] < X[xs2]) ? 1 : 0;

data/.data/spec/std/isa/inst/I/sub.yaml

@@ -29,7 +29,7 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs1 == 0
-    to: neg xd,xs2
+    to: neg xd, xs2
 operation(): |
   XReg t0 = X[xs1];
   XReg t1 = X[xs2];

data/.data/spec/std/isa/inst/I/subw.yaml

@@ -33,7 +33,7 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: xs1 == 0
-    to: negw xd,xs2
+    to: negw xd, xs2
 operation(): |
   Bits<32> t0 = X[xs1][31:0];
   Bits<32> t1 = X[xs2][31:0];

data/.data/spec/std/isa/inst/I/xori.yaml

@@ -31,5 +31,5 @@ access:
 data_independent_timing: true
 pseudoinstructions:
   - when: $signed(imm) == -1
-    to: not xd,xs1
+    to: not xd, xs1
 operation(): X[xd] = X[xs1] ^ $signed(imm);

data/.data/spec/std/isa/inst/M/mul.yaml

@@ -50,22 +50,3 @@ operation(): |
   XReg src2 = X[xs2];
 
   X[xd] = (src1 * src2)[MXLEN-1:0];
-
-cert_normative_rules:
-  - id: inst.mul.encoding
-    name: Encoding
-    description: Encoding of `mul` instruction
-    doc_links:
-      - manual:inst:mul:encoding
-  - id: inst.mul.basic_op
-    name: Basic operation
-    description: Basic operation of `mul` instruction
-    doc_links:
-      - manual:inst:mul:operation
-  - id: inst.mul.ill_exc_misa_M_disabled
-    name: Illegal instruction exception when misa.M is 0
-    description: |
-      An illegal instruction exception is raised when the instruction is executed
-      and `misa.M` is 0.
-    doc_links:
-      - manual:csr:misa:disabling-extension

data/.data/spec/std/isa/inst/Q/fsgnj.q.yaml

@@ -32,5 +32,5 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: (fs2 == fs1)
-    to: fmv.q fd,fs1
+    to: fmv.q fd, fs1
 operation(): |

data/.data/spec/std/isa/inst/S/sret.yaml

@@ -133,7 +133,7 @@ operation(): |
     CSR[mstatus].SPIE = 1;
     CSR[mstatus].SPP = 2'b00;
     $pc = $bits(CSR[sepc]);
-  } else {
+  } else if (implemented?(ExtensionName::H)) {
     if (CSR[mstatus].TSR == 1'b1) {
       raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
@@ -141,4 +141,6 @@ operation(): |
     CSR[vsstatus].SIE = CSR[vsstatus].SPIE;
     CSR[vsstatus].SPIE = 1;
     $pc = $bits(CSR[vsepc]);
+  } else {
+    unreachable();
   }

data/.data/spec/std/isa/inst/V/vadd.vv.yaml

@@ -47,11 +47,7 @@ operation(): |
   for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = i * state.sew;
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
-    v[vd] = {
-      v[vd][VLEN-1:end_bit_pos + 1],
-      (v[vs2])[end_bit_pos:start_bit_pos] + (v[vs1])[end_bit_pos:start_bit_pos],
-      v[vd][start_bit_pos-1:0]
-      };
+    V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] + V[vs1][end_bit_pos:start_bit_pos];
   }
 
   CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vfneg.v vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vfabs.v vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl1re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl1r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl2re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl2r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl4re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl4r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vl8re8.v.yaml

@@ -25,5 +25,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vl8r.v vd, (xs1)
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vle8.v.yaml

@@ -31,13 +31,8 @@ data_independent_timing: false
 operation(): |
   XReg virtual_address = X[xs1];
   # "A simple in-order implementation can ignore the settings and simply execute all vector instructions using the undisturbed policy"
-  for (U32 i = 0; i < CSR[vl].VALUE; i++) {
-    U32 start_bit_pos = (CSR[vstart].VALUE + i) * 8;
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * 8;
     U32 end_bit_pos = start_bit_pos + 7;
-    v[vd] = {
-      v[vd][VLEN-1:end_bit_pos + 1],
-      sext(read_memory(8, virtual_address, $encoding), 8),
-      v[vd][start_bit_pos-1:0]
-    };
-    virtual_address = virtual_address + 1;
+    V[vd][end_bit_pos:start_bit_pos] = read_memory(8, virtual_address + i, $encoding)[7:0];
   }

data/.data/spec/std/isa/inst/V/vmand.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vmmv.m vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmfle.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmfge.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmflt.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmfgt.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmnand.mm.yaml

@@ -27,5 +27,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: vs2 == vs1
+    to: vmnot.m vd, vs2
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmsge.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmsgeu.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsle.vi.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmslt.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsle.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsge.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm < 5'b11111
+    to: vmsltu.vi vd, vs2, imm+1, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsleu.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsgeu.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmslt.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsgt.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmsltu.vv.yaml

@@ -29,5 +29,8 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: "true"
+    to: vmsgtu.vv vd, vs1, vs2, vm
 data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/V/vmv.v.i.yaml

@@ -54,19 +54,8 @@ operation(): |
     U32 start_bit_pos = i * state.sew;
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
 
-    # Write the sign-extended immediate (truncated to SEW bits) to the element,
-    # guarding against invalid bit-slice ranges at vector register boundaries
-    if (start_bit_pos == 0) {
-      if (end_bit_pos == VLEN - 1) {
-        v[vd] = sext_imm[state.sew-1:0];
-      } else {
-        v[vd] = {v[vd][VLEN-1:end_bit_pos + 1], sext_imm[state.sew-1:0]};
-      }
-    } else if (end_bit_pos == VLEN - 1) {
-      v[vd] = {sext_imm[state.sew-1:0], v[vd][start_bit_pos-1:0]};
-    } else {
-      v[vd] = {v[vd][VLEN-1:end_bit_pos + 1], sext_imm[state.sew-1:0], v[vd][start_bit_pos-1:0]};
-    }
+    # Write the sign-extended immediate (truncated to SEW bits) to the element
+    V[vd][end_bit_pos:start_bit_pos] = sext_imm[state.sew-1:0];
   }
 
   CSR[vstart].VALUE = 0;